Effective Capacitance Enhancement Methods for 90-nm DRAM Capacitors

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1 Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp Effective Capacitance Enhancement Methods for 90-nm DRAM Capacitors Y. K. Park, Y. S. Ahn, S. B. Kim, K. H. Lee, C. H. Cho, T. Y. Chung and Kinam Kim Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd., Yongin (Received 7 August 2003) For the first time, we successfully demonstrated metal-insulator-semiconductor (MIS) capacitor process integration for 90-nm dynamic random-access memory (DRAM) technology. The robust stack storage node and sufficient cell capacitance for high performance is indispensable for 90-nm DRAM capacitors. In this paper, a novel cell layout and integration technology for 90-nm DRAM capacitors, which can be extended to the next generation DRAM, are proposed and developed for the first time. A diamond-shaped one cylindrical storage node (OCS) with a 1.8-µm stack height is newly developed for a large capacitor area with better stability. Furthermore, a novel Al 2O 3/HfO 2 dielectric material with an equivalent oxide thickness (EOT) of 25 Å is adopted for obtaining sufficient cell capacitance. A reliable cell capacitance and a low leakage current of 26 ff per cell and < 1 fa per cell, respectively, were obtained for a MIS capacitor by using a Al 2O 3/HfO 2 dielectric material. PACS numbers: De Keywords: Capacitor, Diamond-typed OCS, AlO/HfO, DRAM, DMO(Dual Mold Oxide) I. INTRODUCTION As high density and high performance are required for a DRAM (dynamic random access memory) with a COB (capacitor over bit line) structure, cell capacitor technology needs to be developed to provide the required performance [1, 2]. As the minimum feature size of a DRAM decreases, it becomes more difficult to obtain sufficient capacitance for a DRAM cell capacitor. Recently, DRAMs with various cell capacitor structures, which apply to 130-nm and 110-nm DRAM technology, were announced [3 6]. However, in future generations of DRAMs manufactured with sub-0.1-µm technology, difficulties are expected in realizing a sufficient cell capacitance and structural stability because of the remarkable decrease in the cell dimension. In a 90-nm DRAM capacitor, maximization of the cell area and a high-k dielectric material are inevitable for obtaining sufficient cell capacitance. As shown in Fig. 1, a stack height of 1.8 µm and an equivalent oxide thickness (EOT) of 25 Å are inevitable to get 25 ff per cell in the 90-nm design rule. A higher storage node height causes instability of the storage node structure, which results in device failure due to twin-bit or multi-bit failure during DRAM operation [7]. Figure 2 shows the storage node bridge phenomenon due to the instability of the storage node structure. Therefore, the mechanical stability of the storage yk.park@samsung.com; Tel: ; Fax: Fig. 1. Sufficient conditions for obtaining a 25 ff cell capacitance with respect to the design rule. Fig. 2. Storage node bridge phenomenon due to the instability of the storage node structure. node structure is a key factor in increasing the cell capacitance. As reported earlier [6], the MIS Al 2 O 3 capacitor has -112-

2 Effective Capacitance Enhancement Methods for 90-nm DRAM Capacitors Y. K. Park et al Fig. 3. Vertical structure of a fully integrated 512-Mb DRAM using 90-nm process technology. been considered as a promising candidate for future capacitors. However, the EOT of an Al 2 O 3 capacitor for a higher-density DRAM device is limited to an EOT of 33 Å. Therefore, the high-k dielectric material should be developed for next generation DRAMs. In this paper, a novel diamond-shaped cell layout and a landing pad formation technology are proposed to overcome the decrease in the cell capacitance and the mechanical instability, which are inevitable in smallfeature-sized DRAM cells under 90 nm. At the same time, a novel ALD (atomic layer deposition) Al 2 O 3 /HfO 2 double-layer dielectric film with an EOT of 25 Å is introduced for obtaining sufficient cell capacitance for a DRAM cell. Fig. 4. Schematic diagrams of the cell layouts for (a) a conventional OCS and (b) a diamond-shaped OCS. by wet etching lift-off process. Prior to film deposition on a storage node with a cylinder structure, the phosphorus-doped poly-si substrate was nitridated by using rapid thermal nitridation to prevent the oxygen penetration caused by the oxidant during the deposition process. The Al 2 O 3 and the HfO 2 were deposited at 350 C by using an ALD method. The reactant gases were TMA [Al(CH 3 ) 3 ], Hf(OtBu) 4, and O 3 for the oxidant. After the HfO 2 film formation, posttreatment in an oxygen atmosphere was carried out to eliminate the contamination and to cure oxygen defects. As a top electrode, TiN/poly-Si was deposited and activated as a plate. II. EXPERIMENT Figure 3 shows the cross-sectional SEM images of a fully integrated 512-Mb DRAM cell array and its core interface area with 90-nm process technology. First, planar-type cell transistors are formed, which is followed by S/D (source/drain) contact formation by using SAC (self aligned contact) process. After the patterning of BLs (bit lines), storage node (SN) contacts are also formed by using the SAC process [4]. To get a robust capacitor structure for 90-nm DRAM technology, we formed a newly proposed landing pad and diamond-type OCS (one-cylinder-storage-node) type cell capacitor structure to obtain sufficient cell capacitance and mechanical stability. With ArF photolithography, the critical patterns for the landing pad were sharply defined with above 0.3 µm DOF margin. Double oxide layers, such as BPSG (boron phosphorous silicate glass) and PETEOS (plasma enhanced tetra-ethyl-orthosilicate), with different wet etching rates were deposited on the Si 3 N 4 layer that served as the etch stopping layer during the storage node etch process. The double oxide layers were etched by anisotropic etching. The bottom area of the storage node was enlarged due to a different wet etch rate being used during the pre-cleaning process. A 400-Å-thick poly-si was deposited to form the OCS capacitor. The sacrificial oxide, double oxide, is removed III. RESULTS AND DISCUSSION Figure 4 shows a schematic diagram of the newly proposed diamond-shaped SN and landing pad, which enhances the stability of a OCS-type capacitor for a DRAM cell. To maximize the cell area and to enhance the mechanical stability of capacitor, we introduced a novel cell layout. With this layout, the cell area could be increased compared to the conventional cell layout. The cell capacitor structure was composed of a SN contact and a conventional oval-shaped OCS in the design rule over 100 nm. However, a conventional OCS has asymmetries in distance from the nearest OCS in the directions of the bit line and the word line and is mechanically less stable in a special direction. As the minimum feature size of a DRAM cell is decreased below 90 nm, the stability of this conventional OCS structure decreases drastically, which results in a twin-bit failure in the operation of DRAM. Moreover, if we solve the problem of mechanical instability, there are problems such as limited stack height. The overlap of the bottom SN limits the increase in the stack height for the case of a conventional OCS-type structure. In our calculation, the overlap occurred at a stack height of 1.45 µm, as shown in Fig. 5. To overcome the mechanical instability and overlap issue of a conventional OCS

3 -114- Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004 Fig. 5. Overlap margin and limitation of the cell capacitance with the conventional OCS structure. Fig. 7. Cross-sectional SEM image of the landing pad and the bottom cell capacitor structure designed for a DRAM cell with 90-nm technology. Fig. 6. Top-view SEM images of (a) the landing pad and (b) OCS contact after the oxide inside the OCS had been etched out. capacitor, we proposed a diamond-shaped OCS, which needs a landing pad for the connection between the underlying SN contact and the OCS itself. Figure 6 shows top-view SEM images of the (a) landing pad and the (b) OCS contact after the oxide inside the OCS is etched out. With this diamond arrangement, we could eliminate the difficult patterning issue of the conventional layout of storage node, with a rectangular shape. As a result, we could continuously use KrF photolithography to pattern the storage node, even down to 90-nm technology. This structure enhances the process margin from the viewpoint of the structural stability of OCS polycrystalline silicon because the distances from one cylinder to the nearest cylinders are the same. Figure 7 shows a cross-sectional SEM image of the landing pad and bottom cell capacitor structure designed for a DRAM cell with 90-nm technology. The storage node capacitor has a diagonal arrangement whereas the landing pad has an orthogonal arrangement. A special poly pattern is used to connect the cell OCS to the landing pad. Figure 8 shows a cross-sectional SEM image of a robust OCS structure with a stack height of 1.8 µm. For achieving structural stability, we adopted a DMO (dual mold oxide) structure. The DMO structure utilizes the difference in the etch rates between two materials [4]. Fig. 8. Cross-sectional SEM image of a robust OCS structure with a stack height of 1.8 µm. The underlying high etch-rate oxide increases the bottom size of the cylinder, and the cylinder of the DMO structure becomes more stable than that of the SMO (single mold oxide) structure. In this paper, to overcome the extremely high aspect ratio, we changed the combination of BPSG and PETEOS films, and we used special treatments, such as chemical etching for the first and the second DMO materials. Figure 9 shows the twin-bit failure density per 512-Mb DRAM as a function of the capacitor height. The twinbit failure density is greatly increased when the height of stack capacitor is increased. To get reliable cell capacitance, a sufficient capacitor area must be achieved by increasing the stack height. Furthermore, the processinduced heat budget is critical for twin-bit failure. The OCS structure may become unstable as a result of the heat budget at the capacitor dielectric deposition, the pre-deposition treatment, and the post-deposition treatment processes due to the crystallization of SN polycrystalline silicon. By optimizing the deposition process of

4 Effective Capacitance Enhancement Methods for 90-nm DRAM Capacitors Y. K. Park et al Fig. 9. Twin-bit failure density per 512-Mb DRAM as a function of capacitor height. Fig. 12. Trend of the leakage current at 1.2 V of a MIS Al 2O 3/HfO 2 double-layer dielectric capacitor. Fig. 10. Cross-sectional TEM images of (a) an overall 1.8- µm SN in height with a 90-nm feature size and (b) a magnified top-side view of the SN. Fig. 13. Take-off Vp characteristics of an Al 2O 3/HfO 2 capacitor with respect to EOT scale down. Fig. 11. Capacitance distribution and leakage distribution with respect to an EOT scale down of a DRAM cell capacitor with a design rule of 90 nm. SN polycrystalline silicon and adopting a novel capacitor process composed of DMO and a novel diamond-shaped OCS, we could reduce the twin-bit failure density to 25 %, as shown in Fig. 9. Figure 10 shows cross-sectional TEM images of (a) an overall 1.8-µm SN in height with 90-nm feature size and (b) a magnified top-side view of the SN. The step coverage of an ALD Al 2 O 3 /HfO 2 double-layer dielectric with a 1.8-µm OCS height is over 90 %, which is applicable to a DRAM with a 90-nm technology node. The interfaces of Al 2 O 3 /HfO 2 and HfO 2 /TiN were found to be both smooth and sharp, which means that no interfacial reaction was observed. Figure 11(a) shows the capacitance distribution of a DRAM cell capacitor with a design rule of 90 nm. The cell capacitance increases from 23.5 ff to 26 ff per cell by using an optimized ALD Al 2 O 3 /HfO 2 double-layer dielectric film with an EOT of 25Å. Figure 11(b) shows the leakage distribution of a capacitor dielectric film with respect to EOT scale down. The leakage current is less than 1 fa per cell even in EOT 25 Å with a good distribution in the ALD Al 2 O 3 /HfO 2 films for an optimized capacitor process. Therefore, it is possible to reduce the EOT of the Al 2 O 3 /HfO 2 capacitor to around 25 Å while keeping a stable leakage current. Figure 12 shows the trend of the leakage current at 1.2 V for a MIS Al 2 O 3 /HfO 2 double-layer dielectric capacitor. It was possible to reduce the EOT of the

5 -116- Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004 Al 2 O 3 /HfO 2 double-layer in the MIS capacitor to 25 Å with a sub-fa leakage level, which is applicable to a 90-nm design rule DRAM. Figure 13 shows the take-off Vp characteristics of an Al 2 O 3 /HfO 2 capacitor with a respect to EOT scale down. The device functionality can be confirmed by the Vp test for generating a solid 0 10-sec fail bit. The voltage for device operation is sufficient while this takeoff Vp is decreased by 0.2 V for an EOT of 25 Å compared with that for an EOT of 26 Å. IV. CONCLUSIONS In order to form a cell capacitor for a DRAM with a design rule of 90 nm, we proposed and realized diamondshaped OCS layout and landing pad scheme by usingprocesses compatible with previous technology. Moreover, an ALD Al 2 O 3 /HfO 2 double-layer dielectric film was adopted to increase the cell capacitance and to enhance the structural stability. As a result, a cell capacitance of 26 ff per cell, a leakage current less than 1 fa per cell, and a twin-bit failure density of 40 bit per 512-Mb DRAM chip were obtained. REFERENCES [1] Kinam Kim, Chang-Gyu Hwang and Jong-Gil Lee, IEEE Trans. Electron Dev. 45, 598 (1998). [2] Kinam Kim and Moon-Young Jeong, IEEE Trans. Semiconductor Manufacturing 15, 137 (2002). [3] K. N. Kim, H. S. Jeong, W. S. Yang, Y. S. Hwang, C. H. Cho, M. M. Jeong, S. Park, S. J. Ahn, Y. S. Chun, S. H. Shin, J. S. Park, S. H. Song, J. Y. Lee, S. M. Jang, C. H. Lee, J. H. Jeong, M. H. Cho, H. I. Yoon and J. S. Jeon, Symp. on VLSI Tech. (Kyoto, June, 2001), p. 7. [4] Jaegoo Lee, Changhyun Cho, Juyong Lee, Minsang Kim, Jaekyu Lee, Sooho Shin, Donghwa Kwak, Kwanhyeob Koh, Gitae Jeong, Hongsik Jeong, Taeyoung Chung and Kinam Kim, J. Korean Phys. Soc. 41, 487 (2002). [5] K. N. Kim, T. Y. Chung, H. S. Jeong, J. T. Moon, Y. W. Park, G. T. Jeong, K. H. Lee, G. H. Koh, D. W. Shin, Y. S. Hwang, D. W. Kwak, H. S. Uh, D. W. Ha, J. W. Lee, S. H. Shin, M. H. Lee, Y. S. Chun, J. K. Lee, B. J. Park, J. H. Oh, J. G. Lee and S. H. Lee, Symp. on VLSI Tech. (Honolulu, June, 2000), p. 10. [6] H. S. Jeong, W. S. Yang, Y. S. Hwang, C. H. Cho, S. Park, S. J. Ahn, Y. S. Chun, S. H. Shin, S. H. Song, J. Y. Lee, S. M. Jang, C. H. Lee, J. H. Jeong, M. H. Cho, J. K. Lee and Kinam Kim, IEDM Tech. Dig. (San Fransisco, Dec., 2000), p [7] Jeong-Hoon Oh, Hoon Jeong, J. M. Park, J. Y. Park, K. H. Hong, Y. J. Choi, K. H. Lee, T. Y. Chung, Y. J. Park and Kinam Kim, J. Korean Phys. Soc. 41, 884 (2002).