Supporting Information for: Sustained sub-60 mv/decade switching via the negative capacitance effect in MoS 2 transistors

Transcription

1 Supporting Information for: Sustained sub-60 mv/decade switching via the negative capacitance effect in MoS 2 transistors Felicia A. McGuire 1, Yuh-Chen Lin 1, Katherine Price 1, G. Bruce Rayner 2, Sourabh Khandelwal 4, Sayeef Salahuddin 3, and Aaron D. Franklin,1,5* 1 Department of Electrical and Computer Engineering, Duke University, Durham, North Carolina 27708, United States 2 Kurt J. Lesker, Company, Pittsburgh, Pennsylvania 15025, United States 3 Department of Electrical Engineering and Computer Science, University of California - Berkeley, Berkeley, California 94720, United States 4 Department of Science and Engineering, Macquarie University, Australia 5 Department of Chemistry, Duke University, Durham, North Carolina 27708, United States * aaron.franklin@duke.edu 1. 2D NC-FET Fabrication and Characterization 2. Modelling of 2D NC-FET 3. Voltage Gain with Increasing V ds and Repeatability 4. Threshold Voltage Shift 5. Sweep Rate Dependence 6. Energy Dispersive Spectroscopy (EDS) 1

2 1. 2D NC-FET Fabrication and Characterization The process flow schematics for fabricating the 2D negative capacitance field-effect transistors (2D NC-FETs) in this work are found in Fig. S1. Titanium nitride () was grown from a custom-built Kurt J. Lesker plasma-enhanced atomic layer deposition (PE-ALD) cluster system using precursors tetrakis(dimethylamino)titanium(iv) (Ti[N(CH 3 )] 4 ) (TDMAT) and a nitrogen (N 2 )/hydrogen (H 2 ) plasma on an undoped silicon wafer (Fig. S1(a,b)). The ALD chamber was heated to 214 C and the TDMAT precursor to 79 C. The TDMAT had pulse/purge times of 0.5 s/ s. The wafer was then exposed to the plasma for 30 s, followed by a 20 s purge. This was continued for 135 cycles to grow ~ nm. Immediately following deposition, the ALD chamber was heated to 271 C for hafnium zirconium oxide (HfZrO 2, or ) growth. The hafnium precursor tetrakis(dimethylamino)hafnium (Hf(N(CH 3 ) 2 ) 4 ) (TDMAH) was heated to 85 C and the zirconium precursor tetrakis(dimethylamino)zirconium(iv ) (Zr(N(CH 3 ) 2 ) 4 ) (TDMAZ) to 75 C. Water vapor was used for the oxidant to grow the. films were grown in a 1:1 Hf:Zr ratio by alternating cycles of TDMAH, water vapor, TDMAZ, water vapor with pulse/purge times of 0.2 s/ s, 0.14 s/ s, 0.2 s/20 s, 0.14 s/ s, respectively. The alternating cycles were repeated 66 times for 12.3 nm growth or 0 times for 18.6 nm growth (Fig. S1(c)). After completion, the ALD chamber was cooled to 214 C, and the growth was repeated to form the base // metal-ferroelectric-metal (MFM) capacitor of the 2D NC-FET (Fig. S1(d)). 2

3 SiO 2 Si (c) (d) (e) (f) HfO 2 (g) MoS 2 (h) V s V ds V NC Figure S1. Schematic process flow for fabricating 2D NC-FETs including: Si substrate with nm thermally grown SiO 2, ~ nm metallic grown via PE-ALD, (c) 12.3 nm or 18.6 nm ALD-grown ferroelectric layer, (d) ~ nm top metallic layer grown via PE-ALD, (e) patterned and reactive ion etched MFM capacitor, (f) 22.8 nm or 45.7 nm HfO 2 grown with ALD, (g) mechanically exfoliated MoS 2 on HfO 2 gate oxide, and (h) established 25 nm Ni source/drain contacts. Note that the HfO 2 was not selectively grown, but over the entire structure (the schematic shows it only over the MFM capacitor for illustration purposes). The MFM capacitor was patterned with photolithography in photoresist S1805 so that the photoresist remained over the patterned areas. The top layer was etched from the exposed regions surrounding the pattern with a reactive ion etch (RIE) of 36 sccm BCl 3 and 84 sccm Ar in a 0 W inductively coupled plasma (ICP) with 500 W RIE power for 18 s at 70 mtorr. The was then removed with a 90 s buffered oxide etch (BOE), exposing the bottom layer for characterization (Fig. S1(e)), followed by removal of the S1805 resist. Initial polarizationelectric field (P-E) characterization was completed with a Radiant Technologies, Inc. RT66B 3

4 Ferroic Tester, which confirmed the anticipated linear behavior of the unannealed. MFMs were then subject to a rapid thermal anneal (RTA) between C for 30s. P-E characterization was repeated to ensure ferroelectricity. A schematic of the ALD chamber and the P-E characteristics of the films pre- and post-anneal are given in Fig. S2. N 2 Showerhead Ar Plasma Ellipsometer Substrate Heating (c) Polarization (µc/cm 2 ) No Anneal 500 C 550 C 600 C Electric Field (kv/cm) 3000 Figure S2. Schematics of PE-ALD system showing N 2 plasma and Ar carrier gasses and -- MFM capacitor. (c) P-E characteristics of the MFM capacitors before and after annealing at different temperatures. After characterization of the MFM capacitors, -30 nm hafnium oxide (HfO 2 ) was ALD-grown at 225 C from TDMAH and water vapor with pulse/purge times of 0.2 s/ s and 0.14 s/ s, respectively for 150 cycles (12.26 nm) or 300 cycles (45.7 nm) (Fig. S1(f)). Then, MoS 2 was mechanically exfoliated over the patterned regions (Fig. S1(g)). Flakes were optically characterized and thicknesses were confirmed with atomic force microscopy (AFM), with flake thicknesses chosen between ~5-9 nm for device fabrication. Electron beam lithography (EBL) was employed to pattern the contacts, leads, and contact pads in poly(methyl methacrylate) (PMMA) 950 A3 resist, followed by metallization with 25 nm Ni (contacts and leads) or 2 nm Ti, 15 nm Pd, 20 nm Au (contact pads). Lift-off was performed in 80 C heated acetone (Fig. S1(h)). Note that the entirety of the contacts, leads and pads were patterned on top of the MFM 4

5 structures, creating complete overlap with the MFM. While nonideal, this arrangement was used to circumvent leakage between the contacts and the layer at the edge of the MFM structures. The device were electrically characterized with an Agilent (Keysight Technologies) B1500A Semiconductor Parameter Analyzer. As stated in the main text, V NC acted as the gate for 2D NC-FET characterization, and a floating voltage probe was placed on V int to measure voltage gain. For the MoS 2 2D-FET characterization, V int acted as the gate, and the probe on V NC was removed. This allowed for direct comparison of 2D-FET operation with and without the ferroelectric layer, on the same MoS 2 channel. 2. Modelling of 2D NC-FET A 2D NC-FET model was developed to verify the observed threshold voltage shift between the base MoS 2 device (2D-FET) and the corresponding 2D NC-FET. To this end, first the base 2D-FET was modeled as shown in Fig. S3. We used the industry standard BSIM- IMG compact model for modeling the base MoS 2 device. DC transfer characteristics of the 2D- FET were modeled following the standard DC parameter extraction procedure, which yielded an accurate model for channel charge in the device under different bias conditions. Next, the Landau-Khalatnikov (L-K) formulation was used to model the ferroelectric layer. The L-K model has parameters α and β to capture the non-linear ferroelectric behavior, upto second order. α and β can be linked to the ferroelectric parameters: critical electric field (E c ) and remnant polarization (P 0 ) [1]. E c and P 0 were obtained from the measured P-E curve shown in Fig. S2. To calculate the voltage across the ferroelectric layer, the L-K model needs the total charge in the layer. Total charge is the sum of the intrinsic channel charge and the charges in the 5

6 overlap gate-source and gate-drain capacitances. Intrinsic charge can be calculated from the base 2D-FET model and depends on the applied bias and voltage across the ferroelectric layer. This interdependence of voltage across ferroelectric layer and the intrinsic charge is solved selfconsistently in our model. For quantifying the impact of overlap capacitances, we use our selfconsistent model to simulate the 2D NC-FET for different values of overlap capacitances as a percentage of the intrinsic gate capacitance, as shown in Fig. S3(b d). It is seen that, depending on their relative value compared to intrinsic gate capacitance, overlap capacitance affects the subthreshold behavior and the threshold voltage of the device. C ov = 20% C 2D-FET V ds V ds S S HfO 2 D V int HfO 2 D V int V NC C ov = 40% C 2D-FET C ov = 90% C 2D-FET (c) (d) V ds V ds S D S D V int HfO 2 V int HfO 2 V NC V NC Figure S3. 2D-FET simulation (solid line) fit to match experimental data (circles). Simulated 2D NC-FET (solid line) with the overlap capacitance at 20% of the 2D-FET capacitance, plotted with the experimental 2D-FET data and showing slight threshold voltage 6

7 shift. (c) Overlap capacitance increased to 40% with more negatively shifted threshold voltage. (d) Overlap capacitance increased to 90% with significant reduction in SS and large threshold voltage shift. All insets show schematics of simulated device. 3. Voltage Gain with Increasing V ds and Repeatability The defining characteristic of the negative capacitance effect is the internal voltage amplification. While Figures in the manuscript detailed the dependence of hysteresis and SS on V ds, it did not show the internal voltage amplification observed with increasing V ds. In Fig. S4(a,c), we display the subthreshold characteristics of a 2D NC-FET at increasing V ds along with the internal amplification from each of these sweeps. Additionally, Fig. S4(b,d) illustrate the yield and variation present among different 2D NC-FETs on the same chip but with different MoS 2 channels. As is true for MoS 2 devices (2D-FETs) in any geometry, there is a considerable variation from device-to-device in terms of on-state performance and threshold voltage. However, what is encouraging about these 2D NC-FETs is that, despite the presence of this anticipated variation, they all exhibited marked sub-60 mv/dec switching behavior, as shown with the three devices in Fig. S4(b,d) along with the others throughout the manuscript. 7

8 -5 I d (A) L ch = 1 µm V ds = 0 mv V ds = 200 mv V ds = 300 mv V ds = 400 mv I d (A) V ds = 250 mv Flake 1 Flake 2 Flake (c) dv int : dv gs V NC (V) V ds = 0 mv V ds = 200 mv V ds = 300 mv V ds = 400 mv (d) SS (mv/dec) V NC (V) Flake 1 Flake 2 Flake 3 Thermal Limit V gs (V) I d (A) -6 Figure S4. Characterization of additional 2D NC-FETs. Subthreshold curves from the same channel at different V ds and from 200 nm (pink), 500 nm (purple), and 1 µm (green) L ch across different MoS 2 flakes. (c) Increases in the change in V int with respect to V NC (internal voltage gain) for each V ds in. (d) Point-by-point subthreshold swing vs drain current for devices in, showing all devices operate well below the thermal limit. 8

9 4. Threshold Voltage Shift -5-6 I d (A) -7-8 L ch = 500 nm V ds = 1 V 2D-FET 2D NC-FET V gs (V) Figure S5. Comparative hysteretic subthreshold curves for a 2D-FET (green) and corresponding 2D NC-FET (blue), on the same MoS 2 channel, without curve shifting. The considerable shift in V th is attributed to the increased thickness of the HfO 2 and layers along with the overlap capacitance, as discussed in the section above on the modelling of the 2D NC-FET. 5. Sweep Rate Dependence All previous plots of characteristics from 2D NC-FETs have used the same measurement sweep rate for consistency, with each demonstrating sub-60 mv/dec switching. The effects of altering the measurement speed (by increasing the time per measurement) on the NC effect was also studied, as shown in Fig. S6. Here, three hysteretic subthreshold curves are shown where the time for each data point (each measurement) was 6 µs (purple), 8 µs (pink), and µs (blue), as controlled using the B1500 parameter analyzer. Both V th and the hysteresis (measured at I d = -9 A) undergo substantial linear decreases with slight increases in the sweep rate (Fig. S6). While this effect requires further investigation in order to interpret its precise/quantitative origin, it is attributed to interface traps in the gate stack, especially since the sweep rate dependence of hysteresis in a traditional MFM is typically opposite the observation in these devices (hysteresis for MFMs increases with sweep rate). In this case, the small changes in sweep rate explored in 9

10 Fig. S6 may be modulating the impact of interface traps based on the trap charging rates longer voltage pulse duration (slower sweep rate) allows for more traps to charge and thus yields more hysteresis. This has been observed in other nanomaterial-based FETs, where small decreases in the sweep rate yielded significant increases in hysteresis [2]. As nanomaterials offer no surface bonding to their supportive oxide substrate, they tend to be more prone to deleterious interface trap effects such as these Lch = 500 nm Vds = 1 V 6µs 8 µs µs VNC (V) 0 VVthth(V) (V) (A) R = Id 2 Hysteresis (V) = R 16 R 14 = Sweep Rate (Hz) Sweep Sweep Rate Rate (Hz) (Hz) Figure S6. Subthreshold curves from the same device collected at different sweep rates. 6, 8, and µs correspond to the length of time per data point. The decrease in ION found when the time per measurement was 8 µs is attributed to the remnant polarization of the. Top: decreasing hysteresis with increasing sweep rate (faster sweeps). Bottom: decreasing threshold voltage with increasing sweep rate. 6. Energy Dispersive Spectroscopy (EDS) EDS analyses of the device structure was collected (Fig. S7) while obtaining scanning tunneling electron microscopy (STEM) images. The EDS yielded a detailed elemental map to show the distinction between layers and provide evidence for no perceivable diffusion between the critical layers of the gate stack (note, oxygen and nitrogen appear more throughout the spectra because of the presence of these molecules in ambient conditions).

11 MoS2 Ni HfO2 Vds Ni Figure S7. Composite EDS image of the gate stack with Ni contact electrode. The apparent presence of silicon in some regions is because the silicon peak in the EDS spectrum is close to the hafnium peak. (Inset) Schematic of device area where EDS was taken. EDS analysis mapping the locations of each element within the device structure. All elements are mostly confined to their individual layers, except oxygen and nitrogen. The increased proportion of these elements is due to their presence in ambient conditions. References [1] S. Khandelwal et al. "Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics," IEEE Electron Device Letters 38.1 (2017): [2] H. Wang et al., Hysteresis of Electronic Transport in Graphene Transistors, ACS Nano 4.12 (20):