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1 Supporting Online Material for 00-GHz Transistors from Wafer-Scale Epitaxial Graphene Y.-M. Lin,* C. Dimitrakopoulos, K. A. Jenkins, D. B. Farmer, H.-Y. Chiu, A. Grill, Ph. Avouris* *To whom correspondence should be addressed. (Y.-M.L.), (P.A.) This PDF file includes: Materials and Methods SOM Text Figs. S to S6 References Published 5 February 200, Science 327, 662 (200) DOI: 0.26/science.84289

2 Supporting online material for 00 GHz Transistors from Wafer Scale Epitaxial Graphene Y.-M. Lin*, C. Dimitrakopoulos, K. A. Jenkins, D. B. Farmer, H.-Y. Chiu, A. Grill, and Ph. Avouris* *To whom correspondence should be addressed. (P.A.) [Materials and methods] Epitaxial graphene was grown on Si-terminated, high purity semi-insulating (HPSI) 4H(000) SiC wafers in a UHV chamber. The SiC wafer was first cleaned from oxide contamination by annealing at 80 o C under disilane flow (20% disilane in He). Ar flow was then introduced and adjusted to reach a pressure of torr prior to the graphene growth. The SiC wafer was annealed at 450 o C for two minutes to form one to two layers of graphene and cooled down under the Ar flow. The number of active graphene layers was determined by Raman spectroscopy and cross-section TEM to be between one to two layers. Complete growth conditions and characterization can be found in Ref. (S). Both Hall bar devices and RF transistors (Fig. S) were fabricated on the same graphene wafer. The source and drain electrodes were formed by e-beam lithography and lift-off and consisted of Ti/Pd/Au metals (nm/20nm/40nm thick). To define the graphene channel and to isolate individual devices, regions of graphene were etched in an oxygen plasma using poly(methyl methacrylate) (PMMA) as the etch mask. The top-gate dielectrics were deposited using procedures described in detail in Ref. (5). Briefly, a layer of polyhydroxystyrene was spin-coated on the wafer to form a uniform buffer layer with a target thickness of 0 nm. The methyl and hydroxyl groups contained in the polymer provide ideal sites for the subsequent oxide deposition by atomic layer deposition (ALD). This composite dielectric stack possesses a capacitance of about 95 nf/cm 2 (5). Finally, the top-gate electrodes consisting of Ti/Pd/Au metals

3 (nm/20nm/40nm thick) were formed by e-beam lithography and lift-off. The transport measurements were performed at room temperature in ambient environments. [Supplementary Text] The Hall-effect mobility and the field-effect mobility in a top-gated Hall bar device were measured and compared as a function of gate voltage. The Hall-effect mobility was derived by the equation μ H = σ/(e n H ), where σ is the sheet conductivity and n H is the sheet carrier density determined by Hall measurements. The field-effect mobility was obtained by μ FET = dσ dn e dvg dv H G. The carrier mobility values derived from two definitions were in good agreement within 0% (Fig. S2A). Fig. S2B shows the distribution of the carrier mobility measured from ten Hall bar structures across the wafer, with the carrier mobility ranging between 800 and 500 cm 2 /Vs. This mobility distribution across the wafer may lead to performance variations among graphene RF transistors of the same dimension. Graphene RF transistors with two different gate lengths, 550 nm and 240 nm, were fabricated, both having a total channel width of 30 μm including the dual channels. Their dc characteristics were measured using an Agilent semiconductor analyzer 456C. Fig. S3 shows the output and transfer characteristics of a 550-nm-gate graphene transistor. Similar to 240-nm-gate devices (Fig. C in the main text), no clear current saturation was observed up to V D = 2V. For both gate lengths, the graphene FETs exhibited n-type transistor characteristics and reached drive currents of more than ma/μm at V D = 2V. To assess RF characteristics of the graphene FET, on-chip microwave measurements were carried out up to 30 GHz using a HP850 vector network analyzer with groundsignal-ground (GSG) coplanar probes. A standard open, short and load calibration was employed to calibrate the network analyzer, and short and open structures were used to de-embed the signals of the parasitic capacitance and the series resistance associated with the pads and connections. This de-embedding procedure is a well-established standard method and was performed using an "open" test structure without graphene and a "short"

4 test device where the gate, source, and drain electrodes are all connected by metals. The layouts of these open and short structures are strictly identical to that of the active device except in the graphene channel. Fig. S4 shows the measured current gain h 2, after the de-embedding, as a function of frequency f for three 240-nm-gate and nine 550-nm-gate graphene FETs. The current gain h 2 is obtained from measured S parameters and is given by S 2 h 2 =. The current gain h 2 for all devices exhibits the /f (- S) (+ S22) + S2 S2 dependence, where a well-defined cut-off frequency f T can be determined. This /f frequency dependence for current gain h 2 is a well-known feature for Si MOSFETs, and is particularly significant here because it verifies the ac measurement and de-embedding procedures used for extracting the intrinsic high-frequency properties, and further suggests a conventional FET-like behavior for graphene transistors. Based on this observed /f dependence for h 2, the cut-off frequency can also be derived by the product f T = f h 2 at any measurement frequency. On this graphene wafer, the measured cut-off frequency ranged between 20 and 53 GHz for 550-nm-gate graphene FETs, and the f T increased to GHz for 240-nm-gate devices (Fig. S4). The cutoff frequency of a transistor, in principle, can also be estimated from the dc transconductance g m by the relation f T = g m /(2π C G ), where C G is the gate capacitance. For example, for the 240-nm-gate transistor shown in Fig. C, the peak g m is about 4.2 ms at V D = V. For this device, the gate capacitance is estimated from the gate dimensions (240 nm by 30 μm) to be F. This corresponds to a cut-off frequency of 47 GHz at V D = V. Since the transconductance in roughly proportional to the drain bias in these graphene FETs due to the quasi-linear output characteristics, the cut-off frequency at V D = 2V is estimated to be 94 GHz. This estimated performance is in close agreement with the measured f T for this device (Fig. S5). Since there is no clear current saturation behavior in these graphene RF transistors within the drain bias explored, the transconductance of the transistor is proportional to the

5 carrier mobility in the channel material (S2). Thus, the variation of the channel mobility may lead to the f T variations for graphene FETs of the same gate dimension. In addition to the current gain, the graphene FETs also possess power gain (Fig. S6) over a wide frequency range. The maximum frequency f MAX, which corresponds to the highest frequency with non-vanishing power gain, was measured to be 0 GHz and 4 GHz for graphene FETs with f T = 53 GHz and 00 GHz, respectively. Different from f T, f MAX is highly dependent on the device layout and interconnects, including the metal thickness that affects the gate and source/drain resistance (S3). Therefore, f MAX could be further enhanced by decreasing the gate resistance with a thicker metal stack or with a multifinger gate layout. Figures A graphene B source drain metal Top gate source gate graphene Figure S: SEM image of (A) a top-gated Hall bar device and (B) a top-gated field-effect transistor fabricated on the epitaxial graphene wafer. The scale bar in (B) is 2 μm.

6 A Mobility [cm 2 /Vs] Hall mobility FET mobility Vg [V] B 6 Count [#] Mobility [cm 2 /Vs] Figure S2: (A) Measured Hall-effect mobility and field-effect mobility as a function of gate voltage of the same graphene device. (B) The distribution of graphene carrier mobility measured from ten top-gated Hall bar structures on the 2 graphene wafer.

7 A Current [ma/μm] Vg = -3 V to 3V Step V Vd [V] B Drain Current [ma/μm] Vd = V Vg [V] Figure S3: (A) Output characteristics and (B) transfer characteristics of a graphene RF transistor with a gate length of 550 nm.

8 A Current Gain h /f L G = 550 nm 53 GHz Frequency [GHz] 00 B Current Gain h /f Device Device 2 Device 3 L G = 240 nm 00 GHz 0 Frequency [GHz] 00 FIG. S4: Measured current gain h 2 as a function of frequency for (A) nine 550-nm-gatelength graphene FETs and (B) three 240-nm-gate-length graphene FETs. The cut-off frequency ranges between 20 and 53 GHz for 550-nm-gate graphene FETs, and the f T increases to GHz for 240-nm-gate devices. The drain biases were 2 V for all devices except for the device in (B), which was measured at V D = 2.5 V.

9 h V D = 2.5 V V D = 2 V V D = V 00 GHz 0 Frequency [GHz] 00 Figure S5: Measured current gain h 2 as a function of frequency of a 240-nm-gate-length graphene FET at drain biases of, 2, and 2.5 V. The measured cut-off frequency is 55 GHz at V D = V and increases to 00 GHz at 2.5 V.

10 A 00 L G = 550 nm h 2 /2 G MAG Gain 0 f MAX = 4GHz 0 Frequency [GHz] B 00 L G = 240 nm h 2 /2 G MAG Gain 0 f MAX = 0GHz 0 00 Frequency [GHz] Figure S6: Measured power gain (G MAX ) /2 and current gain h 2 as a function of frequency for (A) 550-nm-gate-length and (B) 240-nm-gate-length graphene FETs. G MAX is the maximum available gain derived from S-parameter measurements, and the f MAX is the frequency at which G MAX becomes unity. The measured f MAX are 4 GHz and 0 GHz for graphene FETs possessing f T of 53 GHz (550-nm-gate) and 00 GHz (240- nm-gate), respectively.

11 Reference S. C. Dimitrakopoulos, Y. M. Lin, A. Grill, M. Freitag, Y. Sun, Z. Chen, K. A. Jenkins, D. B. Farmer, Y. Zhu, J. Ott, R. Wisnieff, Ph. Avouris, submitted. S2. Y.-M. Lin, K. A. Jenkins, A. Valdes-Garcia, J. P. Small, D. B. Farmer and Ph. Avouris, Nano Letters 9, 422 (2009) S3. Ali M. Niknejad, Electromagnetics for high-speed analog and digital communication circuits, Chapter 8, published by Cambridge University Press (2007)

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