An Analytical Model for a Gate-Induced-Drain-Leakage Current in a Buried-Channel PMOSFET

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1 Journal of the Korean Physical Society, Vol. 4, No. 5, November 00, pp An Analytical Model for a Gate-Induced-Drain-Leakage Current in a Buried-Channel PMOSFET Seong-Ho Kim, Sung-Eun Kim, Joo-Han Park, Sung-Hoan Kim, Myung-Soo Kim, Jung-Mo Koo, Byung-Sun Kim, Eun-Soo Kim, Soo-Cheol Lee and Chang-Sik Choi LSI Process Architecture, LSI Developnt Team, System-LSI Division, Samsung Electronics Co., Ltd, Yongin Received 7 August 00) The gate-induced-drain-leakage GIDL) current is generally known to originate from the difference between the vertical electric fields at the gate and the drain. When an 1-dinsional model simulation was carried out to analyze this phenonon, a significant difference was found to exist between the 1-dinsional model simulation and the asured GIDL current. In this study, the subthreshold leakage characteristics of a 0.5-µm-design ruled p-type tal-oxide-semiconductor-field emission-transistor MOSFET) were analyzed using simulation modeling with a substrate-biased condition. The results of the fitting revealed that the subthreshold leakage was influenced by the vertical an electrical field between the gate and the drain, as well as by the lateral electrical field between the gate and the substrate. From this result, we could calculate the effect of the effective tunneling-barrier lowering on the band-trap-band tunneling GIDL phenonon due to the lateral electric field, and we confirm that the asured result was well fitted by the calculation. Also, in order to clarify the effect of the lateral field, we monitored the trends of the GIDL current for different spacer lengths. PACS numbers: 85.0.T Keywords: MOSFET, GIDL, PMOS I. INTRODUCTION Minimization of the off-state leakage current in taloxide-silicon MOS) transistors has beca a very important issue with the advent of very low-power, batterybased applications. However, leakage in the drain is an inevitable problem for scaling the MOS transistor toward the deep submicron region. The gate-induceddrain-leakage GIDL) current has been recognized as a major leakage component in off-state MOS transistors. This leakage current is known to be very sensitive to the gate oxide thickness, the drain concentration, the lateral doping gradient, and the applied drain-to-gate voltage. Until now, the origin of the GIDL has been investigated, and nurous models have been suggested to explain that phenonon. Based on a qualitative agreent between experintal results and a theory, a band-to-band tunneling originating from the electrical field between the gate and the drain is considered as the major leakage chanism 1]. Another chanism, in which the doping concentration plays an important role in the subbreakdown phenonon, was suggested, because the previous models could not satisfactorily ex- andrea.kim@samsung.com; Tel: ; Fax: plain the experintal results, such as the I D -V D characteristics ]. More recently, a quasi-two-dinsional quasi--d) model considering both a vertical electric field and a lateral field were proposed in terms of the drain-induced energy-barrier reduction ]. However, to our knowledge, it had the limitations because the quasi- -D model considered only direct tunneling and used a fixed fitting parater. Until now, the proposed models have reported nurous sources of GIDL, such as the thickness of the gate oxide, the drain doping concentration, the lateral drain doping gradients, and the substrate bias. Also, a bandto-band tunneling BTBT) was generally accepted as a tunneling chanism. If above conditions are considered, an explanation based on a -D model is more reasonable than are based on an 1-D model. In this study, in order to find a suitable fitting thod, we proposed a simple -D simulation. Based on this model, we try to simulate and fit our experintal results. II. GIDL MODELING The p-channel MOS drive current was determined to be above 60 µa/µm when a 65-nm spacer length was adopted. Since we used a buried-channel-type PMOS -86-

2 -864- Journal of the Korean Physical Society, Vol. 4, No. 5, November 00 Fig.. Illustration of band bending and electron and hole tunneling in the lateral and the vertical direction to gate poly. 1. Indirect Tunneling Fig. 1. Subthreshold characteristics with different substrate bias, V sub. Since silicon normally shows an indirect tunneling nature, we consider this as 4 6] J t = A ) B B E tot exp, 1) = E vert + E lat, ) where J t is a current density, is an total electric field, A is a pre-exponential constant and B is a tunneling barrier: A = q m r V bend T ox π h V gd V bend), ) Fig.. GIDL characteristics for Fig. 1 with different V dg. without lightly doped drain LDD) implantation, as previously ntioned, it was not difficult to anticipate the large leakage current. Also, this abnormally large leakage current was found to be dominated by the GIDL. Figures 1 and show the asured drain current I d ) as a function of the drain-gate bias V dg ) for biases ranging from 1 to 7 V and as a function of the substrate bias for biases ranging from 0 to V, respectively. As the asured results show, the leakage current significantly increases with the substrate bias. A previous 1-D model predicted that the GIDL current would not vary, regardless of the substrate bias 1]. However, the results of this study show that the drain current is strongly dependent on the substrate-bias condition. To overco this limitation of 1-D model, we propose a modified -D two-step BTBT model with indirect tunneling. B = 4 m 1 r Eg Et). 4) qh where q is the charge of one electron, m r = 0. m 0 a silicon effective mass), T ox is the thickness of oxide, and V bend is the value of band-bending. The electrical field at Si surface is given by ] ɛ si E si Z = W ) = ɛ ox E ox = ɛ ox V gd V fb V bend ) T ox.5) Applying a deep-depletion approximation with Eq. 5), we can express V bend as ] V bend = V gd + qn AToxɛ si ɛ ox V gd + qn AT oxɛ si /ɛ ox V gd, where V gd is sa as V gd V fb. However, since the width of deep depletion is considered to be Å and the depth of the drain doping concentration is about 100 or 00 /cm, the vertical electric field is determined by the electric field at Si E si ) within the deep depletion region.. Lateral Field Chang et al. reported a two-step tunneling process considering electron-hole tunneling in both the x- direction and y-direction; however, electron tunneling 6)

3 An Analytical Model for a Gate-Induced-Drain-Leakage Current Seong-Ho Kim et al mainly occurs in x-direction, as shown in Fig. 7]. According to the Fermi Golden Rule, the dependence of electron ti constant τ e ) and hole ti constant τ h ) on electric field, E t, at the trap level is given by τ e = τ 0c exp8π/hm e / E c E t ) / /q ], τ h = τ 0v exp8π/hm h / E t E v ) / /qe l ], 7) where m e and m h are the effective masses for the electron and the hole, respectively and conduction τ 0c and valence τ 0v are the effective transit tis in the conduction band and in the valence band, respectively. When an electric field is sufficiently large, the tunneling process is more dominant than the thermal conduction process. In such a case, the ti τ e is approximately the sa as τ h. Therefore, from Eq. 7), we can obtain the energy level of interface traps which are most effective in the two-step tunneling process. E t = E v + m h E l Ec ] / 1 + m h E l ], 8) where E l and are the lateral and the total electric field, respectively. If the abrupt junction approximation is used, the lateral field, E l, can be expressed as qn b V bi + V db ) E l =. 9) ɛ si Substituting Eq. ) to Eq. 8), we obtained the effective tunneling barrier, B, B = B 0 / 1 + m r E l ], B 0 = 4 m 1 r Eg). 10) qh. Fitting Parater We simulate the leakage current, I d, using the above relations: I d = F J t, 11) area where F is a fitting parater to compensate for an approximated overlap region. In this work, since the field distribution changed with V dg, a modified lateral field, E l = KE l, was applied. K is a fitting parater for the electric field. was grown to 4 nm. Then a gate-poly reoxidation, resulting in a 10-nm oxide asured from silicon), was carried out. After the definition of the gate poly, a 10-nm oxide layer was deposited using chemical-vapor-deposition and a 65 to 80-nm Si N 4 layer was deposited using lowpressure CVD. These layers were then etched to form sidewall spacer. Both the source and the drain were implanted with 0-KeV BF + ions at the dose of cm. The dopants were annealed in nitrogen at 975 C for 10 sec. After tallization, the wafers were sintered in hydrogen at 400 C for 40 min. Since it is generally known that the effect of the source on the GIDL can be disregarded, a asurent was carried out using - terminal points, such as the drain-gate-substrate point. Figure 4 compares the asured and the simulated results for the subthreshold characteristics. We found that the fitting results based on our simulated model fitted the experintal results well whereas those based on Endoh s model did not. Since Endoh s model mainly used a fixed tunneling value, 1. MV/cm, the effect of III. RESULTS AND DISCUSSION An n-poly gate p-channel MOS device was fabricated with a gate length of 0.5 µm without LDD. A buriedchannel PMOS was used in this study. The starting materials were boron-doped, 100)-oriented Si wafers with a resistivity Ωcm. The gate-oxide thickness, t ox, Fig. 4. Measured and simulated results for the subthreshold characteristics.

4 -866- Journal of the Korean Physical Society, Vol. 4, No. 5, November 00 Fig. 5. Measured and simulated results for the subthreshold characteristics with different substrate biases, V sub. Fig. 7. Results of Simulation result region using T- SUPREMR IV for the gate-to-drain overlap region. Fig. 6. Measured and simulated results for different spacer widths. Fig. 8. Simulation results for the lateral electric fields for different spacer widths. the lateral field was disregarded in their model. The asured subthreshold characteristics for different substrate biases, V sub, are also consistent with the simulated results, as shown in Fig. 5. Figure 6 shows the GIDL in PMOS for different spacer widths. The leakage current decreased with increasing the spacer width. Ghodsi et al. explained that this phenonon is due to a reduction in the P+ drain-to-gate overlap region and, hence, to the smaller area under the gate 8]. In this study, we tried to consider the effect of the lateral field on the GIDL for different spacer widths. Figure 7 shows the simulated results of overlap region width with different spacer length. The simulation was carried out using the T-SUPREM program. From the results, the overlap region widths for 65-nm and 80-nm spacer lengths were 0 nm and 45 nm, respectively. The GIDL simulation result, considering only the overlap region area, is shown in Fig. 6. A significant mismatch was found to exist between the simulated and the asured results. For more consideration, the lateral field along the x-direction was calculated, and the result is shown in Fig. 8. The lateral field for 65-nm and 80-nm spacer widths was determined to be 0.6 and 0.4 MV/cm when the highest vertical electric field is applied to transistor. The ratio of these values is very similar with that of the fitting paraters, K, adopted in this study. From this result, we concluded that the influence of the lateral field is important in reducing the GIDL current. REFERENCES

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