MaxCaps Next Generation Dielectrics for Integrated Capacitors

Transcription

1 MaxCaps Next Generation Dielectrics for Integrated Capacitors Guenther Ruhl Infineon Technologies AG Σ! 2365 Semicon Europa 2011 Dresden, October 11, 2011 October 11,

2 Outline Introduction MaxCaps Project Overview Selected results DRAM capacitors RF/decoupling capacitors High voltage capacitors Summary October 11,

3 MaxCaps: Overview MAterials for next generation CAPacitors and memories Project Framework: MEDEA+ Duration: Q1/08 Q3/11 Objective Address complete value chain for targeted applications Precursor modelling, development & delivery Equipment & process development Application process module development October 11,

4 MaxCaps: Goals Develop capacitor modules consisting of ultra high-k materials and metal electrodes in future memory and capacitor applications Targeted deposition methods WP1: ALD / PEALD WP2: MOCVD / AVD Targeted Applications WP3: DRAM storage capacitors WP4: Planar BEOL capacitors (RF, decoupling, high voltage) WP5: Trench capacitors for SiP interposers Develop Phase-change Memory modules based on ALD material WP6: GeSbTe/SbTe based cells including electrodes October 11,

5 MaxCaps: Consortium October 11,

6 Capacitor requirements RF capacitors ITRS Roadmap 2009/2010 C f 7 J leak <10-8 A/cm² DRAM capacitors EOT J leak <10-7 A/cell October 11,

7 Capacity enhancement Capacity determined by several factors C 0 k optimization potential A d limited by trench geometry (etch process) limited by U bd /E bd October 11,

8 C f [ff/µm²] Film thickness [nm] E bd [MV/cm] Boundary conditions Specific capacity C f & film thickness determined by k J. McPherson et al., IEDM `02 Digest (2002) 633. SiO2 Al2O3 Ta2O5 ZrO2 SrTa2O6 SrTiO3 Si3N4 HfO2 La2O3 Pr2O3 TiO U bd = 15 V k Cf film thickness k October 11,

9 Dielectric material screening Target Dielectric thin film material with k >50 Film thickness up to >100 nm Excellent step coverage for trench capacitors Material screening Literature research 14 dielectric materials / material stacks evaluated 5 electrode materials evaluated Planar MIM capacitors Deposition methods AVD (MOCVD) ALD October 11,

10 J 1V [A/cm²] Dielectric material screening Leakage current 1 V J leak < 10-7 k < E E E E E E E E E E E k SrTiO/Au,Pt SrTiO/TiN,TaN PESrTiO/Au,Pt PESrTiO/TiN,TaN SrTiO&Al2O3/Au,Pt SrTiO&Al2O3/TiN,TaN SrTiO&SrTaO/Au,Pt SrTiO&SrTaO/TiN,TaN SrTiO&SrO/Au,Pt SrTiO&SrO/TiN,TaN BaSrTiO/Au,Pt BaSrTiO/TiN,TaN BaSrTiO&Al2O3/Au,Pt BaSrTiO&Al2O3/TiN,TaN BaTiO/Au,Pt BaTiO/TiN,TaN SrTaO/Au,Pt SrTaO/TiN,TaN TiTaO/Au,Pt TiTaO/TiN,TaN NbTaO/Au,Pt NbTaO/TiN,TaN AlTiO2&Al2O3/TiN,TaN CeAlO/Au,Pt CeAlO/TiN,TaN October 11,

11 DRAM capacitors Test device ALD SrTiO 3 /TiO x RuO x, TiN electrodes Planar device on 300 mm wafer M.A. Pawlak et al., IEEE IEDM 2010 (2010) 277. October 11,

12 DRAM capacitors J leak vs EOT M.A. Pawlak et al., IEEE IEDM 2010 (2010) 277. October 11,

13 DRAM capacitors Achievements Record low J leak = 10-6 /10-8 A/cm² at 0.4/0.5 nm EOT Low-roughness Ru oxidation process Small crystallite size of Sr-rich STO maintained by TiO x layer intermixing : high k (~85) at low J leak October 11,

14 J 3V [A/cm²] Dielectric material screening Leakage current >1 V J leak <10-7 k < E E E E E E E E E E E k SrTiO/Au,Pt SrTiO/TiN,TaN PESrTiO/Au,Pt PESrTiO/TiN,TaN SrTiO&Al2O3/Au,Pt SrTiO&Al2O3/TiN,TaN SrTiO&SrTaO/Au,Pt SrTiO&SrTaO/TiN,TaN SrTiO&SrO/Au,Pt SrTiO&SrO/TiN,TaN BaSrTiO/Au,Pt BaSrTiO/TiN,TaN BaSrTiO&Al2O3/Au,Pt BaSrTiO&Al2O3/TiN,TaN BaTiO/Au,Pt BaTiO/TiN,TaN SrTaO/Au,Pt SrTaO/TiN,TaN TiTaO/Au,Pt TiTaO/TiN,TaN NbTaO/Au,Pt NbTaO/TiN,TaN AlTiO2&Al2O3/TiN,TaN CeAlO/Au,Pt CeAlO/TiN,TaN October 11,

15 RF/decoupling capacitors Leakage current reduction multilayer dielectrics Crystalline SrTiO 3 high-k layer Amorphous SrTaO x leakage current blocking layer C. Baristiran Kaynak et al., Thin Solid Films 519 (2011) October 11,

16 RF/decoupling capacitors Leakage current reduction vs k eff reduction C. Baristiran Kaynak et al., Thin Solid Films 519 (2011) October 11,

17 RF/decoupling capacitors Achievements Low leakage current densities (<10-7 A/cm²) achievable only with dielectric multilayer k eff <50 Material choice: AVD BaSrTiO 3 /Al 2 O 3 & ALD SrTiO 3 /Al 2 O 3 J leak = < V k eff Voltage linearity <300 ppm/v² C f = 7.7 U bd = 15 V PDA temperature > 550 C Compatible with non-noble metal electrodes (TiN, TaN) Excellent step coverage for trench capacitors with ALD (shown for SrTiO 3, AlTiO 2 ) October 11,

18 Breakdown voltage >30 V High voltage capacitors Medium-k dielectric: ALD HfErO x (E bd = 3.9 MV/cm) Multilayers with ALD Al 2 O 3 (E bd = 7.0 MV/cm) k = 29 k eff = 19 k eff = 16 HfErO x Al 2 O 3 /HfErO x /Al 2 O 3 Al 2 O 3 /HfErO x nanolaminate t diel = 80 nm Data by: B. Toomey (Analog Devices) T. Blomberg (ASM) K. Cherkaoui, S. Monaghan (Tyndall National Insitute) October 11,

19 High voltage capacitors Achievements Nanolaminate shows lowest J leak at high k E bd Dielectric k E bd [MV/cm] k E bd J [A/cm²] HfErO x Al 2 O 3 /HfErO x /Al 2 O Al 2 O 3 /HfErO x NL Nanolaminate approach with medium-k dielectrics is a potential solution for high-voltage MIM capacitors with high capacitance density Optimization ongoing October 11,

20 Summary Extensive material screening performed Leakage current density limited choice of high-k dielectric depends on operating voltage DRAM capacitors k 100 RF/decoupling capacitors k <50 High voltage capacitors k <20 Deposition processes available Planar & moderate AR trench capacitors AVD & ALD High AR trench capacitors ALD MaxCaps is a joint success of cooperating partners along the whole value chain October 11,