R&D Issues for High-k Gate Dielectrics

Transcription

1 R&D Issues for High-k Gate Dielectrics T.P. Ma Yale University Spacer High-k Gate Dielectric Stack Source Drain Gate electrode, poly Upper interfacial region Bulk high-k film Lower interfacial region Substrate

2 ITRS Gate Stack Parameters Year of Production DRAM ½ Pitch 90 nm 80 nm 70 nm 65 nm 45 nm Physical Gate Length MPU/ASIC (nm) Equivalent physical oxide thickness for MPU/ASIC Tox (nm) Gate dielectric leakage at 100 C (ma/µm) High-performance Equivalent physical oxide thickness for low standby power Tox (nm) Gate Dielectric Leakage (pa/µm) LSTP Thickness control EOT (% 3s) <± 4 <± 4 <± 4 <± 4 <± 4

3 (C. Osburn)

4 Tunneling current increases exponentially with decreasing oxide thickness Taur, IEEE Spectrum, July 1999

5 Metal/Oxide/Semiconductor (MOS) Transistor Speed Increases with Charge Carrying Capacity, Q. Q = CV Dielectric constant where C = ε /d Oxide thickness To Increase C: Decrease d Increase ε (ε = k ε o ) High-k dielectrics

6

7 (Adapted from E. Garfunkel)

8

9

10 Dielectric Constants of Some High-k Materials

11 Reported High-k Dielectrics Iwai, et.al., 2002 IEDM

12 Material/thermal properties Electrical Properties Dielectric Material interface stability Crystallization phase separation leakage dielectric constant band offsets electrical defects device current SiO 2 SiO x N y Al 2 O 3 Al 2 O 3 -SiON ZrO 2 HfO 2 La 2 O 3 Sub surf ace oxid atio n po2 dep end ent?? Y 2 O 3 ZrO 2 -SiO 2 HfO 2 -SiO 2 ZrO 2 -Al 2 O 3 HfO 2 -Al 2 O 3 La 2 O 3 -SiO 2?????? Y 2 O 3 -SiO 2 HfO x N y LaAlO 3 epi??

13 Color Coding for High k Dielectrics Interface stability unreactive at 1000 C reactive at 1000 C reactive at 800C reactive at 600C Crystallization little xstalizatiobn at 1000C mostly crystalline by 1000 C highly crystalline by 800C crystalline at 600 C Phase Separation mostly phase mixed at 1000C partial phase separation by 1000C partial phase separation by 850C mostly phase separated by 700C Leakage <0.001 A/cm 2 >0.001 A/cm 2 >0.1 A/cm 2 > 10 A/cm 2 Dielectric Constant > <5-10 <5 Band Offset > < 0.7 Electrical Defects within 25% of those of SiO 2 or SiO x N y within orde of SiO 2 or SiO x N y systems > 2 orders worse than SiO 2 or SiO x N y too high to be considered Drive Current (for 1nm dielectric) 95% of SiO 10-20% degraded 20-30% degraded > 30% degraded

14 Current R & D Issues Arise from the Needs to: Achieve EOT << 1 nm Minimize Gate Leakage Current Ensure Thermal Stability Maintain High Drive Current and Transconducctance Ensure Reliability

15 Some R&D Issues for High-k Gate Stack

16

17 (After Gusev)

18 (After Garfunkel)

19 (After Garfunkel)

20 (After Garfunkel)

21

22 PVD-dielectrics Nitrogen incorporation technique HfO 2 BN TN HfO x N y HfO x N y HfO 2 HfO 2 HfO x N y HfO 2 Si Si Si Si Various nitrogen incorporation processes for HfO 2 (e.g. NH 3 surface nitridation, top nitridation or HfO x N y using N 2 plasma) were developed. It was found that nitrogen incorporation increased crystallization temperature, reduced boron penetration, increased breakdown field, reduced leakage current and improved reliability.

23 Advantages EOT (? TaN/HfO 2 /Si V FB (V) Annealing Temperature ( o C) Annealing Time (sec) Ref) R. Choi et al, VLSI 2001 & K. Onishi et al, VLSI 2001 Disadvantages Large hysteresis and interface state density Poly-Si/HfO 2 /Si PVD-dielectrics Surface Nitridation by NH 3 Annealing Surface nitridation provides better interface stability and boron penetration immunity than control. Potential reliability problem due to Boron diffusion inside the HfO 2

24 HfOxNy vs HfO2 Choi, et.al IEEE EDL VOL. 24, NO. 4, APRIL 2003

25 Nitrogen Incorporation Degrades Mobility Kang et.al, 2002 IEDM

26 TaN Gate/PVD-HfO 2 NMOSFET/BN : Carrier Mobility Mobility (cm 2 /V-s) W/L=150µm/10µm Universal No anneal FG anneal EOT : 8.4 Å Effective Field (MV/cm) Using nitrogen incorporation and HT(600 C) forming gas anneal, high mobility (~380 cm 2 /Vs was obtained (EOT = 0.84 nm).

27 Thermal Stability Against Crystallization Form Silicate (e.g. HfSiO4) Nitrodize High-k Dielectric (e.g. HfOxNy) Form Alumnate (e.g. HfAlxOy)

28 HfO 2 crystallizes between 300 and 400ºC (110) HfO 2 100nm Counts (A.U.) o C 400 o C 300 o C As-deposited Theta (degree)

29 Xtallization Temp. of HfO 2 Rises by Adding Al Counts (A.U.) (110) HfO 2 100nm 500 o C 400 o C 300 o C As-deposited Counts (A.U.) HfAlO with ~31.7% Al, ~100nm 1000 o C 900 o C 850 o C As-deposited Counts (A.U.) Theta (degree) HfAlO with ~6.8% Al, ~100nm 700 o C 600 o C 500 o C As-deposited Theta (degree) As deposited JVD HfO 2 is amorphous Crystallization occurs at C 6.8% Al Raises Tc to C 31.7% Al Raises Tc to >850 C Theta (degree)

30 Annealing temp. dependence of leakage in ultra-thin ( nm) HfO 2 and HfAlO films Leakage current density (A/cm 2 V g -V fb = -1V HfO 2 x-tallization onset HfO 2 6.8%Al 2 O 3 x-tallization onset HfO %Al 2 O 3 x-tallization onset PDA Temperature ( C) Rise of leakage current is due to crystallization; subsequent decrease is due to growth of interfacial region. Crystallization temp. is higher by 100 C compared to thick films. Addition of Al increases thermal stability

31 Substrate Injection I-V Fits Schottky Emission Model with Barrier Hieght of 1.13 ev for HfO 2 /Si log(leakage Current) (log(a)) o C ~1.13eV Ec Ef Ev Pt HfO 2 SiO 2 27 o C Pt/JVD-HfO 2 /n-si EOT=1.63nm Substrate injection -ln(j/t 2 ) o C o C 250 o C E 1/ V g (V)

32 Gate Injection I-V Fits Frenkel-Poole Model with Trap Energy of ~1.5 ev in HfO 2 log(leakage Current) (log(a)) ~1.5eV 400 o C Pt HfO 2 SiO 2 27 o C Ec Ef Ev Pt/JVD-HfO 2 /n-si EOT=1.63nm Gate injection ln(j/e) V /T V g (V) 22-2V -2.5V

33 Tunneling current of HfO 2 at 77K and F-N fitting in high field region-pt gate log(leakage Current) (log(a)) -3 T=77K -4 Pt/HfO 2 /p-si -5 EOT=3nm ln(i/e 2 ) /E V g (V) 43 42

34 Tunneling current of HfO 2 at 77K and F-N fitting in high field region-al gate log(leakage Current) (log(a)) T=77K Al/HfO 2 /p-s i EOT=3nm ln(i/e 2 ) /E V g (V)

35 F-N I-V characteristics with 2 different electrodes yield barrier height and effective mass of electron F-N tunneling current: 1/ 2 J = J 0[ Φ exp( AdΦ ) ( Φ + ev )exp( Ad( Φ + ev ) Slope of lnj/e 2 vs 1/E: 1/ 2 )] B B Pt Al qm = π ( *) / / Φ 3h qm = π ( *) / / Φ 3h Where 32 Pt 32 Al Φ Pt Φ Al = 12. V (Pt gate) (Al gate) Φ Φ Al Pt = 128. V = 248. V m* = 01. m 0

36 Energy band diagrams of Pt/HfO 2 /p-si and Al/HfO 2 /p-si Vacuum Level ~2.82eV 5.3eV ~2.48eV Ef 4.1eV ~1.13eV ~1.28eV Ec Ef Ev 4.05eV Ec Ef Ev Pt HfO 2 Si Al HfO 2 Si

37 Energy band diagrams of Al/ZrO 2 /Silicate/Si and Al/Al 2 O 3 /Si Obtained by internal photoemission and FN tunneling experiments Vacuum Level Vacuum Level E F 1.95 ev 4.15 ev 4.05 ev ~1.9 ev E c E v ~2.1 ev E F 4.15 ev 4.05 ev ~3.1 ev 9 ev ~ 3.0 ev E c E v Al ZrO 2 Silicate Si Al Al 2 O 3 Si Al/ZrO 2 /Silicate/Si Al/Al 2 O 3 /Si

38 Band Diagrams of Al/Ta 2 O 5 /SiN/Si and Al/TiO 2 /SiN/Si Vacuum Level 4.15 ev 2 ev 4.05 ev 2 ev 4.15 ev 4.05 ev E F ~0.38 ev ~0.28eV ~1.0 ev E c E v E F 3.25 ev E c ~0.9eV 4.65 ev E v Al Ta 2 O 5 SiN P-Si Al TiO 2 SiN P-Si Al/Ta 2 O 5 /SiN/Si Al/TiO 2 /SiN/Si

39 Degradation of Channel Mobility in High-k Gated MOSFETs SiON 400 Mobility (cm 2 /V-s) FG 400 癈 FG 500 癈 FG 600 癈 Universal NMOS W/L = 150/10 祄 EOT ~ Effective Field (MV/cm) Mobility (cm 2 /V-s) HfO 2 Universal No anneal FG anneal Effective Field (MV/cm)

40 Common Problems that Cause Errors in High-k Gated MOSFET Mobility Trapping by interface traps (including border traps) that cause overestimation of carriers and thus underestimation of mobility High gate leakage current that results in underestimation of mobility at high fields

41 Mobility of HfO 2 -Gated MOSFET Mobility (cm 2 /V-s) -Effect of Interface Traps With N it Correction nmosfet,hfo 2 W/L=20µm/15µm 100KHz 50 PDA temperature w/o N 700 o C it Correction 600 o C Q inv (µc/cm 2 ) Corrected curves are higher Both show a peak, as predicted by scattering theory

42 Mobility measurement Effective mobility: µ Conventional eff Q = L w inv = V d C d Q Inversion charge density: I ox ( V inv (V g ( V g ) g ) - V T ) Split CV: Vg Q = C ( V ) dv inv gc g g C gc is not step function of V g at V T => need split CV

43 Standard split CV method is inadequate for high-k dielectrics with high N it Problem 1. N it can respond to ac signal C gc = C ox Cox ( C + C inv + Cit ) + C + C inv D it Vg E it C it E c E F E v Solution: Higher frequency for split CV C ox C inv C D Problem 2. N it can respond to dc signal Gate Dielectric substrate dv = ( dq + dq ) / C g inv Solution? trap ox C gc N it response to ac signal N it response to DC signal Ideal Vg

44 Mobility from Split CV -Interface trap correction for mobility extraction C gc /Area (x10-8 F/cm 2 ) I d (µa) Ideal w/o N it V g1 V g (V) V g2 Measured With N it (a) V g (V) (c) µ 1 µ 2 Q inv (µc/cm 2 ) Ideal w/o N it 150 Q 1 Q 2 Measured With N it (b) With N it Correction W/O N it Correction (d) Q inv (µc/cm 2 ) Q 1, not Q 2, should be used for mobility extraction C gc /Area (x10-8 F/cm 2 ) Effective Mobility µ eff (cm 2 /V-s) µ eff = L w V d I d Q ( V inv g ) ( V g )

45 Mobility from Split CV (cont d) -Interface trap correction for mobility measurement At high frequencies, gate-channel capacitance C gc = C ox CoxC + C inv inv + C D Vg E it E c E F E v where C inv = dq dψ is the same with or w/o interface traps for the same Q inv inv s Gate C ox Dielectric C inv C D substrate At same C gc, Q 1 extracted from ideal C gc and Q 2 from measured C gc contain the same amount of mobile inversion charge, while Q 2 contains extra interface trapped charge

46 Mobility of HfO 2 -Gated MOSFET Mobility (cm 2 /V-s) -Effect of Interface Traps With N it Correction nmosfet,hfo 2 W/L=20µm/15µm 100KHz 50 PDA temperature w/o N 700 o C it Correction 600 o C Q inv (µc/cm 2 ) Corrected curves are higher Both show a peak, as predicted by scattering theory

47 Hall Mobility vs Effective Mobility from split CV 1000 µ Hall Mobility (cm 2 /V-s) µ eff SiO 2 µ eff-correction µ HfO 2 µ Hall eff-no-correction nmosfet, poly gate Q inv (x10-6 C/cm 2 )

48 Normalized Inversion Charge Density 0.7 Q inv /C inv (V) HfO 2 split CV w/o correction split CV with correction Hall effect V g -V T (V)

49

50 Temperature dependence of mobility µ eff (cm 2 /V-s) HfO 2 with Correction Universal Mobility Temperature: 120K 160K 200K 240K 280K 320K 50 0 HfO 2, w/o Correction Effective Vertial Field (MV/cm) Effective mobility for HfO 2 is lower than universal mobility even after interface correction.

51 Extraction of mobility limited by phonon scattering µ (cm 2 /V-s) nmosfet, T=240K µ coul µ eff µ ph µ SR Effective Field (MV/cm) 1 µ = ph µ eff µ coul µ sr The mobility limited by phonon is extracted according to Matthiessen s rule.

52 Temp. dependence of mobility limited by phonon scattering µ ph (cm 2 /V-s) nmosfet E eff =0.65MV/cm E eff =0.75MV/cm E eff =0.85MV/cm SiO 2 HfO Temperature (K) Mobility limited by phonon scattering for HfO 2 sample is much lower than that for SiO 2 sample

53 The difference between HfO2 and SiO2 is attributed to soft optical phonons in HfO 2 1/µ ph (cm 2 /V-s) MV/cm 0.75MV/cm 0.65MV/cm HfO 2 SiO 2 difference between HfO 2 and SiO Temperature (K) Scattering Rate (x10 13 s -1 ) The scattering rate by the additional soft optical phonons in HfO 2 sample is a weak function of temperature, which is consistent with theoretical calculation.

54 The scattering rate due to optical phonons: Where 1 τ N op R [ N R 1 = ηω / kt e + ( N 1 R + 1) u( E ηω )] u(x) is the unit step function. is phonon occupation number For For For ηω < E 1 τ op ηω << kt ηω > kt (2N 1 τ 1 τ op op R + 1) T = e e x x constant where x = ηω kt

55 Inelastic Electron Tunneling Spectroscopy An Inelastic Tunneling Event at E=eV = hν Causes (a) I-V to increase slope; (b) a step in di/dv; (c) a peak in d 2 I/dV 2 I di/dv d 2 I/dV 2 Elastic Elastic Inelastic ev=hν Elastic Inelastic V

56 Various Inelastic Modes in the Barrier (Left) May Be Reflected in IETS (Bottom Right) d 2 I dv 2

57 Interactions Detectable by IETS Substrate Silicon Phonons Gate Electrode Phonons Dielectric Vibrations Impurity Molecular Vibrations Trap States

58 Measurement Setup based on standard lock-in measurement Second derivative of I-V is proportional to second harmonic signal from device under test.

59 Vibration Position and Direction Dependence of IETS Theoretical Calculation Shows that: (a) electrons have higher probability to interact with vibrations closer to interfaces; (b) electrons have higher probability to interact with vibrations normal (LO mode) to the interfaces,

60 Bias Polarity Dependence Electrons have higher probability to interact with a vibration located near the positively biased electrode.

61 SAMPLES Texas Instruments Lot 8020 Device Area: 0.01 cm 2 500TiN/6000 AlCu/500 TiN 8000 TEOS Phosphorous Implant 5x10 15 ions/cm 2, 80keV 4500 LOCOS 2500 ISD Polysilicon 15 to 18 Tunnel Oxide n-type (100), 1½cm-10½cm

62 Deconvolution of IETS Spectrum of SiO 2 /Si Silicon phonons Si-O modes Wave Number [cm -1 ] mV 43.6mV 53.6mV G i [Arbitrary Units] 59.4mV 63.4mV Silicon phonons Si-O modes Voltage Bias [Volts] x10-3

63 IETS (Arbitrary Units) Si phonons and SiO 2 vibration modes Si phonons SiO 2 vibrations enter text here mv: Si 44 mv: Si 53 mv: Si 59 mv: Si TA mode LA mode LO mode TO mode Voltage (V) Voltage (V) 63 mv: Si-O LO1 mode (Rocking) 144 mv: Si-O AS1 mode (Asymmetric Stretch) 150 mv: Si-O AS2 mode (Asymmetric Stretch) 155 mv: Si-O LO3 mode (Symmetrric Stretch) 165 mv: P-O mode

64 W/O HF Vapor (a) IETS Si(LA) Si(TA) Si(LO) Si(TO) W/O HF Vapor SiO 2 SiO 2 (a) 21 enter text here With HF Vapor Si-F mode (b) With HF Vapor (b) Voltage (mv) IETS can detect structure changes caused by different processing conditions. (a) SiO 2 /Si without HF vapor pre oxidation cleaning (b) SiO 2 /Si with the HF vapor pre oxidation cleaning Voltage (mv)

65 IETS can detect changes caused by thermal annealing The increase of LO3 peak height in forward bias spectra after annealing indicates increase of the 142 degree bond angle distribution close to the SiO 2 /poly interface.. Changes in oxide mode after 2 hour, 400 C anneal in N2. A,B before annealing, C,D after annealing

66 Electrical Stress Alters the Si-O Modes But Leaves the Si Phonons Unchanged Si phonons Increasing Stress Si-O modes

67 IETS can detect changes caused by elctrical stress IETS reveals changes in SiO 2 /Si interface after AC stress. Possible explanation is that AC stress breaks weak bonds and cause positive charges at the interface. The positive charges will modify the bonding structure for SiO2 near the interface. A:Initial; B-D:After 10 3,10 4,10 5 sec +0.5V 1kHz square wave stress; E:After 10 3 sec +2V 1us 1kHz pulses; F: After 10 3 sec -2V 1us 1kHz pulses.

68 IETS of Thermal SiO 2 on Si and CVD Si 3 N 4 on Si Si-O ( LO1 ) 8.0x mv 780 mv Si-H Si-N Si-H Si ( TA ) Si-F Donor Si ( LA ) Si ( LO ) Si ( TO ) Si-O ( LO4 ) Si-O ( LO3 ) 4.0x x x x10-9 SiO 2 Si 3 N 4 SiO 2 Si 3 N 4 IETS (Arbitrary Units) Voltage (V)

69 IETS of Al gate/hfo 2 /Si structure compared with FTIR Hf-O modes appear in IETS: 35mV(270cm -1 ), 50mV(400cm -1 ), 70mV (560cm -1 ). (Arbitrary Units) Hf-O Hf-O Si Hf-O FTIR Hf-O-Si IETS Voltage (mv)

70 IETS of JVD HfO 2 Comparison between HfO 2 and SiO 2 on silicon substrate IETS (A.U.) HfO 2 SiO 2 Hf-O Hf-O Hf-O Si-O-Hf Si-O Si-O Voltage (V)

71 Phonon Modes for Tetragonal HfO 2 A 2u E u1 E u2 A 2u E u1 E u2 TO (mv) ~30 ~43 ~77 LO (mv) ~37 ~75 ~83

72 IETS of JVD HfO 2 IETS (Arbitrary Units) Hf-O Si Hf-O Si-O-Hf Si-O Voltage (V)

73 IETS of JVD HfO 2 Si IETS (A.U.) Hf-O Hf-O Si-O-Hf Si-O IETS (A. U.) IETS (A. U.) Voltage (mv) Voltage (mv)

74 IETS sensitive to process variations for Al/HfO 2 /Si structure (1) Post deposition annealing: Furnace vs. RTA 1.40E E E-007 RTA IETS (A.U.) 8.00E E E E E E E E-008 Furnace anneal ~15A HfO 2 600C N 2 2min ~25A HfO 2 600C RTA N 2 2min Voltage (mv)

75 IETS sensitive to process variations for Al/HfO 2 /Si structure (2) Hf-O Hf-O Si-O-Hf Hf-O ~15A HfO2 N2 600C 3mins Si-O ~10A HfO 2 N 2 600C 3mins + WV 600C 2mins Thermal Oxide Reference Voltage (V)

76 IETS sensitive to process variations for Al/HfO 2 /Si structure (3) Hf-O peaks stronger with increasing PDA temperature Linked to more HfO 2 crystallization at higher temperatures. 1.00E E-008 Hf-O Si Hf-O Si Hf-O 600C IETS (A. U.) 6.00E E E E C 400C 300C -2.00E-008 ~25A HfO 2 RTA in N Voltage (mv)

77 Bias Polarity Dependence of IETS for Al/HfO 2 /Si Results suggest significantly different microstructures near Al-HfO 2 interface and Si-HfO 2 interface. HfO 2 /Si interface is more SiO 2 -like. HfO 2 /Al interface is more HfO 2 -like. 8.00E E-010 ~15A JVD HfO 2 on Si, annealed in N 2 600C 3min Si 4.00E E-010 Si Hf-O Hf-O Hf-O Si-O-Hf IETS (A.U.) 0.00E E E-010 Forward Bias Si Si Si Si-O Si-O -6.00E E-010 Reverse Bias -1.00E Voltage (mv)

78 IETS of HfAlO on Si Al-O peak appears in both forward and reverse-bias spectra, suggesting that Al-O bonds exist throughout both interfaces Possible Al-O-Hf vibration is identified at 0.095V. IETS (A.U.) HfAlO (30% Al) on Si PDA at 500 o C Si Si Si Si Si Hf-O Al-O-Hf Al-O-Hf Hf-O Al-O Si-O-Hf Forward Reverse Si-O Al-O Si-O-Hf Si-O Voltage (V)

79 Stress induced Effect DC Stress in general increases the leakage current and conductance, most likely due to the generated traps. Current (A.U.) Increasing stress HfO 2 annealed at 600 o C After 200s 1.2V stress After 400s 1.2V stress After 800s 1.2V stress measured at 300K Conductance G (A. U.) HfO 2 annealed at 600 o C After 200s 1.2V stress After 400s 1.2V stress After 800s 1.2V stress measured at 300K Increasing stress Voltage (V) Voltage (V)

80 I Trap Related Effect Trap Assisted Tunneling Background I-V Charge Trapping V G i Trap Assisted Tunneling Charge Trapping V

81 Stress induced Effect Features at 0.07V and 0.16V indicate trap assisted tunneling. The polarity dependence of the features suggests that the traps are located near the HfO 2 -Al interface. O riginal, Forw ard Bias After 20s 2.5 V Stress After 200s 2.5 V Stress After 600s 2.5 V Stress IETS (A.U.) Si Trap or defect Assisted Tunneling Al-O Si-O-Hf Si-O Trap or defect Assisted Voltage (V)

82 Stress induced Effect (Reverse Bias) Original, Reverse Bias After 20s 2.5 V Stress After 200s 2.5 V Stress After 600s 2.5 V Stress IETS (A.U.) Si Trap Assisted Tunneling Si-O-Hf Si-O Voltage (V)

83 Stress induced Effect Trap assisted tunneling increases after stressing. d 2 I/dV 2 (A.U.) After 800s 1.2V stress After 200s 1.2V stress Original Increasing Stress Traps Voltage (V)

84 Stress-induced traps measured under forward and reversed biases d 2 I/dV 2 (Arbitrary Units) (a) Forword Bais Si (b) Reverse Bias Si Si-O-Hf (1) Before Al-O Si-O Stress (2) After Stress (1) Before Si-O-Hf Si-O Al-O Stress (2) After Stress Voltage (mv)

85 Conclusion Extensive R&D Efforts for High-k Gate Dielectrics Are Needed to Realize EOT << 1 nm Low Gate Leakage Current Good Thermal Stability High Drive Current and Transconducctance Good Reliability