23.0 Review Introduction

Transcription

1 EE650R: Reliability Physics of Nanoelectronic Devices Lecture 23: TDDB: Measurement of bulk trap density Date: Nov Classnotes: Dhanoop Varghese Review: Nauman Z Butt 23.0 Review In the last few lectures we have been discussing the time dependent dielectric breakdown (TDDB) in CMOS devices. The physics behind TDDB was explained based on the Anode Hole Injection (AHI) model. According to this model, the electrons tunneling from the cathode impact ionize at the anode and generate hot holes. A fraction of these hot holes get injected back into the gate oxide and generate defects. The dielectric breakdown time (T BD ) of devices subjected to TDDB stress was found to be Weibull distributed. This was explained based on the percolation theory, where defects generating at random locations in the oxide eventually line up and form a shorting path between the two electrodes, thereby damaging the device. In order to validate these theoretical models, it is important to have measurement techniques capable of monitoring the defect densities as a function of stress time. This lecture focuses on various measurement techniques that are commonly used to attain this Introduction Figure 1 shows the time evolution of gate leakage current for a CMOS device subjected to TDDB stress (V G =V STS ). The gate current increases gradually as defects are generated in the oxide and ultimately lead to device breakdown as a percolation path is formed between the gate and the bulk. Figure 2a shows the spatial distribution of defects that are generated in the gate oxide during the stress phase. Each of these defects introduces an energy level in the oxide band gap, as shown in figure 2b. Electrons tunneling through the gate oxide can hop in and out through these energy levels, resulting in additional leakage paths and hence higher leakage currents. During this process, some of the electrons can get trapped in these levels for a longer duration, leading to bulk oxide charges. I G V G =V STS T BD Time Figure 1 Gate leakage current of a CMOS device subjected to TDDB stress

2 X X X Gate X X Bulk Gate Bulk (a) (b) Figure 2 (a) Spatial distribution of defects generated during TDDB stress. (b) Energy band diagram for NMOS transistor. Each defect introduces an energy level in SiO 2 band gap through which electron can hop in/out. Various techniques are being used to measure the number of defects that are generated during the stress and their energy distributions. Some of these techniques are listed below and will be discussed in greater detail in the following sections. Capacitance-Voltage (CV) Method Stress Induced Leakage Current (SILC) Low Voltage Stress Induced Leakage Current (LV-SILC) Quantum Yield (QY) Measurement Remote Photon Spectroscopy 23.2 Capacitance-Voltage (CV) Method The capacitance-voltage (CV) method makes use of the fact that electrons can remain trapped in a fraction of the defect energy levels, leading to bulk oxide charges. To measure the number of defects that are generated at any given stress time, the stress gate voltage is removed temporarily and the defects levels are charged by injecting electrons. The bulk oxide charge density after charging is proportional to the defect density and can be measured using conventional CV techniques. This method is suitable for gate oxides that are thicker that 100Å. Though this is a simple measurement technique, it has the disadvantage of not being a very sensitive one. The smallest change in defect density that can be measured using the CV method is in the order of per cm 2.

3 23.3 Stress Induced Leakage Current (SILC) SILC measurements are suitable for oxide thickness in the range Å and provides a very sensitive measurement of the defect density. It can measure defect densities in the order of 10 8 /cm 2, which might correspond to a single trap being generated! The SILC measurement is performed by lowering the gate voltage from the stress bias (V G =V STS ) to a measurement bias (V G =V MEAS ) and monitoring the gate current (see Figure 3a). The defect levels in the oxide band gap provide additional leakage paths for the electrons and hence result in higher leakage currents. The increase in leakage current is significant at lower gate voltages when the direct tunneling current is smaller (figure 3b). This is the reason why SILC measurement has to be carried out at V MEAS < V STS. I G V G =V STS ln(i G ) V STS t2 V G =V MEAS t1 t=0s t1 t2 Time V G (a) (b) Figure 3 (a) Gate current during alternate TDDB stress and SILC measurement phases. (b) I G -V G characteristics before stressing the device and during the stress. A careful look at figure 3b shows that the slope of the SILC vs. gate voltage is almost half the slope of the direct current vs. gate voltage. This is an important signature of SILC and to understand this, we derive analytical expressions for various gate tunneling components (figure 4). The direct tunneling current J DIR is given by the expression: ( ) J = AP f f (1) DIR DIR c a Where P DIR is the tunneling probability, f c the Fermi function at the cathode, f a the Fermi function at the anode and A is a constant. The tunneling probability P DIR can be obtained from the WKB approximation as:

4 DIR T T ' OX ξ OX ξtox P e e e k( x) dx k( xdx ) k( x ) dx = = (2) ' ' Where x is the distance measured from the beginning of the tunneling path and x is the distance measured from the trap location. We note that, by definition? +? = 1. Substituting for tunneling probability in equation 1, we get: ξt ' OX ξtox ' ' k( xdx ) k( x ) dx 0 0 DIR = [ c a ] = 1 2 c a ( ) ( ) J Ae e f f APP f f (3) J DIR J 1 J 2 x Figure 4 Gate tunneling current components x Similarly, we can write an expression for J 1, which is the tunneling current component from the cathode into the trap: ( ) ( ) J1 = cσ NOTP1 fc 1 ft ft 1 fc (4) The two terms in the above expressions are the inward and outward electron fluxes from the cathode to the trap and vice versa. In above equation σ is the capture cross-section of the trap, N is the trap density and c is a constant. Equation 4 can be simplified as: OT ( ) J = cσ N P f f (5) 1 OT 1 C T A similar expression can be written for J 2, the tunneling current component from the trap to the anode:

5 ( ) J = cσ N P f f (6) 2 OT 2 T A At steady state, both J 1 and J 2 current component will be equal and will be same as the SILC. Equating 5 and 6, one can eliminate f T, the trap occupation function. Thus we get the following function for SILC. PP J = cσ N f f ( ) 1 2 SILC OT C A P1+ P2 (7) From equation 2, we can see that the direct tunneling probability P DIR (=P 1 P 2 ) in the numerator of SILC current expression is independent of the trap location. However, the P 1 +P 2 term in the denominator is a strong function of the trap location. The SILC is maximized for trap locations at which P 1 +P 2 is minimized. Figure 5 plots the tunneling probabilities P 1, P 2 and their sum as a function of trap location along the oxide. It can be seen that the sum minimizes for traps close to the middle of the oxide, for which P 1 =P 2 =P. Hence, major contribution towards SILC comes from traps which lie close to middle of the oxide (x=t OX /2). P 1 P 1 +P 2 P 2 x = 0 Trap location x = T OX Figure 5 Tunneling probabilities P 1, P 2 and their sum as a function of trap location Substituting P 1 =P 2 =P in equation 7, we get the following approximate expression for the net SILC. cσ NOT P JSILC = ( fc fa) (8) 2 Equation 3 can also be re-written as:

6 ( ) J = AP f f (9) 2 DIR c a Eliminating the tunneling probability P between equation 8 and 9, we get: J SILC ( f f ) cσ NOT C A = JDIR (10) 2 A ( f f ) cσ N OT C A 1 ln( JSILC) = ln + ln 2 A 2 ( J ) DIR (11) First term on the right hand side of the above equation is independent of gate voltage, and hence the voltage dependence of SILC is related to that of direct tunneling current. The above relation explains why the slope of SILC vs. gate voltage is half the slope of direct tunneling current vs. gate voltage Low Voltage Stress Induced Leakage Current (LV-SILC) LV-SILC measurements are suitable for oxide thickness less than 20-30Å. For these thin oxides, the direct tunneling current even at low gate voltage is high enough that any increase in gate leakage due to SILC is difficult to measure (see figure 6). ln(i G ) Direct tunneling SILC Time Figure 6 Direct tunneling current and SILC for thin oxide device. Direct tunneling is much larger compared to SILC for these devices, making measurement of SILC very difficult. The solution to this problem is to reduce the gate voltage further and go to negative gate voltage, close to the device flat band conditions. The energy band diagram of the device corresponding to this condition is shown in figure 7. It can be observed that the band

7 alignment on the gate and substrate is such that very little direct tunneling occurs. Due to the same reason, the trap assisted tunneling current as described for the positive measurement gate voltage is also not present under these conditions. However, an alternate mechanism is possible in which the electron can tunnel to an interface trap and later recombine with a hole from the accumulation layer (see figure 7). This can lead to an increase in the gate current, which is denoted by the term LV-SILC. Gate Bulk J 1 J 2 Figure 7 Energy band diagram of NMOS transistor under negative gate bias. Electron can tunnel to defects close to interface and later recombine with accumulation holes. Similar to conventional SILC, we can write the following expressions for the J 1 and J 2 current components. ( ) J = cσ N P f f (12) 1 OT DIR C T NOT ft J2 = (1 fa) (13) τ R It is important to note that the LV-SILC measures the interface trap density and not the bulk traps as the case of conventional SILC. However if no Si-H bonds are broken during the stress phase, the measured trap density will be due to broken Si-O bonds, and will be proportional to the bulk trap density Quantum Yield (QY) Measurement The measurement techniques discussed so far measures the number of defects that are generated in the oxide. They do not provide any information regarding the energy

8 distribution of these defects. The quantum yield (QY) measurement helps us in overcoming this limitation. Consider the transistor structure as shown in figure 8a. Figure 8b illustrates direct tunneling of electrons from the gate to the bulk and the subsequent impact ionization. The electron that tunneled in and the one that was generated by impact ionization flow out of the device through the substrate contact and contribute to the bulk current. The hole that was generated flows into the source/drain contact and can be measured as an increase in source/drain current. In this way, the two types of carriers that are generated by impact ionization get separated, and hence this is also called a carrier separation measurement. n + 1 p + p + n A 2a 3 2b A (a) (b) Figure 8 (a) Device structure for QY measurements (b) Direct tunneling of electrons (step 1) followed by electron/hole pair generation (step 2). Electrons flow out through substrate contact (step 3) and holes through source/drain contacts. The impact ionization factor a can be measured by taking the ratio of the hole current to the electron current. QY I = I SD SUB (14) As discussed earlier, the defects generated during the stress can lead to significant increase in the gate leakage current (figure 9a). If the trap assisted tunneling process is assumed to be elastic (i.e. electrons do not loose energy during tunneling), one might expect the number of hot holes that get generated by impact ionization to increase with SILC. This increase in generation of hot holes should also get reflected as an increase in the source/drain current. However results from the QY measurement shows that the overall impact ionization efficiency decreases with stress time (figure 9b). This can be only explained by the fact

9 t = 0s ln(i G ) t = 0s a Stress time Stress time V G (a) V G (b) Figure 9 (a) I G -V G and (b) II coefficient a, before stressing the device and during the stress. 1.5eV High Energy Low Energy Figure 10 Trap assisted tunneling process in gate oxide, leading to SILC. Reduction in II coefficient obtained from QY measurement requires inelastic tunneling of electron. Energy loss is estimated to be 1.5eV.

10 that the additional SILC component is inefficient in generating electron-hole pairs when compared to the direct tunneling current. The reduced efficiency might by due to the fact that the electron that gets trapped in a bulk defect looses some energy as the charged defect undergoes a reconfiguration (figure 10). As a result, when the electrons tunnel out from the trap, they arrive at a lower energy compared to the direct tunneling electrons, thereby reducing the impact ionization rate. By matching the experimentally observed reduction in a with simulation, the possible loss of energy within the oxide for the trap assisted tunneling process was estimated to be 1.5eV. If the additional SILC component is capable of impact ionizing and generating hot carriers, a positive feedback loop would have set in and new defects would tend to form close to the existing defects. However TDDB measurement on samples with thinner gate dielectric thickness shows that these devices can have multiple breakdown spots, which are spatially uncorrelated. This can lead to improved device lifetime, which would not have been possible unless the electron looses a fraction of energy in the oxide during the trap assisted tunneling process and become inefficient in impact ionization at the cathode Conclusion We have discussed a number of characterization techniques for trap density based on C- V and I G -V G methods. We have also analyzed the energy levels of the traps by Quantum Yield technique, however we did not have time to discuss the Remote Phonon Spectroscopy. All characterization techniques have some limitations therefore crosschecking various numbers by using multiple characterization techniques is always a good idea. With this lecture, we conclude the discussion regarding classical TDDB breakdown in thin oxides where the first breakdown defines the oxide lifetime (hard breakdown). As we have discussed before that at lower voltages, the first breakdown may not destroy transistor operation (breakdown may be soft). Therefore the transistor lifetime may be longer than previously presumed. We will discuss the issues related to soft and hard breakdown in the next class.