Advanced and Emerging Devices: SEMATECH s Perspective
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1 SEMATECH Symposium October 23, 2012 Seoul Accelerating the next technology revolution Advanced and Emerging Devices: SEMATECH s Perspective Paul Kirsch Director, FEP Division Copyright 2012 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.
2 Outline Overview III-V on Si Heterointegration Device Modules Device Results RRAM Memory Summary 10/15/2012 2
3 Question: Can process technology keep up with data demand? Source: M. Mayberry, Intel, IEEE VLSI Symposium /15/2012 3
4 Image: 'E _ A_17_L26_rot.dm3' MAG: 115kX PCL: Answer: New materials & structures are needed Fin MG Stress Epi on Fin Slot Contacts Replacement MG Nanowires ALD Doping III-V FinFETs 92 nm 24 nm 2 0 n m 3D stacking Heat Sink and memory Logic memory TIM memory memory Si TSV interposer SOC Theme: Image Credit: Intel SEMATECH materials (III-V), structures (finfet), memory (RRAM) for future SOC 10/15/2012 4
5 Five year plan & device roadmap Manufacturing Development Ge pmos; III-V nmos 2019 III-V TFET 2021 D. K. Mohata VLSI 2012???? 2024 Ge pmos; Si nmos 2015 Ge CMOS 2017 S. Banerjee 2009 Si FinFET nd Gen HKMG 2009 Intel Intel Pathfinding: SEMATECH Space 32nm 22nm 14nm 10nm 7nm 5nm 3nm 10/15/2012 5
6 Grand challenges to realize the III-V roadmap Technology Grand Challenges Development Dates HVM III-V MOCVD epi III-V epi metrology III-V FinFET STI, CMP III-V on Si III-V doping, activation, Rco III-V ESH III-V gate dielectric & reliability III-V pfet III-V Tunnel FET 10/15/2012 6
7 Outline Overview III-V on Si Heterointegration Device Modules Device Results RRAM Memory Summary 10/15/2012 7
8 Some III-V fin formation options Option 1: Ge & III-V Replacement Fin HM Si Ge III-V Si Ge Option 2: Top-Down Fin Etch Si Si Si Replace (Grown) Fin HM HM Fin height HM HM Fin height HM HM Fin height Fin height Buffer Buffer Buffer Buffer Si Si Si Si Etched Fin 10/15/2012 8
9 Selective Epi key for low defect replacement FIN GaAs Ox GaAs Ox GaAs 500nm Aspect Ratio Trapping (ART) SiGe / Ge III-V Si Ge 30nm 70% Ge Si Ox Significance: Good scalability, ART in 30 nm feature demonstrated. 10/15/2012 9
10 Improved ART for defect reduction in MOCVD III-V on Si GaAs SiO 2 GaAs Si Si III-V Si Ge Dislocations appear to terminate at sidewalls in XTEM Is there more direct proof that ART works? Aspect Ratio Trapping Si 10/15/
11 Direct proof of reduced III-V threading dislocations X-TEM PVTEM Thick TEM sample (~200nm) GaAs + Si Stacking faults Thick TEM Sample TDs SFs (~200nm) TDs Thin TEM Sample Thin TEM sample (~100nm) GaAs only SFs (~100nm) No TDs observed! Stacking faults Significance: Threading Defects can be reduced with ART III-V on Si 10/15/
12 III-V Fin etch development InGaAs & InAlAs etch development Hardmask Smooth InAlAs 300A InGaAs 1500A InGaAs InGaAs/InAlAs etch ready for STI process flows. Developed with TEL Y. Ohsawa, K Akiteru, Y. Trickett, G. Nakamura H Ohtake 10/15/
13 300mm III-V MOCVD tool at SEMATECH-Albany Top down or bottom up fin requires epi Safety: Independent room, air handling, scrubbers, detectors, exits III-As, III-P, III-Sb, III-N capable tool and space Several new members join consortia for this capability 10/15/
14 Outline Overview III-V on Si Heterointegration Device Modules Device Results RRAM Memory Summary 10/15/
15 P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P III-V non-planar doping module Approach MLD Beam Line Fin Formation DHF Deglaze Wet Chemical Doping Native oxide P P P P P P P P P P P P Process Steps Cap Removal Anneal Oxide Cap P P P P P P P P P P P P P P Doping Uniformity Uniform & Conformal around Fin (by means of wet chemical doping) Poor Uniformity, Non-Conformal FIN Damage No Damage (Wet Chemical Doping) Severe Ion Implant Damage Junction Doping Remarks Fin-Width, Thermal Budget Dependent Defect-Free USJ (<10nm) & highly conformal Cap layer selection is critical Good Industry standard process Severe Fin damage Junction depth >20nm 10/15/
16 Column VI Dopant Conc (1/cm3) Column VI MLD and flash anneal promising ~10nm Xj achieved with 1e20/cm3 active dopant InGaAs Xj=10nm Damage Free, Ultrashallow junctions, with high active dopant possible in III-V 10/15/
17 N D,eff (/cm 3 ) Column VI MLD and flash anneal promising 1E20/cm 3 active dopant achieved in InGaAs q/kt (/ev) Onset of agglomeration (Soak Anneal) Flash Soak Charged Voltage(kV) Damage Free, Ultrashallow junctions, with high active dopant possible in III-V Nd,eff = effective/ activated dopant concentration 10/15/
18 R sh ( /sq) Figure of merit for III-V junction Promising plasma and monolayer doping results 10 4 Plasma 10 3 Beamline Monolayer Doping Beamline challenging to achieve shallow X j and high N D 10 2 ~5e18 ~1e19 MLD, Plasma enables shallow X j and high N D 10 1 Target Target X 5E18 /cm 3 (nm) ~5e19 Active doping similar to in-situ doping (N D >5x10 19 cm -3 ) Junction depth targets are within reach 10/15/
19 Outline Overview III-V on Si Heterointegration Device Modules Device Results RRAM Memory Summary 10/15/
20 (cm 2 /Vs) Gate first 200 mm pilot line III-V devices using VLSI Si process infrastructure! Al M1 SEM decoration etch ILD W TiN Gate Uncorrected R SD corrected Si Reference III-V mesa um x x x10 13 III-V devices heterointegrated on Si in standard VLSI fab High thermal budget of Gate first process limits potential R. J. Hill SEMATECH, IEEE IEDM, 2010 n s (cm -2 ) 10/15/
21 I D [A/ m] Gate last InAs MOSHEMT results High performance short loop test structure 1E-3 1E-4 1E-5 1E-6 1E-7 Lg = 100 nm Lg = 130 nm Lg = 200 nm Lg = 250 nm I ON /I OFF > 3 orders S = 105 mv/dec V DS = 0.5 V E-8 1/3 V DD /3 V DD V G [V] 1E V GS [V] SS = 105 mv/dec. at L g = 100 nm with D it = 4 x /ev.cm 2 Significance: Low Temp Flow, InAs material give good Ion/Ioff & SCE T. Kim SEMATECH, IEEE VLSI Symp, /15/
22 g m,ext (ms/ m) Gate last InAs MOSHEMT benchmarking Short loop test structure with record performance g m,ext [ms/ m] Solid fill V DD = 0.5 V Open Symbol V DD = 1~2V [1] [7] [2] Q=25 This Work [10] [9] Q=15 [7] [8] Q=10 Lg = 100nm record g m,ext L g (nm) [8] [11] SS [mv/dec] Q=1 Q=0.5 Record RF and g m performance suggests module work (epi, gate, contact) progessing Impact: Good performance and short channel effects down to 100nm sub 50nm encouraging too. T. Kim SEMATECH, IEEE VLSI Symp, /15/
23 InAs benchmarking: injection velocity (v inj ) 4 InAs HEMT n ~ 13,000 cm 2 /V-s v x0 [10 7 cm/s] n ~ 9,500 cm 2 /V-s In 0.53 GaAs *Strain-Si *Si nfets V DS = 0.5 V (V DS = 1.1 ~ 1.3 V) L g [nm] - InAs MOSFET shows 2 X higher v inj than Si, even at V DS = 0.5 V - Consistent V inj depending on channel mobility 10/15/
24 InAs benchmarking: injection velocity (v inj ) 4 InAs HEMT n ~ 13,000 cm 2 /V-s v x0 [10 7 cm/s] n ~ 9,500 cm 2 /V-s In 0.53 GaAs n ~ 11,200 cm 2 /V-s InAs QW MOSFET *Strain-Si *Si nfets V DS = 0.5 V (V DS = 1.1 ~ 1.3 V) L g [nm] - InAs MOSFET shows 2 X higher v inj than Si, even at V DS = 0.5 V - V inj on short channel tracks long channel mobility (thus far) 10/15/
25 Outline Overview III-V on Si Heterointegration Device Modules Device Results RRAM Memory Summary 10/15/
26 Potential RRAM applications Case 1: System On Chip (embedded) Attributes BEOL integration Simple materials Speed, power, non-volatility Multi layers possible Monolithic, local storage Use HK/MG tools, etch learning Case 2: High Density (enand, SCM) Challenges Selector device Etch damage Low thermal budget needed Conformal processes CMP of BE (smooth) Patterning costs Parasitic R of metal lines 10/15/
27 Excellent memory test vehicle for NVM Center Cross Section Lower Currents With 1T1R M2 Source nfet Drain STI 1T1R (C p <50 ff) avoids wrong data 40nm Significance: Excellent Test structure ready for RRAM, STT-MRAM 10/15/
28 Hf metal counts Mechanism: RRAM filament seen with STEM / EELS TE Filament is: Conical 2.5nm at bottom One dominant CF RRAM conductive filament STEM Analysis by S. Privitera, S. Lombardo IMM-CNR, Catania, Italy BE Forming nm I BE ReRAM Hf-O breaks along grain boundary ; O diffusion Understanding needed for scalability, variability, endurance 10/15/
29 RRAM stack, structure, methods good Basics in place to test RRAM mfg readiness Significance: Engr RRAM for 3D compatibility & low variability/noise 10/15/
30 RRAM endurance improves Application space may increase Significance: Better Filament / Structures control improves cycling High density, SCM, embedded NAND applications may open up for RRAM 10/15/
31 RRAM cycling endurance Only 3 cyc Mean&Sigma from 50 cycles Significance: RRAM is fast, non-volatile, low power endurance & variability are improving 10/15/
32 Summary Scaling driven by new materials and architectures. Non-Planar III-V on Si Heterointegration: Selective MOCVD in ART promising for HVM. Etched fin profile demonstrated. MLD doping attractive damage free junction process RRAM Attractive for both embedded and NAND applications. Low reset currents achieved with fab friendly material set. AC endurance >344B cycles demonstrated. Variability and noise next issue to address (iedm 2012) 10/15/
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