Faculty Presentation: Novel Technologies

Transcription

1 2009 IMPACT Workshop Faculty Presentation: Novel Technologies Chenming Hu, EECS Department, UC Berkeley Tsu-Jae King Liu, EECS Department, UC Berkeley Eugene Haller, MS&E Department, UC Berkeley Nathan Cheung, EECS Department, UC Berkeley IMPACT NT 1 4/15/2009

2 Novel Technologies: Devices Your Photo Here Student: Jemin Park Faculty: Prof. Chenming Hu Title: Enhancing Speed and Power of 20nm-gate MOSFETs with Air Spacer IMPACT NT 2 4/15/2009

3 Motivation Gate-to-plug capacitance is a growing fraction of gate capacitance. Capacitance reduction provides for improved speed and reduced power. important as I ON and V DD are limited Evaluate the benefits of air spacers relative to oxide and nitride spacers. 3D device simulations 20nm technology node m1 S S G Bulk Bulk Ccp Cgc D m2 D IMPACT NT 3

4 In a 20nm MOSFET with oxide spacer, 77% of the gate charge is due to gate-to-plug/diffusion capacitances. Reduction of these capacitances will be an increasingly effective way to improve CV/I at the 20nm node and beyond. Unlike I ON enhancement, capacitance reduction can significantly reduce the transistor switching energy as well as delay. Nitride Spacer Simulation Results Oxide Spacer Air Spacer I ON (A/um) 1.16e e e-6 I OFF (A/um) 4.16e e e-9 Max Q GATE (Coul) 7.7e e e-16 Inverter Delay (ps) Inverter switching energy (fj) Gate switching charge (fc) IMPACT NT 4

5 Device Fabrication Process Flow Mask Oxide ILD1 (a) After S/D formation (d) Sacrificial spacer removal IMPACT NT 5 (b) ILD1 deposition ILD2 Air Spacer (e) ILD2 deposition (c) Chemical Mechanical Polishing Contact Sacrificial Oxide Gate Source/Drain Substrate

6 Future Goals Complete 3D device simulation study assess the impact of self-aligned contact (SAC) technology compare transistor performance for different spacer materials (silicon nitride vs. air) Fabricate and characterize air-spacer transistors IMPACT NT 6 4/15/2009

7 Novel Technologies: Devices Your Photo Here Student: Darsen Lu Faculty: Prof. Chenming Hu Title: FinFET Compact Model IMPACT NT 7 4/15/2009

8 Motivation FinFET technology is a leading candidate for CMOS scaling to sub-22nm nodes. FinFET SRAM variability comparison between experiment and SPICE simulation reported at last IMPACT Workshop The FinFET compact I-V model must accurately account for temperature and parasitic resistance. IMPACT NT 8

9 Temperature Model Verification V ds = 50mV: V ds = 1.0V: Drain Current ( A) C --> 200C in steps of 50C Increasing T Vgs (V) L G =60nm 20 fins -50C --> 200C in steps of 50C Drain Current (A) 1E-3 1E-6 1E-9 1E-12 1E-15 1E-3-50C --> 200C in steps of 50C Increasing T L G =60nm 20 fins Vgs (V) -50C --> 200C in steps of 50C Gm (ms) C --> 200C in steps of 50C L G =60nm 20 fins Increasing T Vgs (V) C --> 200C in steps of 50C Drain Current ( A) L G =60nm 20 fins IMPACT NT 9 Increasing T Vgs (V) Drain Current (A) 1E-6 1E-9 1E-12 Increasing T L G =60nm 20 fins Vgs (V) Gm (ms) L G =60nm 20 fins Increasing T Vgs (V)

10 Resistance Model Verification 240 L con and c dependences : Rectangular : Epi-shape Symbols:TCAD Lines: Model Rectangular S/D: R ds * W eff ( - m) c =2 x cm 2 c =1 x cm 2 c =3 x cm 2 Epitaxial (faceted) S/D: Lcon (nm) IMPACT NT 10

11 Future Goals Develop a non-quasi-static model for devices operating near f T Verify by comparing S-parameter simulations against measurements Accurately model output conductance by considering floating body effects Develop a model for low-voltage impact ionization effects Enhance the independent multi-gate model (BSIM-IMG) Modeling of back-channel inversion for independently-gated FinFETs Turn-key model for technology and product development IMPACT NT 11 4/15/2009

12 Novel Technologies: Devices Student: Nattapol Damrongplasit Faculty: Professor Tsu-Jae King Liu Title: Tunnel FET Variability Study IMPACT NT 12

13 Motivation: The CMOS Power Crisis Threshold voltage (V TH ) cannot be scaled down aggressively. Supply voltage (V DD ) has not been scaled proportionately. log I DS V DD I ON V DD V TH V TH I OFF V GS 0 VTH V DD S must be reduced to achieve desired I ON /I OFF with smaller V DD Source: P. Packan (Intel), 2007 IEDM Short Course IMPACT 13 K. Bernstein et al., IBM J. Res. Dev. 50-4/5, 2006:

14 3D Simulated Structure Gate Ge Source Drain I D = AE S exp(-b/e S ) IMPACT 14 Germanium-Source Tunnel FET A (m*/e G ) 0.5 B (m*e G3 ) 0.5 Tunneling occurs in the gated source (Ge) region small band-gap: E G = 0.66eV small effective mass: m* = 0.06m o S. H. Kim et al., 2009 Symp. VLSI Technology E F Energy-Band Diagram Gate Source E G,Ge E G,Si

15 Random Dopant Fluctuations (RDF) The methodology proposed by Sano [1] is used to investigate the impact of RDF within the Ge source. Only the long-range portion of the Coulombic potential for ionized dopant atoms is considered, in order to avoid unrealistic singularities in potential profile. In the future, the impact of RDF in the channel region will also be investigated. Nominal TFET TFET w/ RDF [1] N. Sano et al., On discrete random dopant modeling in drift-diffusion simulations: physical meaning of atomistic dopants, Microelectronics Reliability, vol. 42, no. 2,pp ,2002. IMPACT 15

16 Future Goals Complete 3-D device simulations to assess the contributions of various process-induced variations to V TH variation in Ge-source TFETs Gate length variation Gate oxide thickness variation Gate line-edge roughness (LER) Random dopant fluctuations (RDF) Assess the impact of V TH variation on TFET energyvs.-delay performance IMPACT 16

17 Novel Technologies: Materials & Processes Student: Chris Liao Faculty: Professor Eugene Haller Collaborator: Prof. Hartmut Bracht, University of Münster (Germany) Title: Radiation Enhanced Diffusion in Germanium IMPACT NT 17 4/15/2009

18 Motivation High-mobility channel materials such as Si 1-x Ge x and Ge are promising for improving CMOS performance and for voltage scaling Precise control of source/drain and channel dopant profiles is needed to suppress shortchannel effects Advanced modeling and control of diffusion requires an improved basic understanding of diffusion processes in SiGe and Ge S. Thompson et al., Intel Tech. Journal Q IMPACT NT 18

19 Experiment 5 MeV tandem accelerator and heater being built at LBNL 2.5 MeV protons from a tandem accelerator in Bochum, Germany Isotopically enriched 74 Ge/natural Ge multi-layer structure sample is thinned down to 30 μm Protons will pass through, leaving no end-of-range defects Sample is exposed to 1.5 μa proton beam through a 10-mm aperture at 600ºC for 90min IMPACT NT 19

20 Radiation-Enhanced Self-Diffusion in Ge Dashed line: as grown 74 Ge profile Red circles: proton irradiated Blue squares: non-irradiated IMPACT NT 20

21 Radiation-Enhanced Boron Diffusion B clustering IMPACT NT 21

22 Radiation-Retarded Phosphorus Diffusion P implanted at 30 kev with a dose of 3x10 15 cm -2 Dashed line: as-implanted P profile IMPACT NT 22

23 Future Goals Perform structural analysis (e.g. by TEM) of B clustering Continue study of radiation-enhanced Boron diffusion in Ge to determine the role of self-interstitials, for various proton fluxes and sample temperatures Study radiation-enhanced Carbon diffusion in Ge Believed to be interstitial-assisted Quantify the role of self-interstitials and vacancies on diffusion in Ge IMPACT NT 23

24 Novel Technologies: Metrology Student: John Gerling Faculty: Professor Nathan Cheung Collaborators: Mason Freed (KLA-Tencor) Josh Chien (Prof. Dornfeld, UCB ME Dept.) Title: Optical Metrology Wafer with Si Wafer Form Factor IMPACT NT 24 4/15/2009

25 Motivation Spectrometer for Process Monitoring: Molecules Optical Window Si3N4, SiO2 Stack Data Transmission 500 um Cavity LED* STO Dispersion Stack CCD* Data Acquisition* Bulk Silicon Wafer several mm *Internal Power Source Not Shown *In collaboration with KLA-Tencor (Mason Freed) Aluminum reflector l LED l 1 l 2 l nm 500 nm 600 nm 700 nm Detailed cross-section of metrology wafer cell with LED and strontium titanate (STO) high dispersion material on top of a CCD. CCD (200 um thick) Measurement of interface chemical kinetics and identification of precursors to enable quantitative reaction-rate modeling IMPACT NT 25 4/15/2009

26 Dispersion Stack Simulation 300 um thick strontium titanate (STO), sandwiched between 1 um aluminum reflectors with a 10 um wide entrance slit. Nitride window (@ wafer surface) will be sized to provide collimation function. Ray Exit Position, [um] Exit Ray Position at 9, 11, and 13 bounces, 70 deg incident, 1 deg collimation, 300 um STO Wavelength, [nm] 9th bounce 11th bounce 13th bounce 400 nm 500 nm 600 nm 700 nm Animation of dispersion phenomena in STO IMPACT NT 26

27 Experimental Verification Wavelength versus position at 3 rd bounce in prototype STO as observed by CCD. laser λ=535 nm S25 S22 S19 S16 S13 S10 S7 λ S4 S1 CCD STO λ=655 nm 121 S25 S22 S19 S16 S13 S10 S7 S4 S Pixel data of 655 nm and 535 nm light incident on dispersion stack and CCD. Data has been processed for noise and colored red/green for clarity. Grid lines on plot correspond to 5 um square pixel resolution of CCD. Prototype with three bounces shows 12nm/ m resolution. Improved version will have 8 bounces. Expected performance is ~3 nm/ m. IMPACT NT 27

28 New Application: CMP Slurry Characterization with CCD alone CCD camera is a 3-channel RGB detector 50 nm Colloidal Silica (Allied)* Change in Color, [%] R, 1 G, 1 B, 1 R, 2 G, 2 B, 2 Allied 50 nm Colloidal Silica % 20% 40% 60% 80% 100% Slurry Composition by Volume with DI H2O, [%] *In collaboration with Prof. Dornfeld CMP group (Josh Chien) IMPACT NT 28

29 Future Goals Demonstrate dispersion stack with 3 nm/um resolution. Explore RGB response of CCD as a three-channel spectrometer for process monitoring. Design and conduct proof-of-concept experiments for chemical precursor identification and interface kinetic process monitoring. IMPACT NT 29