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1 c Electronics N.V Modelling Compact of Submicron CMOS D.B.M. Klaassen Research Laboratories The Netherlands Eindhoven,
2 contents accuracy and benchmark criteria new applications í RF modelling advanced process technologies í new physical phenomena í process control and parameter statistics conclusions
3 need for standardization continuing series of SEMATECH Compact Model Workshops è accuracy and benchmark criteria compact models èand their parametersè í vital link in the circuit simulation chain interface between í technology engineers and circuit designers foundries and design houses qualitative & quantitative benchmark tests for compact models è accuracy evaluation of public-domain analog compact MOS models í BSIM3v3 from UC Berkeley èseptember 1995è í MOS MODEL 9 from èdecember 1993 in public domainè
4 mean deviation èèè 1 N NX I meas I meas, I sim linear region subthreshold region saturation region output conductance substrate current accuracy and benchmark criteria i=1
5 1 N accuracy and benchmark criteria mean deviation [%] 30 output conductance 10 mean deviation èèè NX 30 subthreshold I meas I meas, I sim i= gate length [micron] saturation linear MOS MODEL 9 BSIM3 averaged over whole geometry range
6 present-day compact models: accurate I-V modelling è process technologies down to 0.35 çm for new applications challenges from new applications? DP bipolar 1 µm NPN MEXTRAM CMOS 0.25µm N-channel CMOS 0.5 µm N-channel MOS MODEL 9
7 Vanoppen et al., IEDM'94 Klaassen et al., AACD'96 new applications RF circuit design in mainstream CMOS IC-process foundries supply compact model parameters for IC-processes public-domain analog compact MOS models literature on high-frequency verication of compact MOS models í MOS MODEL 9
8 air coplanar high-frequency probes ground-signal-ground conguration in special MOS structures common source-bulk conguration in new applications 200 um RF measurements ground ground bulk two-port S-parameter measurements HP8510B network analyzer 200 um on wafer signaal 1 signaal 2 gate drain source ground ground S- to Y-parameter conversion de-embedding procedure for parasitics
9 new applications: RF simulations intrinsic device: MOS model 9 : DC-parameters + oxide capacitance Drain Port 1 Gate R gate C gdo C gso C jun,d C jun,s R bulk Port 2 Source Bulk extrinsic elements: resistances: R ; R gate bulk capacitances: overlap : Cgd0 ; C gs0 junction : C jun,d ; C jun,s
10 common SB conguration Z in ç 1! C e gg j N-ch. 40è1 and 100è1 1 çm CMOS èv dd = 5 V è V ds = 5:0 V ; V gs = 2:0 V in = v in i in Z 5 ëdistributed" parallel segments Iout new applications Iin + Vin input impedance + R g
11 common SB conguration out i in v m! 2 R gc e dg C e gg, j! ç g mr gc e gg + C e ç dg, g,!r gc e gg 1+ N-ch. 40è1; 1 çm CMOS èv dd = 5 V è V ds = 4:0 V ; V gs = 4:0 V 2 3 L ç 2; poly and W L ç 2; poly Iout new applications Iin + Vin transconductance ç W R g = 0,
12 è maximum available power gain G max N-ch. 40è2; 1 çm CMOS èv dd = 5 V è V ds = 5:0 V ; V gs = 2:0 V N-ch. 20è0.5; 0.5 çm CMOS èv dd = 3:3 V è V ds = 3:5 V ; V gs = 3:5 V symbols: measurements lines: simulations è phase output conductance new applications bulk resistance bulk resistance í with without
13 new applications RF applications requirements for compact models í accurate charge model í junction and overlap capacitances í gate and bulk resistance è MOS MODEL 9 gives an accurate description of HF behaviour
14 present-day compact models accurate process technologies down to 0.35 çm for velocity overshoot non-local carrier heating gate tunnelling... advanced process technologies possible requirements for future process technologies í incorporation of new physical phenomena í process control and parameter statistics
15 new physical phenomena A.H. Montree et al., ESSDERC'96: optimized I-line photolithography dry etching of BARC 5.5 nm gate-oxide mean deviation [%] 30 output conductance LOCOS eld isolation advanced retrograde well twin shallow junction extensions 10 double avoured poly TiSi 2 salicidation 30 subthreshold 10 saturation 3 linear 1 MOS MODEL 9 BSIM gate length [micron] 0.25 çm process 18 geometries
16 L poly = 0:18 çm è L e = 0:13 çm è 350 nm LOCOS 4 nm gate-oxide 200 nm polysilicon + 40 nm TEOS E-beam patterning, spacer formation, SèD implant silicidation new physical phenomena TEOS spacers J. Schmitz et al., ESSDERC'96: TiSi2 Gate TiSi2 Source P-type wafer Pockets (optional) Drain poly etch HClèHBr shallow drain extension implant è V supply = 1:8 V
17 new physical phenomena: N-channel L e = 0:13 çm linear region saturation region measurements symbols: MOS MODEL 9 lines:
18 new physical phenomena: N-channel L e = 0:13 çm subthreshold region output conductance measurements symbols: MOS MODEL 9 lines:
19 MOS MODEL 9 describes down to L e = 0:13 çm devices no need to take new phenomena è velocity overshootè èe.g. new physical phenomena: N-channel L e = 0:13 çm all physical eects well-modelled into account avalanche generation measurements symbols: MOS MODEL 9 lines:
20 present-day compact models will be accurate è process technologies down to 0.18 çm for new physical phenomena mean deviation [%] 30 output conductance subthreshold saturation linear MOS MODEL gate length [micron] BSIM3
21 ç, V Tè V ds, èvgs saturation current gs =V ds =V supply è èv ç 1 + new physical phenomena mobility reduction 4 series resistance minimum-length devices 3 2 lateral electrical field 1 transversal electrical field design rule contributions almost è constant technology scaling ç 2 ç ds V I ds = 2 F èvgs ; V ds ;R seriesè
22 process control & parameter statistics SIA roadmap... supply voltage [V] gate length [micron]... rapidly decreasing supply voltage
23 process control & parameter statistics supply voltage [V] 4 CIRCUIT 3 2 delay power gate length [micron] DEVICE MM9 W/L arbitrary variation threshold voltage [mv] VTO K θ γ PROCESS fingerprinting tox Dvt temp gate length [micron]
24 control & parameter statistics process process technology IC design implantations anneals oxidations... EoL measurements threshold voltage current drive subthreshold swing... circuit performance compact model parameters threshold voltage gain factor body-effect factor...
25 process control & parameter statistics ëdirect extraction" Ids curve tting Vsb1(1)=0V Vsb1(2) Vgate(3) Vsb2(1) Vsb2(2) Vgate(2) Vgate(1) Vt0 Vgs èv gs, V Tè V ds + ç1 èvgs, V Tè 1 I ds =
26 process control & parameter statistics W = L = 10 çm worst 3 different V -implants t 3 different V -implants t best common threshold-adjust implantation for n- and p-channels
27 3 3 3 process control & parameter statistics 0 slow fast W = L = 10 çm parameter correlations have to taken into account be è principal components devices with arbitrary geometry? è process block
28 0.8 çm process intra-batch spread of process control & parameter statistics M.J. van Dort et al., IEDM'95: currents of saturation n- and p-channels minimum-length samples
29 distribution gate delay 21-stage ring oscillator process control & parameter statistics CIRCUIT delay power... DEVICE MM9 W/L arbitrary VTO K θ γ PROCESS fingerprinting tox Dvt temp samples
30 Experiments Mizuno et al., í í Eisele et al., process control & parameter statistics L W source W dep drain IEEE TED 41, 2216 è1994è IEDM'95, 67 è1995è = L = 0:25 çm W = cm,3 N + dep ç 1000; n p ndep ç 30 + uctuations are of the order stochastic of several percents
31 process control & parameter statistics How do these intrinsic variations aect device performance?
32 due to dopant uctuations spread in increased process control & parameter statistics P.A. Stolk et al., IEDM'96: threshold voltage í leakage current í subthreshold swing í linear current í
33 increased spread in threshold voltage í process control & parameter statistics extract compact model parameters í gain factor subthreshold-slope parameter í ëtransition" parameter í í mobility reduction parameter
34 process control & parameter statistics correlations study parameters... between
35 control & parameter statistics process set of I-V curves parameter extraction I lin +_ σ I lin compact model parameters V TO +_ σ V ; TO β+_ σ β ; θ 1 +_ σ θ 1 ;... predictability
36 present-day compact models will be accurate process technologies down to 0.18 çm for incorporation of parameter statistics in circuit simulation crucial obtain a realistic design window to advanced process technologies è fast parameter extraction methods essential!
37 Technology Characterisation & Modelling Group Microelectronics Research Centre, Ireland National acknowledgements many colleagues... í Research Laboratories í Semiconductors JESSIèESPRIT Project ADEQUAT+
38 interface between foundries and design houses í accuracy and benchmark criteria í accurate charge model í incorporation of parasitic elements í present-day compact models will be accurate down to 0.18 çm è incorporation of parameter statistics í summary & conclusions standardization eorts è present-day compact models èi-vè accurate down to 0.35 çm RF applications require advanced process technologies è evolutionary development of present-day compact models
mobility reduction design rule series resistance lateral electrical field transversal electrical field
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