Future Trends in Microelectronics Impact on Detector Readout. Paul O Connor
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1 Future Trends in Microelectronics Impact on Detector Readout Paul O Connor
2 Outline CMOS Technology Scaling Analog Circuits Radiation Effects Cost Detector Development Symposium Paul O'Connor BNL April 5,
3 Edwin Hubble Detector Development Symposium Paul O'Connor BNL April 5,
4 Gordon Moore Detector Development Symposium Paul O'Connor BNL April 5,
5 CMOS Logic Element Pair of nearly-ideal switches in series Complementary polarity common control voltage input impedance ~ V DD -tolerant Zero static power V DD Detector Development Symposium Paul O'Connor BNL April 5,
6 MOSFET Scaling 20V 4V Voltages, dimensions reduced by α Results: r E = Conductance Capacitance Speed I / V I / CV const. const. 1 α α Switching energy Power/gate Density Power density CV 2 CV f α 1 2 α 2 α const. Detector Development Symposium Paul O'Connor BNL April 5,
7 Industry Scaling Roadmap New generation every ~2 years with α = 2 L g (1970) 8 µm (2007) 18 nm 180 Detector Development Symposium Paul O'Connor BNL April 5,
8 Transistor Count 10 9 MOSFETs Intel386 Intel486 Pentium 4 Pentium III Pentium II Pentium Pro Pentium 2.5e Year Detector Development Symposium Paul O'Connor BNL April 5,
9 CPU Clock Frequency Hz Intel386 Intel486 Pentium Pentium Pro/II/III Pentium 4 4e Year Detector Development Symposium Paul O'Connor BNL April 5,
10 Transistor Cost 10 0 $ e Year Detector Development Symposium Paul O'Connor BNL April 5,
11 Digital State of the Art 65 nm node: SRAM test chip Nov production Nov crossover 3Q nm node: 153MB SRAM Jan >10 9 MOSFETs production 3Q 07 Detector Development Symposium Paul O'Connor BNL April 5,
12 Failures of Classical Scaling ignores kt ignores mobility degradation and velocity saturation ignores fringing capacitance ignores tunneling ignores atomistic effects ignores industry economics Detector Development Symposium Paul O'Connor BNL April 5,
13 kt 0 MOSFET in weak inversion when V gs < V th : I D q( VGS VTH ) nkt = I0e Ioff = I0 e qv nkt TH Can t continue to scale V TH Tradeoff of speed for leakage current (static power) Multi-V TH processes V DD kt V TH fast low power Detector Development Symposium Paul O'Connor BNL April 5,
14 Gate tunneling current Significant tunneling through SiO 2 when t ox < 3nm J tunnel increases 100X per generation Replace SiO 2 with high-κ dielectric (?) ε 2 EOT = SiO t hi κ ε hi κ Multi-t ox processes Detector Development Symposium Paul O'Connor BNL April 5,
15 Atomistic Effects random dopant distribution oxide thickness variation line edge roughness σv TH, RTS σv TH, σj tunnel, σµ σv TH A. Asenov, IEEE Trans. Electron Dev. 50(9), 1837 (2003) Detector Development Symposium Paul O'Connor BNL April 5,
16 Scaling in Practice Until 180nm node: follow classical scaling with α = 2 2.8X performance per generation Now: continue (super) scaling L g sub-scaling of t ox V DD, V TH have stopped scaling Gate density and speed continue to scale Increase of E, conductance Switching energy decreases only by 1/α not 1/α 3 Power density increase ~ α Static power from leakage, gate tunneling make power problem worse SiO 2 lattice constant 3 kt/q Detector Development Symposium Paul O'Connor BNL April 5,
17 Power is biggest impediment to further scaling L G -1 L G -4 E. Nowak, IBM J. Res. & Dev. 45(2), 169 (2002) Detector Development Symposium Paul O'Connor BNL April 5,
18 Next-generation Transistors Strain Engineering UTSOI, DG-FET High-k gate dielectric Reduce mobility degradation Suppress SCE through improved electrostatics Suppress Jtunnel M. Bohr, Intel, 2003 IEDM F.-L. Yang et al., IMEC, 200 VLSI Symp. S. Thompson, Intel,IEEE T-ED 51(11), 1790 (2004) Detector Development Symposium M. Ieong, IBM, Sol. State and IC Tech Paul O'Connor BNL E. Gusev et al., IBM, 2004 IEDM April 5,
19 SiGe Heterojunction Bipolar Transistor (HBT) Power-performance ~ 2X standard CMOS at same feature size Cost also ~ 2X Provides 3 4 year head start over CMOS Eventually CMOS provides better cost-performance Detector Development Symposium Paul O'Connor BNL April 5,
20 Analog: Speed, Gain & Matching Speed/intrinsic gain tradeoff f T ~ 1/L G for min-l G devices Output conductance g ds sensitive to geometry and bias Gain g m /g ds severely degraded in ultra-scaled devices: failure to adhere to classical constant-e scaling Threshold Mismatch Dopant fluctuations: σ VTH, LG min ~ α Overcome by increasing W*L Power penalty ft, GHz ft gm/gds Technology Node, nm g m /g ds nm f T, Hz m nm P, W Pelgrom, Philips, 1998 IEDM Detector Development Symposium Paul O'Connor BNL April 5,
21 Analog Low-V Challenges DD Increasing ratio of V TH /V DD rules out use of many classical analog design toplogies, e.g. cascodes. To achieve same performance at lower V DD, analog circuits need increased power. 100X Power 4X SNR SNR, BW held constant 10 4 Power held constant (performance limited by thermal noise) Dynamic Range Min. Feature Size, um 10 uw 100 uw 1000 uw A. Annema et al., IEEE JSSS 40(1), 132 (2005) Detector Development Symposium Paul O'Connor BNL April 5,
22 Noise in scaled CMOS For CSA, consider noise in relation to gate capacitance Thermal noise improvement from higher f T : ENC th ~ 1/α 1/f noise depends on interface trap density, device area, inversion charge density no consistent trend with scaling Choice of L,W for minimum noise needs to account for moderate inversion operation Gate leakage current shot noise (parallel) Energy Resolution [ENC] ENC (rms e - ) TECHNOLOGY SUPPLY COST/RUN 0.35µm 3.3V 14k$ 0.25µm 2.5V 19k$ 0.18µm 1.8V 32k$ Preamplifier Power [mw] P O'Connor and G. De Geronimo, Prospects for charge sensitive amplifiers in scaled CMOS, NIM A480, 713 (Mar. 2002) G. Anelli 2005 Detector Development Symposium Paul O'Connor BNL April 5,
23 Radiation Tolerant Inverter NMOS Enclosed Layout Transistor (ELT) PMOS p+ guard ring DRAIN V DD GATE GATE SOURCE OUT IN DRAIN SOURCE metal 1 polysilicon n+ diffusion p+ diffusion contact to diffusion Detector Development Symposium Paul O'Connor BNL April 5,
24 Radiation Effects below 0.25µm Thinner gate oxides more tolerance to Total Ionizing Dose Thick field oxide charging edge leakage in NMOS loss of isolation NWELL- NWELL 0.13µm IBM technology harder than 0.25µm: non-elt devices OK except narrow/thick-oxide NMOS to 70 Mrad+ lateral isolation OK, no guard ring needed SEU cross section higher, lower critical charge No radiation-induced SEL ELT non-elt F. Faccio, CERN, FEE Workshop Snowmass 2003 Detector Development Symposium Paul O'Connor BNL April 5,
25 Fab Line Cost $B Electronic Materials Prof. Dr. Helmut Föll University of Kiel; Faculty of Engineering Detector Development Symposium Paul O'Connor BNL April 5,
26 Mask Set and Fabrication Cost MASK SET ENGINEERING RUN $M Technology Cost/run ($M) Cost/mm^2 ($) 0.5um 0.35um 0.25um 0.18um 0.13um Technology Detector Development Symposium Paul O'Connor BNL April 5,
27 Example - BNL ASIC Design Group Develops Low Noise FEE for gas and semiconductor detectors accelerator experiments medical imaging astrophysics homeland security 70% Federal, 30% commercial Staff 5 ASIC professionals 1 DAQ engineer 1 Technician CAD suite and test labs 7 8 runs/year through MOSIS 0.35, 0.25, and 0.18um mixed-signal CMOS 5K 600K MOSFETs per chip $20K $80K per MPW run Development cost per design ~ $200K x no. revisions needed Detector Development Symposium Paul O'Connor BNL April 5,
28 Summary Power dissipation is the major obstacle to further CMOS scaling. Foundry and mask costs going up as process options (multi-v th, multi-t ox, HBT, passives, etc.) added for SOC. Analog design is compromised by the low supply rail. Except for high radiation resistance and packing density, ultra-scaled technologies offer few advantages to justify their enormous cost. Plenty of opportunity to innovate in (n-4)-generation CMOS. Detector Development Symposium Paul O'Connor BNL April 5,
29 Bon Appétit! Detector Development Symposium Paul O'Connor BNL April 5,
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