Previously. ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Variation Types. Fabrication

Transcription

1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Previously Understand how to model transistor behavior Given that we know its parameters V dd, V th, t OX, C OX, W, L, N A Day 13: September 27, 2013 Variation C GC C GCS 1 C GCB 2 But We don t know its parameters (perfectly) 1. Fabrication parameters have error range 2. Identically drawn devices differ 3. Parameters change with environment (e.g. Temperature) 4. Parameters change with time (aging) Why I am more concerned with robustness than precision. 3 Today Sources of Variation Fabrication Operation Aging Coping with Variation Margin Corners Binning 4 Variation Types Fabrication Many reasons why things are different Show up in many different ways. Scales Wafer-to-wafer, die-to-die, transistor-totransistor Correlations Systematic, spatial, random (uncorrelated) 5 6 1

2 Process Shift Oxide thickness Doping level Layer alignment Growth and Etch rates and times Depend on chemical concentrations How precisely can we control those? Source: Noel Menezes, Intel ISPD Vary machine-to-machine, day-to-day Impact all transistors on wafer 8 Systematic Spatial Parameters change consistently across wafer or chip based on location FPGA Systematic Variation 65nm Virtex 5 Chemical-Mechanical Polishing (CMP) Dishing Lens distortion 9 [Tuan et al. / ISQED 2010] 10 Oxide Thickness Line Edge Roughness 1.2µm and 2.4µm lines [Asenov et al. TRED 2002] From:

3 Optical Sources Phase Shift Masking What is the shortest wavelength of visible light? How compare to 45nm feature size? Today s chips use λ=193nm Source Line Edges (PSM) Intel 65nm SRAM (PSM) Source: 15 Source: 16 Statistical Dopant Placement Random Trans-to-Trans Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates Stochastic process 17 [Bernstein et al, IBM JRD 2006] Transistors differ from each other in random ways 18 3

4 Impact Source: Noel Menezes, Intel ISPD Changes parameters W, L, t OX, V th Change transistor behavior W? L? ν sat C OX W V GS V T V DSAT t OX? 2 W = µ n C OX ( V L GS V T )V DS V 2 DS 2 20 Example: V th V th 65nm Many physical effects impact V th Doping, dimensions, roughness Behavior highly dependent on V th ν sat C OX W V GS V T V DSAT 2 = I Sʹ W e L V GS V T nkt / q 1 e V DS kt / q 1+ λv DS ( ) [Bernstein et al, IBM JRD 2006] Impact of V th Variation? Impact Performance Higher V TH? Not drive as strongly I d,vsat (V gs -V TH ) Performance? V th I ds Delay (R on * C load )

5 Impact of V th Variation FPGA Logic Variation Xilinx Virtex 5 65nm Altera Cyclone-II 90nm Think NMOS Vgs = Vdd 25 [Tuan et al. / ISQED 2010] [Wong, FPT2007] 26 Variation in 65nm FPGAs LUT-to-LUT Same LAB LAB (27,22) average 5% variation [Gojman, FPGA2013] DeHon May [Gojman, FPGA2013] DeHon May Delay Map Two LUT2LUT across Chip LAB (27,22) [Gojman, FPGA2013] DeHon May DeHon May

6 Reduce Vdd (Cyclone IV 60nm LP) Impact of V th Variation? Lower V TH? Not turn off as well leaks more [Gojman, FPGA2013] DeHon May = I Sʹ W e L V GS V T nkt / q 1 e V DS kt / q 1+ λv DS ( ) Operation Temperature Voltage Borkar (Intel) Micro 37 (2004) Temperature Changes Different ambient environments January in Maine July in Philly Air conditioned machine room Self heat from activity of chip Quality of heat sink (attachment thereof) Self Heating = I Sʹ W e L V GS V T nkt / q 1 e V DS kt / q 1+ λv DS ( ) 35 Borkar (Intel) Micro 37 (2004) 36 6

7 How does temperature impact on-current? Thermal Profile for Processor High temperature More free thermal energy Easier to conduct Lowers Vth Increase rate of collision Lower saturation velocity Lower saturation voltage Lower peak Ids slows down One reason don t want chips to run hot 37 [Reda/IEEE Tr Emerging CAS v1n2 2011] 38 How does temperature impact leakage current? Temperature and Ids High temperature Lowers Vth VGS VT nkt / q 39 W IDS = ISʹ e L VDS 1 e kt / q (1+ λvds ) 40 Voltage Power supply isn t perfect Differs from design to design Aging Board to board? How precise is regulator? Hot Carrier NBTI IR-drop in distribution Bounce with current spikes

8 Hot Carriers Trap electrons in oxide Also shifts V th NBTI Negative Bias Temperature Instability Interface traps, Holes Long-term negative gate-source voltage Affects PFET most Increase V th Partially recoverable? Temperature dependent 43 Another reason not to run hot. 44 [Stott, FPGA2010] Measured Accelerated Aging (Cyclone III, 65nm FPGA) Coping with Variation 45 [Stott, FPGA2010] 46 Variation Impact of V th Variation See a range of parameters L: L min L max V th : V th,min V th,max Higher V TH Not drive as strongly I d,vsat (V gs -V TH ) ν sat C OX W V GS V T V DSAT 2 Lower V TH Not turn off as well leaks more 47 = I Sʹ W e L V GS V T nkt / q 1 e V DS kt / q 1+ λv DS ( ) 48 8

9 Variation Margin for expected variation Must assume V th can be any value in range Speed assume V th slowest value Probability Distribution I on,min =I on (V th,max ) I d,vsat (V gs -V th ) Gaussian Distribution V TH 49 From: 50 Impact Impact Given V th,nom = 250mV Sigma 25mV Probability of 100 transistor circuit in range when each has 96% prob.? when each has 99.8% probability? Given V th,nom = 250mV Sigma 25mV What maximum V th should expect to see for a circuit of 100 transistors? 1000 transistors? 10 9 transistors? Variation Margining See a range of parameters L: L min L max V th : V th,min V th,max Validate design at extremes Work for both V th,min and V th,max? Design for worst-case scenario Also margin for Temperature Voltage Aging: end-of-life

10 Process Corners Many effects independent Many parameters With N parameters, Look only at extreme ends (low, high) How many cases? Try to identify the {worst,best} set of parameters Slow corner of design space, fast corner Use corners to bracket behavior 55 Simple Corner Example Vthp 350mV 150mV 150mV Vthn 350mV What happens at various corners? 56 Process Corners Many effects independent Many parameters Try to identify the {worst,best} set of parameters E.g. Lump together things that make slow Vthn, Vthp, temperature, Voltage Try to reduce number of unique corners Slow corner of design space Use corners to bracket behavior 57 Range of Behavior Still get range of performances Any way to exploit the fact some are faster? Probability Distribution Delay 58 Speed Binning Idea Probability Distribution Sell Premium Delay Sell nominal Sell cheap Discard Parameters Approximate Differ Chip-to-chip, transistor-to-transistor, over time Robust design accommodates Tolerance and Margins 59 Doesn t depend on precise behavior 60 10

11 Midterm 1 Admin Contents should not be a surprise Identify CMOS/non-CMOS Identify CMOS function Any logic function CMOS gate Noise Margins Circuit quasistatic configuration and switching delay Midterm Monday 7 9pm in Towne 309 Previous midterm Solutions linked to syllabus But only one midterm in 2010 so parts more advanced than where we are now Review on Sunday 5:30pm