Extending the Era of Moore s Law

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1 14 nm chip X SEM from bohr 2014 idf presentation.pdf Extending the Era of Moore s Law Tsu Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley September 11, 2017 SPIE Photomask Technology + EUV Lithography Conference

2 IC Technology Advancement Gordon E. Moore, Cramming more Components onto Integrated Circuits, Electronics, pp , April 1965 The minimum cost point moves to a larger number of components per IC over time, with advancements in manufacturing technology. Investment Transistor Scaling Market Growth Lower Cost/Component Higher Performance 2

3 Outline Transistor Scaling to the Limit Extending the Era of Moore s Law Summary

4 Transistor Basics Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) Gate length, L G log (CURRENT) I ON Channel width, W I OFF Inverse slope is subthreshold swing, S [mv/dec] Electron Energy Band Profile n(e) exp ( E/kT) 0 V TH GATE VOLTAGE V DD v eff increasing E Source increasing V GS distance Drain I W v Q D inv Q inv C ox ( V V ) TH GS 4

5 Complementary MOS Devices & Circuits CIRCUIT SYMBOLS N channel P channel MOSFET MOSFET G S D ON if V G >V S +V TH G S D ON if V G <V S V TH CMOS NAND GATE CMOS INVERTER CIRCUIT V0 DD V V IN 0 V V DD NOT AND (NAND) TRUTH TABLE S OFF ON D D OFF ON S V =0 =VV OUT DD V DD V OUT 0 V DD INVERTER LOGIC SYMBOL STATIC MEMORY (SRAM) CELL V IN WORD LINE BIT LINE 0 1 or or 1 0 BIT LINE 5

6 CMOS Technology Scaling XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc.) 90 nm node 65 nm node 45 nm node 32 nm node T. Ghani et al., IEDM 2003 (after S. Tyagi et al., IEDM 2005) K. Mistry et al., IEDM 2007 P. Packan et al., IEDM 2009 strained Si eff high-k/metal gate C ox 6

7 Design for Manufacturing courtesy Mike Rieger (Synopsys, Inc.) SRAM bit cell layouts C. Webb, Intel Technology Journal, vol. 12, No. 2, pp , 2008 PG PU PD PU PD PG PD PG PU PU PG PD 90 nm 65 nm 45 nm 7

8 6-T SRAM Cell Impact of Misalignment Desired layout (6 T SRAM cell) Actual layout w/ lateral misalignment (gate length variations) PD PU PG PG PU PD L g reduced L g increased Actual layout (corner rounding) Actual layout w/ vertical misalignment (channel width variations due to active jogs) W reduced W increased 8

9 6-T SRAM Cell Double Patterning of Gate Desired layout (6 T SRAM cell) Actual layout after 1 st gate patterning PD PU PG PG PU PD Actual layout after active patterning Actual layout after 2 nd gate patterning (no gate length variation) 9

10 Impact of Variability on SRAM STATIC MEMORY (SRAM) CELL WORD LINE BUTTERFLY CURVES V SN2 V DD SNM1 SN1 SN2 BIT LINE BIT LINE SNM2 V SN1 0 V DD Pre charged to V DD V TH mismatch results in reduced static noise margin. lowers cell yield and/or limits V DD scaling Immunity to short channel effects needed! 10

11 Short Channel Effects Gate C ox C dep Source Body Drain V TH decreases with decreasing L g and with increasing V DS : log I D Source Drain Increased capacitive coupling between Gate and channel provides for better Gate control, hence reduced SCE V GS 11

12 FinFET/Tri Gate Transistor H Fin L G W Fin GATE Source Gate 10 nm SOURCE 20 nm Drain D. Hisamoto et al. (UC Berkeley), IEDM nm L g FinFET DRAIN log I D V DD S I ON C C total V GS ox Superior gate control higher I ON /I OFF or lower V DD Multiple fins can be connected in parallel to achieve higher ON state drive current. Y. K. Choi et al., (UC Berkeley) IEDM 2001 Intel Corp., May

13 SiGe SOI Spacer Lithography Y. K. Choi, T. J. King, and C. Hu, IEEE Trans. Electron Devices, Vol. 49, No. 3, pp , 2002 a.k.a. Sidewall Image Transfer (SIT) and Self Aligned Double Patterning (SADP) 1. Deposit & pattern sacrificial layer 3. Etch back mask layer to form spacers SiGe SOI BOX BOX 2. Deposit mask layer (SiO 2 or Si 3 N 4 ) SiGe SOI BOX 4. Remove sacrificial layer; etch SOI layer to form fins fins BOX Note that fin pitch is 1/2 that of patterned layer 13

14 MOSFET Evolution 32 nm planar FinFET: 22 nm thin body beyond 7 nm Stacked stacked nanosheets nanowires? P. Packan et al. (Intel), IEDM 2009 FD SOI: Intel Corp. K. Cheng et al. (IBM), VLSI Symp N. Loubet et al. (IBM, Samsung, GLOBALFOUNDRIES) C. Dupré et al. (CEA LETI) Symp. VLSI IEDM Tech Stacked gate all around (GAA) FETs achieve the highest layout efficiency. 14

15 Channel Length Scaling Limit Quantum mechanical tunneling sets a fundamental scaling limit for the channel length (L C ). If electrons can easily tunnel through the source potential barrier, the gate cannot shut off the transistor. nmosfet Energy Band Diagram (OFF state) SOURCE DRAIN E C J. Wang et al., IEDM Technical Digest, pp , 2002 E C 15

16 1 nm Gate Length MOSFET S. B. Desai et al., Science, Vol. 354, No. 6308, pp , 2016 A 1 nm diameter CNT gated MoS 2 MOSFET is demonstrated with ON/OFF current ratio 10 6 (V DD 1 V) Heavier m eff (0.45m 0 vs. 0.26m 0 in Si) Bandgap energy 1.3 ev 16

17 Future Logic Switches Future Drain Current 1/S Today Energy Today Future Gate Voltage Delay Higher I ON /I OFF ratio lower minimum Energy/op Steeper switching behavior needed (S < 60mV/dec) 17

18 Outline Transistor Scaling to the Limit Extending the Era of Moore s Law Summary

19 Self Aligned Double Patterning Cross sectional View Plan View 19

20 Multiple patterning techniques have extended Moore s Law beyond the lithographic resolution limit at increasing cost Normalized Cost and Steps Single Exposure Cost Steps LELE Single Spacer Samsung, EUVL Symposium 2009 ASML, SPIE Advanced Lithography 2012 Double Spacer The sheer cost and complexity of this lithographic solution could dissuade chipmakers from jumping to future nodes, thereby stunting the growth rates of the IC industry. Semiconductor Engineering, April 17 th, /25/2016 Sang Wan Kim 20 20

21 Tilted ion implantation (TII) Approach A sub lithographic damage region can be achieved by tilted ion implantation (TII) + photoresist/hard mask self aligned to pre existing mask features on surface 21

22 Impact of TII on SiO 2 Etch Rate S. W. Kim et al., SPIE Advanced Lithography 2016 Ar + implant conditions: 15 tilt; 1.5 kev; dose = 0, 2 or 3 x /cm Etch rate [Å/sec] 1.5 3E14 2E14 ~6X ~9X no implant SiO 2 Depth [Å] 3E14 2E Damage [x10 22 /cm 3 ] Symbols & solid lines: etch rate in 200:1 DHF Dotted lines: damage profile (SRIM) 22

23 Double Patterning by TII Thermal SiO 2 : masking layer Formation of linear a-si hard-mask features by spacer patterning hard mask SiO 2 23

24 Double Patterning by TII θ Thermal SiO 2 : masking layer Formation of linear a-si hard-mask features by spacer patterning hard mask Si y First implant: positive tilt angle x W trench y(tan(θ) cot(α)) α α SiO 2 x x Silicon W trench 24

25 Double Patterning by TII Thermal SiO 2 : masking layer Formation of linear a-si hard-mask features by spacer patterning hard mask First implant: positive tilt angle x W trench y(tan(θ) cot(α)) Second implant: negative tilt angle x W trench y(tan(θ) cot(α)) SiO 2 25

26 Double Patterning by TII Thermal SiO 2 : masking layer Formation of linear a-si hard-mask features by spacer patterning hard mask Si y First implant: positive tilt angle x W trench y(tan(θ) cot(α)) α Second implant: negative tilt angle x W trench y(tan(θ) cot(α)) SiO 2 x W fin x x Silicon W fin x Selective removal of damaged SiO 2 Si substrate dry etch W fin 2y(tan(θ) cot(α)) W trench 26

27 Proof of Concept: Single Implant S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016 Cross sectional Scanning Electron Micrographs Ar-ion implantation with θ = etched a-si remaining a-si Si substrate Si substrate Sub lithographic features (~45 nm) achieved by 15 tilt, 3.0 kev Ar + implant into 10 nm thick SiO 2 hard mask dilute HF etch Si dry etch 27

28 Self Aligned Nature of TII Patterning P. Zheng et al. (UC Berkeley), IEEE Transactions on Electron Devices, vol. 64, no. 1, pp , 2017 The TII defined edge closely tracks the HM edge = a Si hard mask = un etched c Si = etched c Si 28

29 Line Edge Roughess Comparison P. Zheng et al. (UC Berkeley), IEEE Transactions on Electron Devices, vol. 64, no. 1, pp , samples, 2.74 µm long TII improves low and mid frequency line edge roughness 29

30 TII Patterning Resolution Limit P. Zheng et al. (UC Berkeley), IEEE Transactions on Electron Devices, vol. 64, no. 1, pp , 2017 Error bars represent 1 standard deviation TII can be used to pattern features as small as 10 nm. 30

31 Double Tilted Implant Results S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016 Cross-sectional SEM Plan-view SEM 1 15 LTO 3 a-si 2 Si substrate Local pitch halving achieved with ±15 tilt, 3.0 kev Ar + implants ~21 nm half pitch of the etched Si features 31

32 Double Patterning Approaches Spacer lithography (SADP) Silicon 32

33 Double Patterning Approaches Spacer lithography (SADP) Tilted Ion Implantation (TII) PR PR SiO 2 (Oxidation) PR Silicon Silicon 33

34 Double Patterning Approaches Spacer lithography (SADP) Tilted Ion Implantation (TII) Hard mask (CVD) SiO 2 (Oxidation) SiO 2 (Oxidation) Silicon Silicon SiO 2 (Oxidation) Silicon Silicon The cost of TII double patterning can be only ~60% of the cost of SADP. Silicon

35 Sub Lithographic Hole Formation S. W. Kim et al. (UC Berkeley), Journal of Vacuum Science & Technology B, vol. 34, , 2016

36 Future Work: 2D Patterning by TII 1. Coat IC layer with HM layer; < P min 2. Perform multiple litho+tii processes in sequence, such that each litho+tii process forms a latent 1D pattern in the HM layer; < P min /2 < P min /2 P min /2 < P min < Pmin/2 P min /2 P min /2 Implant Direction P min /2 A B 3. Selectively etch the HM layer to form the composite 2D pattern; P min /2 D C P min /2 4. Transfer the 2D pattern to the IC layer by a selective etch process. 36

37 Outline Transistor Scaling to the Limit Extending the Era of Moore s Law Summary

38 Summary There s still plenty of room for CMOS technology scaling! Advancements in transistor structures and materials will enable continued miniaturization and voltage scaling. Innovations to mitigate the challenge of growing cost of patterning are needed to extend the era of Moore s Law New Innovations Investment Lower Cost/Function Lower Power Market Growth 38

39 Acknowledgements TII Enhanced Lithography: Dr. Sang Wan Kim (now with Ajou University) Dr. Peng Zheng (now with Intel Corporation) Dr. Leonard Rubin (Axcelis Technologies) UC Berkeley Marvell Nanofabrication Laboratory Funding from Applied Materials, Lam Research, National Science Foundation 39

40 3 D NAND Flash Technology Vertical FETs (vfets): Poly Si is used as the semiconductor material. Lithography steps for multiple memory layers are shared. Density scaling is not driven by lithography. Aspect ratios of etched and filled features are large (>40:1). 40

41 Heterogeneous Integration Enhanced performance & functionality in a compact form factor Separate layer fabrication processes Integrated fabrication process MEM relay Metal Insulator Interconnects CMOS layer J. J. Q. Lu et al., Future Fab Int l, Issue 23, 2007 Si substrate V. Pott et al., Proc. IEEE, Vol. 98,

42 IC Technology Advancement D. C. Edelstein, 214th ECS Meeting, Abstract #2073, 2008 Intel s 14nm CMOS technology Time Advanced back end of line (BEOL) processes have air gapped interconnects S. Natarajan et al. (Intel), IEDM

43 Reconfigurable Interconnect K. Kato et al., IEEE Electron Device Letters, vol. 37, no. 12, pp , I/O 0 Program 0 Program 0 Program 0 Bit Line (BL) Movable electrode I/O 1 Program 1 Program 1 Program 1 A bi stable switch is implemented using multiple metal layers Vias are for electrical connection and flexural elements for a more compliant electrode, for lower programming voltage. Small footprint due to vertically oriented movable electrode, and shared actuation and contacting electrodes across the array A non linear device can be integrated to prevent sneak leakage current in a cross point array 43

44 LUT Performance Comparison K. Kato et al., IEEE Electron Device Letters, vol. 37, no. 12, pp , 2016 Area (μm 2 ) CMOS (F = 45nm) CMOS+NEMS (F = 20nm) 10 1 Readout delay (ns) Program delay (ns) Readout energy (fj) Program energy (fj) More compact, faster, and energy efficient than CMOS! 44

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