High Mobility Channel Impact On Device Performance High mobility materials (advantages) High Mobility - Low Leakage

Transcription

1 High Mobility Channel Impact On Device Performance High mobility materials (advantages) High mobility materials (disadvantages) energy Low m* transport Increasing µ brings us closer to the ballistic limit E F RI + $ I sat = qn Source S v inj " 1# R ' & ) % 1+ R( I + High ν inj Low R E F -qv D ε(x) position CB VB* VB 27 Low E g High κ s Low m* High Leakage Currents Worse SCE High Tunneling Leakage Low Density Of States Leakage currents may hinder scalability High Mobility - Low Leakage Device performance : I off vs I on A: Low mobility low leakage Electrostatics: κ s, geometry B: High mobility low leakage C: High mobility high leakage Performance is determined by a combination of transport and electrostatics 28 1

2 Picking the Right High-µ Material Effective mass Vs Bandgap Dielectric constant Vs Bandgap Typical scenario: - Low Effective Mass - Small Bandgap - High Dielectric Constant 29 Problems with High-µ Materials High mobility materials have: Have low density of states in the Γ-valley, reducing Q inversion and hence drive current. Due to quantization caused by thin body and high surface E-field charge spills into L and X valleys where mobility is low Have small direct band gap which gives rise to high BTBT leakage (except GaAs). Have a high dielectric constant and hence are more prone to short-channel effects. We have investigated and benchmarked Double-Gate n-mosfets with different channel materials (GaAs, InAs, InSb, Ge, Si) taking into account band structure, quantum effects, BTBT and short-channel effects. Pethe, Krishnamohan, Kim, Oh, Wong, Nishi and S, IEDM

3 Performance vs Scaling I ON (ma/µm) Ge and III-V materials have higher I DS than Si. Band to band tunneling leakage (I BTBT ) scales with band gap. Pethe, Krishnamohan, Kim, Oh, Wong, Nishi and S, IEDM Benchmarking Novel Channel Materials for NMOS Performance Tradeoffs between performance (CV/I) and static power dissipation (I for a DG-NMOS with T ox = 1nm and different channel materials (I OFF ) Gate Delay (CV/I) (ps) Si V DD 0.3V-1V Ge GaAs InAs 0 1E-13 1E-10 1E-7 1E-4 I BTBT (A/µm) 32 InSb Need innovative structure to combine advantages of a high-µ material for transport and a large bandgap material for leakage 3

4 Heterostructure DG MOSFET Device geometry Si Ge Si/Ge/Si Heterostructure: What does it buy us? Transport through the high mobility (narrow Eg) Leak through the wide Eg (low mobility) T. Krishnamohan et al, IEEE Transactions ED special issue on Non-classical Si CMOS devices and technologies: Extending the roadmap (Invited) 33 Ge/Si Heterostructure PMOS Materials: Strained Si, Relaxed-Ge or Strained-(Si)Ge? Device structures: Monomaterial or Heterostructures? Ge Si/Ge/Si H-FET Power-Performance L G =16nm, T S = 5nm, Vdd=0.7V Transport through high mobility (narrow Eg) Leak through the wide Eg Terminology (x,y) for channel material x = Ge content in the channel material and y = Ge content in an imaginary relaxed (r) substrate to which the channel is strained (s) H-FET: heterostructure FET Krishnamohan, Kim, Jungemann, Nishi and S, VLSI Symp. June Switching Frequency (THz) Control (0,0) r-si (0.6,0) s-sige H-FET (0,0.6) s-si (0.6,0) s-sige (1,0) s-ge H-FET (1,0) s-ge (1,1) r-ge I OFF, min (nm) (0,1) s-si 4

5 Heteroepitaxial Growth of Ge on Si Relaxed-Ge on Si, T Ge >> T crit Strained-Ge on Si T Ge > T crit Strained-Ge on Si T Ge < T crit 35 Strained-Ge Bulk PMOS on Relaxed Si Device structure Band diagram Measured Mobility and BTBT Krishnamohan, Krivokapic, Uchida, Nishi and S, IEEE Trans. Electron Dev., May High mobility due to: Strain in Ge Reduced scattering due to reduced E-field in Ge channel being away from the interface Low S/D leakage due to: Reduced E-field in Ge E g due to confinement of Ge film 5

6 Strained-Ge Heterostructure SOI MOSFET Band Diagram Device structure TEM Mobility I d -V g 4X improvement over Si Krishnamohan, Krivokapic, Uchida, Nishi and S, IEEE Trans. Elec Dev., May Center Channel Double Gate Heterostructure FET PMOS Elwomis: Full-Band Monte-Carlo Simulations Depletion-Mode DG Depletion regions OFF S G G D Hole ψ ON Channel in the center G S D G Electron ψ NMOS Higher drive current Carriers in the center of an un-doped strained-si or Si x Ge 1-x channel high mobility also due to zero E field, strain, low surface scattering 38 Higher cut-off frequency Krishnamohan, Kim, Nguyen, Jungemann, Nishi and S, IEEE Trans. Elec Dev., May

7 Effect of Extrinsic Resistance on Double Gate FETs R s R d I d = K (VK g V th I d R s ) α Ultrathin body higher series resistance More severe effect in Double-Gate FET Twice I d flows through same Rs higher series drop Degradation in I ON Need to reduce parasitic resistance Shenoy and S, IEEE Trans. Nanotechnology, Dec Effect of Extrinsic Resistance on Double Gate MOSFETs SCE Series Resistance 1.E+21 1.E+20 GATE Net Doping (cm-3) 1.E+19 1.E+18 1.E+17 1.E+16 1.E+15 1.E+14 1.E Doping gradient 5nm/dec 4nm/dec 3nm/dec 2nm/dec 1nm/dec 0.5nm/dec x (nm) Extrinsic resistance reduces gate overdrive performance limiter in ballistic FETs Doping profile too gradual: dopants spill into channel worse SCE Doping profile too abrupt: large series resistance in extension tip Extrinsic (S/D) resistance may limit performance in future ultrathin body DGFETs Shenoy and S, IEEE Trans. Nanotechnology, Dec

8 Two kinds of transistors Junction S/D MOSFET Schottky S/D MOSFET Possible advantages of Schottky S/D MOSFET Better utilization of the metal/semiconductor interface Possible option to overcome the higher parasitic resistance Modulation of the source barrier by the gate High V g barrier thin tunneling current I ON Low V g barrier thick tunneling current I OFF Better immunity from short channel effects Possible Disadvantage I ON reduction due to the Schottky barrier 41 Schottky Barrier MOSFETs on Ultrathin SOI Simulations of single-gated Schottky barrier MOSFETs on ultrathin silicon on insulator. Tsi=54 nm device at V ds =0.8 V. The inset shows the conduction band in the channel for different Vg. Knoch et al., Appl. Phys. Lett., 14 October

9 PN Junction vs. Schottky S/D Si DGFET Simulations PN Junction S/D I ON vs. I OFF Schottky S/D Low barrier (~0) height metal/semiconductor contacts required to achieve high I ON and low I OFF Fermi level pinning makes it difficult to achieve R. Shenoy, PhD Thesis, Example of Schottky Barrier MOSFET Schottky Barrier L g ~20 nm FETs with Complementary Silicides PtSi PMOS, ErSi NMOS Silicide Si BOX Lg + Spacers =27nm Source ErSi 2 Tilted W=25nm Gate N +poly, ErSi 2 Lg Tox Vg-Vt Ion Swing Ion/Ioff Vt PtSi PMOS 20 nm 4 nm 1.2 V 270 ua/um 100 mv/dec 5E5-0.7 V ErSi NMOS 15 nm 4 nm 1.2 V 190 ua/um 150 mv/dec 1E4-0.1 V Metal S/D reduce extrinsic resistance Need ultrathin channel, double gate Need low barrier technology to ensure high I on 44 I d (A/µm) 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 J. Boker et al.- UC Berkeley PMOS T ox = 4nm L g = 20nm V sd from 0.2V to 1.4V in steps of 0.4V NMOS T ox = 4nm L g = 15nm V g (V) 9

10 60 nm In 0.7 Ga 0.3 As HEMTs * J. A. del Alamo, MIT Gate SiN X Source Source InGaAs cap InAlAs insulator InGaAs channel Drain Drain InP InAlAs buffer Features: L g = ~60 nm gate by e-beam lithography L g = ~ 60 nm nm InGaAs HEMTs J. A. del Alamo, MIT At 0.5 V: V T = V, S= 70 mv/dec, DIBL= 44 mv/v, I on /I off = 2.7x

11 MIS Capacitor Stack on GaAs Fitzgerald (MIT) HFCV shows low hysteresis, little frequency dispersion Jg-V curve shows low leakage κ of dielectric stack estimated to be ~10.6 Al 5 nm 80 Å AlN 27Å GaAsN P-GaAs 47 C (F) 4.0E E E E E E E E khz Rev 100 khz Fwd 1 MHz Rev 1 MHz Fwd 0.0E V 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E V Jg (A/cm 2 ) accumulation inversion Scaling Subthreshold Slope I D V T 60 mv/decade S < 60 mv/decade V G [ NTRS/ITRS data, Plummer et al, Proc. IEEE (Mar 2001) ] V DD is scaled for low power,delay V T must scale to maintain I D In MOSFET subthreshold slope is limited to kt/q (60mV/dec at 300K) I D leakage increases Static power increases Dynamic-Logic circuits/ latches can lose value Can we beat the 60mV/dec limit? 48 11

12 Impact Ionization region V S < 0 P + V G > 0 Poly Inversion layer (n) Buried-Oxide N + I-MOS I-MOS is a gated p-i-n diode and works by channel-length modulation (and hence breakdown modulation). OFF state: Low V G : Longer effective channel length: Lower E-fields: No breakdown. Experimental Results ON state: High V G : Inversion layer: Higher E-fields: Breakdown occurs. Device Structure Offset ~ 0.5 µm GATE Gate-Ox. ~ 20 nm 2 µm N µm P + BURIED OXIDE SILICON (K. Gopalkrishnan & J. Plummer, Stanford ) 49 Beating kt/q in MOS Structures To achieve better than kt/q operation in an insulated gate structure requires: Carrier injection method with no first order temperature dependence essentially either impact ionization or tunneling OR Internal gain mechanism I-MOS utilizes both approaches: impact ionization and internal gain (avalanche multiplication) V S < 0 P + V G < 0 Poly Inversion layer (p) Buried-Oxide BTBT region N + BTBT current: A and B are constants, E is electric field in the tunneling direction, and E G is bandgap BTBT has exponential dependence on electric field therefore the possibility for steeper than kt/q operation exists Silicon BTBT transistors have consistently shown worse than kt/q subthreshold characteristics Practical BTBT transistor will require use of new materials with improved tunneling coefficients

13 Seemingly Useful Devices Limited Current Drive Cryogenic operation Limited Fan-Out Critical dimension control Challenging fabrication and process integration B + = Spintronics Need high spin injection and long spin coherence time ~ 2 nm Limited thermal stability New architectures needed 51 Carbon Nanotubes Controlled growth Organic Insulator / Semiconductor Monolayer J. Collet et al., APL 76, 1339 (2000)

14 Organic Semiconductors B. Crone, A. Dodabalapur et al. Nature 403, 521 (2000) All-Printed Polymer Circuit Z. Bao / Stanford LSI (864 Transistors) Applications identification tags low-end data storage smart cards emissive displays electronic paper distributed computing toys, clothes,... low-cost, lightweight, rugged, flexible electronics No competition to Si, Going where Si can t follow!! 53 Self-Assembled Monolayer Molecular FET Molecular FETs Molecular Switchs Molecular Length Defines Channel 54 14

15 Molecular Electronics Interfaced with Silicon Technology Demultiplexers Order (n) wires (large pitch) To gain element or logic circuit MS Molecular Switch multiplexer Crosspoint molecular electronic memory: 2 n bits (20 30 nm pitch) Molecular mechanical complexes as solid-state switch elements Non-traditional patterning techniques to achieve a memory bit (cross-point) density of >10 11 /cm 2. Non-linear, voltage response of molecular switches to latch (amplify) and clock signals by coupling a large molecular circuit with very few CMOS-type amplifiers. 55 Source: Nicholas Melosh and J. Heath Ballistic Nanotube Transistors Growth MOS Transistor Gate Nanotube D 10 nm SiO 2 HfO 2 S C n H m Fe C n H m Catalyst Support Dai (Stanford) McIntyre (Stanford) Gordon (Harvard) Lundstrom (Purdue) I DS (µa) -IDS (A) p++ Si L ~ 50 nm V DS = -0.1,-0.2,-0.3 V V G (V) 56 I DS (µa) IDS (µ A) V -0.1 V -0.4 V -0.7 V -1.0 V -1.3 V L ~ 50 nm V DS (V) Key Challenge: Low thermal budget controlled growth 15

16 High Performance CNT N-MOSFETs D 10-6 Ids (A) 10-8 S~70 mv/dec V ds =0.5 V S~80 mv/dec G S CNT K + K G V gs (V) d~1.6 nm 1 Pd HfO 2 n + i n nm SiO 2 p+ Si Pd 10 Ids (µ A) p-fet n-fet Moderate S/D doping Dai/Gordon/Guo Groups V ds (V) Ambipolar Schottky S/D Nanotube FETs 58 16

17 Theoretical Limits to Scaling Thermodynamic limit: E b k B.T.ln2 Quantum mechanics x. p h x min (Integration density) E. t h τ (witiching speed) E min x min E b Ultimate limit: x min ~ 1.5 nm transistors/cm 3 Switching speed t min ~ 0.04 ps 25 Tbits/sec Switching energy E bit = 17 mev Power = 55 nw/bit For densely packed, 100% duty cycle devices Total power density = W/cm 2 With duty cycle ~1 %, Active transistors ~1 % Total power density = 370 W/cm 2 P = n max E bit t min Source: George Bourianoff, Intel 59 Charge a Spin Based Switch E b Jim Harris et al. (Stanford) Spin ΔE b (e-) ~1.7x10-2 ev ΔE(spin) ~8.6x10-8 ev B + = E b a w w ΔE(spin) << ΔE(e-) After Mark Bohr, (Intel) Single spin state can be detected by measuring if there is any tunneling current

18 New materials Ge SiGe Semiconductors Ta 2 O 5 HfO 2 ZrO 2 High-k dielectrics Al SiO 2 Si Al SiO 2 Si Si 3 N 4 Poly Si PtSi 2 WSi 2 CoSi 2 TiSi 2 MoSi 2 TaSi 2 Silicides Air HSQ Polymer TiN TaN Cu W Low-k dielectrics Metals ZrSi x O y RuO 2 Pt IrO 2 Y1 PZT BST Electrode materials Ferroelectrics (S. Sze, Based on invited talk at Stanford Univ., Aug. 1999) Moore s Law increasingly relies on material innovations 61 Conclusion: Technology Progression Bulk CMOS Cu interconnect Low-k ILD FD SOI CMOS (After P. Wong) Wafer bonding Crystallization Nanowires Strained Si Si (tensile) Si 0.8 Ge 0.2 Si 1-x Ge x 3D ICs Optical interconnect Nanotechnology Si High k gate dielectric Metal gate Ge on Si hetroepitaxy Ge on Insulator Double-Gate CMOS Source Gate Drain Ge/Si Heterostrcture Feature Size (Time) 100 nm 2 nm 62 Detectors, lasers, modulators, waveguides Nanowire Nanotube Selfassembly Interconnects and contacts for nanodevices Single e transistor Molecular device B + = Spin device 18