Microsystems Technology Laboratories, MIT. Teledyne Scientific Company (TSC)

Transcription

1 Extraction of Virtual-Source Injection Velocity in sub-100 nm III-V HFETs 1,2) D.-H. Kim, 1) J. A. del Alamo, 1) D. A. Antoniadis and 2) B. Brar 1) Microsystems Technology Laboratories, MIT 2) Teledyne Scientific Company (TSC) Sponsors: Intel, FCRP-MSD, TSC Discussions with R. Chau & M. Radosavljevic IEDM December-9 th,

2 Contents 1. Introduction - Virtual Source Injection Velocity (v x0 ) 2. Methodology to extract v x0 3. Virtual Source FET Model 4. Conclusions 2

3 Virtual Source Injection Velocity V G V S V D I 1-r D r I D R S Q i_x0 R D v E C E C v x0 k B T l Virtual Source 0 x L x o I D = Q i_x0 v in fully Ballistic case = Q i_x0 v x0 with scattering v x0 : FOM to determine I D and gate delay ( ). Goal of this work: measure v x0 in III-V channel Ref: Prof. Lundstrom, Purdue Univ. 3

4 v x0 - How to extract? Approaches: - 1) Inversion charge is linear with V GS for V GS > V T. g GS GS T I D = Q i_x0 v x0 = C gi ( V GSi V T ) v x0 I D v x0 = Cgi ( V GSi V T ) Limitation: Linearity assumption underestimates Q i_x0. - 2) Transconductace method. (I D ) g mi (V GSi ) = g mi = C gi v x0 v x0 = Cgi Limitation: Assumes v x0 constant with V GS. x0 GS Ref: 1) D. A. Antoniadis (IBM Journal-06), 2) G. Dewey (EDL-08) 4

5 Contents 1. Introduction - Virtual Source Injection Velocity (v x0 ) 2. Methodology to extract v x0 3. Virtual Source FET Model 4. Conclusions 5

6 v x0 Proposed Methodology V V G V I D = Q i_x0 v x0 v x0 = I D / Q i _ x0 I D -I D : Measured Drain Current E C R S Q i_x0 v x0 R D -Q i_x0 : Sheet Charge Density Q i_x0 = C gi d(v GS,i ) where C = 10 mv -R s and R d correction i = I D (R S +R D ) L 0 x x o V GSi = V GS I D R S - V T roll-off off correction in Q i_x0 - DIBL correction in Q i_x0 6

7 Device Technology: III-V HEMT Gate PR Gate Metal Ti/Pt/Au S Oxide t ins t ch D Cap Etch stopper Barrier Channel Buffer Barrier = In 0.52 Al 0.48 As ( 4 or 10 nm ) 4nmIn Al As Channel = In 0.53 Ga 0.47 As ( 2 nm ) 2 nm In 0.53 Ga 0.47 As Channel = In 0.7 Ga 0.3 As ( 8 nm ) Core or InAs ( 5 nm ) 5 nm InAs, 8 nm In 0.7 Ga 0.3 As Channel = In 0.53 Ga 0.47 As ( 3 nm ) 3nmIn 0.53 Ga 0.47 As Buffer = In 0.52 Al 0.48 As (~400 nm) t ch = 10 nm ch In 0.52 Al 0.48 As Substrate = InP (~300 nm) -L g : 200 nm ~ 30 nm, t ins = ~ 4 nm - Channel: In 0.53 Ga 0.47 As, In 0.7 Ga 0.3 As, InAs Refs: Kim et al., iedm-08, iprm-09 7

8 C gi - How to extract in small L g device? C gi intrinsic gate capacitance per unit area [ff/ m 2 ] (from S-parameters at linear region, = 10 mv) C g C gi C C g = C gi x L g + 2C gext_inner + 2C gext_outer f(v GSi - V T T) C g C g (OFF) = C gi x L g + 2C gext_inner

9 Q i_x0 - How to extract? Q i_x0 = C gi d(v GS,i ), where C = 10 mv 12 L g = 30 nm x C gi 3 C F/ m 2 gi [ff ] 4 Q i_xo 2 1 Qi Xo = 10 mv V GSi [V] 0 9

10 v x0 = I D / Q i_x0 L g = 30 nm In 0.7 Ga 0.3 As HEMTs with t ins = 4 nm =005V 0.05 = 0.2 V = 0.35 V = 0.5 V 4 x = 0.05 V = 0.2 V = 0.35 V = 0.5 V [ma/ m] 0.4 Q i_x0 2 I D DIBL correction V GSi [V] V GSi [V] v x0 can be extracted t at any bias condition. As V GSi, less DIBL correction due to i. 10

11 Bias Dependent v x0-30 nm InGaAs HFET 4 v [10 7 x0 cm/s] = 0.05 V = 0.2 V =05V 0.5 = 0.35 V V GSi [V] v x0 V GSi v x0 Extracted v x0 is NOT constant with V GSi. x0 (I D ) (Q i_x0 ) GSi (v x0 ) (V GSi ) = v x0 + Q i_x0 (V GSi ) (V GSi ) 11

12 v x0 for different L g 4 x 107 L g 3 v x0 [cm m/s] 2 L g = 30 nm L g = 40 nm 1 L g = 60 nm L g = 80 nm = 0.5 V L g = 130 nm As L g, g, V GS gs - V V T T [V] v x0 improves and then saturates at L g ~ 40 nm. 12

13 v x0 vs. L g for different channels 4 (InAs) n ~ 13,000 cm 2 /V-s 3 cm/s] v x0 [10 7 n ~ 11,000 cm 2 /V-s 2 (In Ga As) n ~ 9,500 cm 2 /V-s (In 0.53 Ga 0.47 As) 1 *Strain-Si *Si nfets = 0.5 V (V 0 DS = 1.1 ~ 1.3 V) L g [nm] - III-Vs shows 2X higher v x0 than Si, even at = 0.5 V. - As InAs composition, v x0 due to m e*. Ref: * Khakifirooz et al., TED, 1674 (08) 13

14 v x0 vs. DIBL 4 3 InAs InAs HFETs HFETs [5] In 0.7 Ga 0.3 As HFETs [6] In 0.53 Ga 0.47 As HFETs m/s] x0 [107 cm v x and 45-nm node devices with V dd = 1.1 to 1.3 V [9] [1] 1 7X Strained nfets with V V[4] 0 dd = 0.5 [2] DIBL [mv/v] 7X higher v DIBL = 100 mv/v, V dd = 0.5 V Ref: 1) Khakifirooz et al., TED, 1674 (08), 2) G. Dewey (EDL-08) 14

15 Contents 1. Introduction - Virtual Source Injection Velocity (v x0 ) 2. Methodology to extract v x0 3. Virtual Source FET Model 4. Conclusions 15

16 The Virtual Source FET Model A Simple, Physical Universal-Short Channel FET Semi-empirical Model (based on Si MOSFET model [1]) I D = Q i_x0 v x0-m F sat VS I D = Q i_x0 v x0 F sat : Semiempirical saturation function V G V D Known Device Parameters C inv ox : Q ix0 = C inv ox f(s, V GSi,i, V t* ) : V * t = V t0 - i DIBL, From I D (i )vs vs. V GSi S : Subthreshold swing: From log(i D ) vs. V GSi : Threshold Voltage at V D ~0 (from I off and DIBL) V t0 R S,D : V GSi =V GS -I D R S ; i = -2I D (R S +R D ) E C R s v x0 Q i_x0 0x L eff x o Fitted Physical Parameters V x0-m : Maximum carrier velocity at virtual source (x=x 0 ) eff : Effective mobility, assumed constant [1] Khakifirooz et al., TED, 1674 (08)

17 Comparison - 30 nm In 0.7 Ga 0.3 As HFET Fitting parameters: eff, v x0m Measured V GS =05V 0.5 Modeled V ds =0.5 V V ds =0.5 V 0.35 V 0.2 V 0.05 V 0.05 V Excellent agreement: - from linear to saturation, and weak to strong inversion. - eff = 1500 cm 2 /Vs, v x0m = cm/s 17

18 Comparison: v x0 = v x0m F sat L g = 30 nm In 0.7 Ga 0.3 As Extracted Modeled =0.5 V 0.35 V 0.20 V 0.05 V Excellent agreement with extracted values of v x0. 18

19 v x0 NEGF simulation 30 nm In 0.7 Ga 0.3 As HEMTs v x0 = 3.1 x 10 7 cm/s: close to experimental value. Acknowledgement : Y. Yang and M. S. Lundstrom, Purdue Univ. 19

20 Conclusions Methodology to extract injection velocity (v x0 ) at virtual source. Sub-100 nm InGaAs HEMTs - v x0 > cm/s at = V for In Ga As - Peak v xo = cm/s for InAs sub-channel -7 higher than Si at DIBL = 100 mv/v and = 0.5 V Virtual Source FET model - Excellent description of I-V characteristics of III-V HEMTs with physically meaningful values of v x0. 20