THE CARRIER velocity in a MOSFET channel near the

Transcription

1 994 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012 On the Interpretation of Ballistic Injection Velocity in Deeply Scaled MOSFETs Yang Liu, Mathieu Luisier, Amlan Majumdar, Dimitri A. Antoniadis, Fellow, IEEE, and Mark S. Lundstrom, Fellow, IEEE Abstract The ballistic injection velocity is examined in state-of-the-art Si extremely thin SOI MOSFETs using ballistic quantum simulations and a virtual source (VS) compact model. The results indicate that the device performs at around 50% 60% of its ballistic limit and that the ballistic injection velocity at the top of the potential barrier (ToB), as obtained by numerical simulation, can be significantly lower than its counterpart extracted at the VS. This occurs because, at high drain bias, the ToB moves under the influence of gate bias toward the source contact, where additional mobile charge resides that are not directly induced by the gate contact but by the source contact. This effect becomes increasingly important as channel length shrinks and is affected by several factors, including the details of the source design. The accurate estimation of a physically meaning injection velocity under ballistic limit could be therefore very difficult in very short channel MOSFETs. Index Terms CMOS scaling, injection velocity, virtual source (VS). I. INTRODUCTION THE CARRIER velocity in a MOSFET channel near the source is a key device performance metric [1] [5]. Because the so-called injection velocity continues to play an important role in technology development, it is important to clearly understand its physical significance. In the literature, the injection velocity has been identified either as the average carrier velocity at the top of the energy barrier (ToB) between the source and the channel [2], [6] or as the velocity at the socalled virtual source (VS) [7], [8]. While the ToB and VS concepts are very often used to describe the same quantity, it will be shown in this paper that they refer to two different locations along the transistor channel characterized by carrier Manuscript received October 4, 2011; revised December 5, 2011; accepted January 5, Date of publication February 10, 2012; date of current version March 23, This work was supported in part by the Focus Center Research Program on Materials, Structures and Devices (FCRP-MSD). The review of this paper was arranged by Editor D. Esseni. Y. Liu is with the IBM Research Division, Hopewell Junction, NY USA ( liuyang@us.ibm.com). M. Luisier is with the Integrated System Laboratory, ETH Zürich, 8092 Zürich, Switzerland ( mluisier@iis.ee.ethz.ch). A. Majumdar is with the IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY USA ( amajumd@us.ibm.com) D. A. Antoniadis is with the Microsystems Technology Laboratory, Massachusetts Institute of Technology, Cambridge, MA USA ( daa@mtl.mit.edu). M. S. Lundstrom is with the Network for Computational Nanotechnology and the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN USA ( lundstro@purdue.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED velocities that can be quite different under the ballistic limit. This distinction will be increasingly important as channel lengths continue to shrink. In spite of its technical significance as a key device metric, the injection velocity cannot be obtained via direct measurement. A common way to extract the injection velocity consists of estimating the charge density at the ON-state using the measured C V data and taking into account the effect of the series resistance and threshold voltage shift due to shortchannel effects [7] [10]. A compact VS model based on this method has been developed to accurately fit a wide range of I V characteristics with only a few fitting parameters [10]. When this model is applied to III V HEMTs, the VS injection velocity extracted from their I V and C V data agrees very well with the velocity at the top of the barrier from 2-D simulation [11] [13]. Some concerns arise, however, in short-channel Si transistors [5], where the velocity at the VS becomes very close to its physical limit, the band-structure-limited ballistic velocity at the top of the barrier. A rigorous simulation approach is therefore critical to help interpret the velocities extracted from experimental data and understand the origin of the difference (if any) of ballistic injection velocities obtained from numerical simulations and from a VS analysis. This paper therefore uses numerical simulation to compare the ballistic injection velocity at the top of the barrier to the value extracted from the I V and C V characteristics (which we will denote as the velocity at the VS of the device). We will show that these two velocities can be different and depend on source design as gate lengths scale down and that the VS and ToB velocity discrepancy under ballistic limit comes from the difficulty in separating the source and the channel in deeply scaled MOSFETs. This effect will become increasingly important as devices are scaled to 10 nm and below. We will also explain why this discrepancy is less pronounced in III V HEMTs than in Si MOSFETs. It should be noted that the VS model produces very sensible results when it is used to analyze measured data. The difference of the injection velocity observed between the VS model and simulation may be magnified under the ballistic conditions examined here in the Si MOSFETs, but it is an effect that we should be aware of. This paper is organized as follows: In Section II, we describe the device structure of an extremely thin SOI (ETSOI) MOSFET fabricated at IBM [14], [15]. The performance of the ETSOI FET is then analyzed with the VS compact model in Section III, from which the VS velocity will be extracted. Next, in Section IV, the ETSOI s ballistic performance is examined with nanomos, a 2-D simulation tool [18]. In Section V, /$ IEEE

2 LIU et al.: ON THE INTERPRETATION OF BALLISTIC INJECTION VELOCITY IN MOSFETs Ω μm) [14] is included in nanomos in a postprocessing step once the intrinsic I V is computed. The conventional dr/dl method was used for extracting R SD with V DS = 50 mv and an external gate overdrive of 0.7-V nfets [17], [18]. III. VS COMPACT MODEL ANALYSIS The performance of the ETSOI FET is first examined by the VS model. In a nanoscale MOSFET, the inversion layer carriers at the beginning of the channel near the source (the VS) are thermally injected into the channel and determine the saturation drain current according to [4], [8] [10] I Dsat /W = υ x0 Q i (x 0 ) (1) Fig. 1. ETSOI device structure considered in this paper. The simulation domain is indicated by the dashed square, for which a 2-D quantum simulator nanomos has been developed to examine the ballistic injection velocity. where x 0 is the position of the VS, and v x0 and Q i (x 0 ) are the VS velocity and charge density per unit area, respectively. The VS velocity is extracted from (1) with charge density Q i (x 0 ) computed by [7], [8] Q i (x 0 )= V GS +ΔV T I on R S 0 C gsddv g (2) Fig. 2. S/D doping concentration profile and 1-nm overlap (L ov) distance in the ETSOI FETs. The effective channel length is L EFF = L G 2nm. the discrepancy between the two models is analyzed before concluding in Section VI. II. ETSOI DEVICE STRUCTURE The device used in this paper is an ETSOI MOSFET. ETSOI FETs are attractive candidates for high-performance logic applications for the 22-nm technology node and beyond. They also represent good test devices to compare the injection velocity extracted from I V /C V data to the value extracted from simulations. The device structure is taken from [14] and [15] with gate length L G = 40 nm, as shown in Fig. 1. The device includes an intrinsic SOI body with thickness T SOI = 8.6 nm, a 145-nm-thick buried oxide (BOX), and a 1.1-nmthick SiON gate oxide (ε = 4.8). The structure is depicted in Fig. 1. The overlap distance between the gate and the source/drain (S/D) extensions L OV (where S/D doping drops to /cm 3 ) is 1 nm for the nfets [16]. Taking this point as the beginning of the effective channel, we have L EFF = L G 2 nm. Thus, L EFF represents the effective channel length. This estimate of L EFF was shown to be very accurate via the universality of short-channel effects in [14]. As shown in Fig. 2, the doping profile beyond the doping level of cm 3 is Gaussian-like with a constant slope of 0.7 nm/dec. The extracted total series resistance (R SD = R S + R D = where C gsd is the measured gate capacitance at V DS = 0V. The upper limit of the integral in (2) is corrected to account for series resistances and for threshold voltage shift ΔV T due to short-channel effects. It is clear then that the VS is defined as the position in the channel at which the charge density in strong inversion is given by (2) or by C oxinv (V GS V T ) in a more simplistic way. A VS compact model [10] based on the above concept has been developed for analysis of real devices with only nine parameters, among which the following four parameters are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions C G ; 2) subthreshold swing SS; 3) drain-induced barrier lowering DIBL; and 4) effective channel length L EFF. The fitted physical parameters are low-field mobility μ EFF, parasitic source-to-drain resistance R SD, and VS injection velocity v x0. The VS compact model has been very useful in extracting very reasonable device parameters by fitting the real measured device data [1], [19]. We next examine the ETSOI device performance with the VS compact model. Fig. 3 shows the I V curves from the same set of measured ETSOI data and the VS compact model fitting. C G = 2.0 μf/cm 2 is used for strong inversion gate capacitance, SS = 72 mv/dec, and DIBL = 45 mv/v. Other fitted parameters are R SD = 250 Ω μm, effective mobility μ EFF = 300 cm 2 /V s, and VS velocity v x0 = cm/s. The use of bias-independent R SD and μ EFF for VS model fits is justified for theoretical and experimental reasons, as discussed in [20]. At V GS = 0.6 V and V DS = 1.0 V, the VS charge density N(x 0 ) is about cm 2. The results show that the VS model fits the measured data with very sensible parameters.

3 996 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012 Fig. 3. Comparison of the (lines) VS model fit and (symbols) measured data for the I d V GS characteristics at V DS = 0.05 and 1.0 V and for the I d V DS characteristics. The VS analysis fits the measured data from a 40-nm gate-length ETSOI nfet with very sensible parameters. Fig. 4. Comparison between simulated and measured C V characteristics. The measured C V was obtained from long-channel FETs with gate length L G = 1and2μm. The simulated results differ from the measured data by 5% at the maximum gate capacitance before gate leakage becomes significant and reduces the gate capacitance. The little drop in the simulated C V is due to polygate depletion. IV. BALLISTIC PERFORMANCE ANALYSIS The ballistic performance of the ETSOI FET is now examined with nanomos [21], which self-consistently simulates transport in 2-D devices by coupling a mode-space Nonequilibrium Green s Function quantum transport model using effective masses with a 2-D Poisson solver. The nanomos program has evolved to treat a wide range of device structures and materials, with the capability of modeling both ballistic and dissipative transport in nanoscale transistors [22], [23]. Recently, nanomos has been adapted to a III V HEMT structure designed for logic applications, for which good agreement between simulations and the measured data can be obtained. This indicates that the simulator captures the physics of realistic devices very well [12], [13], [24] [26]. The intrinsic simulation domain in nanomos is indicated by the dashed square in Fig. 1. The capacitance of the polygate SOI structure is first simulated with nanomos by setting the sourceto-drain voltage to 0 and ramping the gate-to-source voltage from small to large values. The simulation results are compared with the C V data measured at 1 MHz. As shown in Fig. 4, the simulated C V characteristics agree well with the data before the measured C V starts to drop due to the large gate leakage current flowing through the thin SiON gate oxide. This shows that our simulated structure is properly calibrated to handle the effects of polygate depletion. The ballistic I V characteristics of the ETSOI FETs are next compared with the experimental data in Fig. 5. Note that the simulation results include the measured series resistance (R S = R D = R SD /2 = 135 Ω μm). The ballistic simulation shows that the measured ON-current of the 40-nm ETSOI FETs (V GS = 0.6 V and V DS = 1.0 V) is about 57% of the simulated one, indicating that the device operates at about 57% of its ballistic limit, or in other words, the ballistic ratio of the ETSOI FETs in the ON-state is about 57%. The ballistic injection velocity can be extracted from the nanomos simulations. It is also often identified as the average velocity at the ToB [2], [3], [27], i.e., I Dsat /W = qυ ToB n ToB. (3) The top of the barrier injection velocity υ ToB is related to its ballistic limit υ T through the backscattering coefficient r, i.e., [2], [3] ( ) 1 r υ ToB = υ T (4) 1 + r where υ T 2kB T I 1/2 (η FS ) πm I 0 (η FS ) is the ballistic thermal injection velocity at the top of the barrier assuming that a single parabolic subband is occupied [27], [28]. As the backscattering coefficient r decreases with shrinking gate length, υ ToB is expected to approach its ballistic limit υ T. Here, the ballistic injection velocity and the charge density at the ToB are obtained from the nanomos simulation as υ T = cm/s and n ToB = cm 2, which is shown in Fig. 6, where the carrier velocity, the electron density (obtained by integrating the electron charge distribution across (5)

4 LIU et al.: ON THE INTERPRETATION OF BALLISTIC INJECTION VELOCITY IN MOSFETs 997 Fig. 5. Comparison of (lines) ballistic simulation (R SD = 270 Ω μm included) and (symbols) measured data for I d V GS characteristics at V DS = 0.05 and 1.0 V and for I d V DS characteristics. The ballistic and measured ON-currents indicate that the 40-nm gate-length ETSOI nfet operates at about 57% of its ballistic limit in the ON-state. Fig. 6. Electron density, average velocity, and conduction band profile along the device at ON-state (V GS = 0.6 V,V DS = 1.0 V). n ToB and υ T are the mobile electron density and ballistic injection velocity at the ToB, and N i (x 0) and υ x0 denote the electron density and injection velocity at the VS under ballistic limit, respectively. υ x0 is larger than υ T as the ToB and the VS refer to different points in the device. the depth of the channel), and the conduction band profile along the channel are plotted. The corresponding intrinsic biases are V GSi = 0.35 V and V DSi = 0.50 V (I on = 1730 μa/μm). The key result here is that the charge density at the ToB extracted from nanomos simulations (n ToB = cm 2 ) exceeds by more than 70% N(x 0 ) from the VS model fitted to the measured data ( cm 2 ), as shown in Section III, although the intrinsic gate bias for the ballistic limit simulation is smaller (same extrinsic gate bias but higher current at ballistic limit). As an initial guess, one would expect n ToB to be smaller than N(x 0 ) due to the smaller internal gate voltage. As a consequence of the surprisingly high n ToB,the ballistic injection velocity at the ToB is almost the same as the velocity extracted from the measured data with the VS model ( cm/s versus cm/s). In fact, if we use (2) with the simulated C V from Fig. 4 and the same series resistance and ballistic ON-current, the charge density at the VS of the ballistic-limit-simulated FET becomes N i (x 0)= cm 2, leading to a ballistic injection velocity at the VS equal to v x0 = I on /qn i (x 0)= cm/s, as shown in Fig. 6. The surprisingly high ToB inversion charge calculated in nanomos compared with the extracted N(x 0 ) of the VS model is therefore the cause of the velocity difference. The origin of this extra charge and the influencing factors is the subject of the rest of this paper. V. D ISCUSSION The significantly higher charge density at the ToB in the nanomos simulation compared with the value extracted at the VS from the I V /C V data based on (2) or the VS model leads to a two-times lower ToB ballistic injection velocity compared with the VS one. This is a substantial difference that needs to be understood. In the VS model, the charge in the channel is always balanced by the gate charge. The capacitance used to estimate the charge density at the VS under high V DS condition is the gate capacitance measured at V DS = 0. Fig. 7 examines this assumption in nanomos simulation by comparing the charge density at the top of the barrier in the channel (n ToB ) and the charge density at the gate electrode at the position directly above the top of the barrier (n gate ) under low and high V DS. The gate charge density above the top of the channel barrier

5 998 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012 Fig. 7. Charge density at the gate n gate and at the ToB n ToB in the channel under high and low V DS. The higher channel charge at the ToB under high V DS indicates that a large amount of the charge at the ToB is not entirely balanced by the gate charge but by the charge in the source/channel junction. Fig. 8. Electron density and conduction band profile along the ETSOI FET under high and low V DS,andV GS = 0.35 V. The charge density at the ToB under high V DS significantly increases as the ToB moves into the source/channel junction, where a significant amount of charge is already present before the formation of any inversion layer. is calculated as n gate = ε ox E ox /q, where ε ox and E ox are the dielectric constant and the normal electric field in the oxide, respectively. It is observed that, at V DS = 0, n ToB is exactly balanced by n gate, with both slopes versus V GS giving the same gate capacitance. At V DS = 0.5 V, n gate is still equal to the charge under low V DS,butn ToB is much higher, indicating that it is not entirely balanced by n gate. Hence, the gate and channel capacitance values become nonreciprocal at high V DS, i.e., dq ch,tob /dv GS > dq g,tob /dv GS. We refer to the first quantity as the ToB gate capacitance. Further examination of n ToB under high V DS reveals that the extra charge in excess of n gate originates from the charge at the source/channel junction since the ToB moves into the source when V DS increases. This movement was also observed by Lochtefeld [19], Zilli et al. [29], and Giusi et al. [30]. The extra charge at the ToB is therefore induced by the source contact instead of directly by the gate. This is a purely electrostatic effect that the current VS model does not capture, although it can very accurately reproduce experimental data. This might be due to the fact that both VS and ToB models reduce the transistor dynamics to a single point, but the choice of this point is relatively free. It can be the place where the channel charge is equal to the charge mirrored at the gate contact (VS) or the location of the ToB. Nevertheless, the velocities extracted from the two models have different interpretations and should not be confused. Fig. 8 plots the electron density and conduction band profile along the device at V DS = 0 (dashed line) and V DS = 0.5 V (solid line). It can be seen that the top of the barrier moves to the source/channel junction under high V DS, where a significant amount of charge is already present before the inversion layer starts to form. In other words, under high V DS, n ToB consists of two parts: 1) the gate-induced charge, which is balanced by n gate ; and 2) the source-induced charge at the source/channel junction at V GS = V T. Due to this additional charge contribution, the ballistic injection velocity at the top of the barrier from the nanomos simulation is lower than the value at the VS obtained by direct extractions from measured I V /C V data. In the ballistic MOSFET theory [27], [31], the mobile charge density at the top of the barrier is assumed to be induced from the gate alone. As a result, the ballistic injection velocity at the ToB in Si MOSFETs under nondegenerate conditions is υ T = 2k B T/πm = cm/s [27], [28], [31], and it increases under degenerate conditions according to (5). Our 2-D simulations, which include Fermi Dirac statistics, show that υ T at the ToB starts from cm/s at the nondegenerate limit (due to the very small separation between the light and heavier valleys, which degrades the injection velocity) and then becomes even smaller under degenerate conditions due to the extra charge induced by the movement of the ToB into the source under high V DS, which is omitted in the ballistic MOSFET model [27], [31]. The important point from the above discussion is that injection velocities extracted at the ToB from simulation and at the VS from measured or simulated I V /C V data correspond to values at two different locations in the device. The latter location, which is usually referred to as the VS, is defined at location x 0, where, in the strong inversion, Q i (x 0 )=q 0 N i (x 0 )=C oxinv (V GS V T ), with C oxinv being the gate capacitance measured under low V DS and V T being the threshold voltage under high V DS. As shown in Fig. 6, the position of the VS is about 0.6 k B T downstream from the ToB at the ON-state for the specific ETSOI device under consideration here. Although they are very close, the rapidly changing charge density there leads to a significant difference in the ToB and VS injection velocity. The fact that the ToB and the VS refer to different locations in the channel, and the velocity at the VS is larger than that at the ToB has been pointed out previously [8], but here, the difference between these two velocities is found to be much larger than previously found. Finally, we note that although the simulations presented in this paper assume ballistic transport, the discrepancy between the low and high drain bias gate capacitance values is a result of the electrostatics in the device, and it is expected to still be present when scattering is turned on. The magnitude of the source-induced charge density at the ToB discussed above in the ETSOI device is affected by several

6 LIU et al.: ON THE INTERPRETATION OF BALLISTIC INJECTION VELOCITY IN MOSFETs 999 factors, which have been studied in detail with nanomos simulations [32]. The factors that control this effect are as follows: 1) short-channel effects; 2) the source doping level and source/channel junction grading; and 3) the channel material. These effects are separately discussed next. Before discussing these effects, we should note that, in the simulations, the velocity and charge density vary with position on an exceedingly sharp spatial scale. In practice, transistors are 3-D structures with a width direction usually larger than the transport direction. Our simulation domain is only 2-D, and it is assumed that the electrostatic potential, charge density, and doping profile do not vary along the width direction. However, due to line edge roughness and process variability, the device properties may vary along the width direction, and the 3-D device can be imagined as the superposition of 2-D simulation domains with different ToB locations. This means that the position of the ToB is not uniquely determined but results from the average of different positions. Nevertheless, we believe that these model calculations illustrate the key factors that affect the carrier density at the top of the barrier and therefore cloud the experimental determination of the injection velocity at that particular location in the channel. A. Short-Channel Effects The source-induced mobile charge density at the ToB under high V DS is affected by the gate length. Simulation [32] shows that, under low V DS, the electron density at the ToB remains almost the same (and, therefore, the ToB gate capacitance is unchanged) with varying gate lengths. However, under high V DS, with constant V GS V T, both the ToB electron density and the ToB gate capacitance increase, and this increase becomes more pronounced at shorter gate lengths. It should be noted that this effect is related to, but not directly caused by, the increased DIBL accompanying the shorter gate length. Increased DIBL should only affect threshold voltage V T, and therefore the electron density, as the gate length shrinks; it should not increase the ToB gate capacitance. The increased ToB gate capacitance as the gate length shrinks is due to the increased V DS -induced movement of the ToB against the sharp electron density gradient of the source. It should be also noted that while this effect is smaller in longer devices, it does not disappear as long as the ToB enters the source/channel junction under high V DS. Other factors, such as the increased channel thickness or oxide thickness, affect n ToB under high V DS in a similar way because they reduce the gate control of the potential at the ToB and make it easier for the ToB to move into the source under high V DS. B. Doping Level and Source/Channel Junction Design The source doping level affects n ToB under high V DS through its effect on the source/channel junction abruptness a higher source doping level increases the charge density in the source/channel junction where the ToB is located and leads to larger ToB gate capacitance as V DS increases. The steepness of the source/channel junction also affects n ToB. With the same sheet charge density in the source, a more Fig. 9. InGaAs-like FETs have smaller ToB charge n ToB than Si at high V DS, and its n ToB at high and low V DS are similar since the ToB in InGaAs-like FETs is located deeper into the channel. The empty and filled symbols denote the electron density at the ToB in Si and InGaAs-like FETs under high and low V DS, respectively. flattened junction increases n ToB and ToB gate capacitance more than a steeper junction does from low-to-high V DS.The carrier density at the ToB is also affected by the source overlap distance in a similar way. C. Channel Material As mentioned in Section I, the injection velocity extracted from the measured data of III V HEMTs agrees very well with the simulation results, and both the charge density n ToB and the gate capacitance under high V DS are observed to be similar to those under low V DS in III V HEMTs nanomos simulations [11] [13]. This appears to be due to the smaller effective masses of the channel material. To investigate this hypothesis, we use a similar but even shorter L G = 12 nm SOI structure as in Fig. 1 and change the values of the transport/transverse effective masses in the channel from Si to those of InGaAs quantumconfined channels, where m x = m y = 0.079m 0. The valley degeneracy factor is also changed to g v = 1. Everything else, including the confinement effective mass m z, the dielectric constant, and the device geometry, remains the same as for the Si FETs. The source doping concentration is set to cm 3 in both cases. Fig. 9 compares the electron density and band edge profiles of Si and InGaAs-like FETs under the ON-state condition, where the charge densities at the ToB under high V DS (empty symbols) and low V DS (filled symbols) are indicated for Si (triangles) and InGaAs-like (circles) FETs, respectively. Unlike the case for Si FETs, n ToB in the InGaAs-like device remains almost the same under different drain biases. The smaller channel effective masses increase the electrostatic screening length (please see the Appendix), which causes the transition of the band edge from the source to the ToB to be broader than in Si, and the location of the ToB in InGaAs-like FETs moves deeper into the channel than for a comparable Si MOSFET, which significantly reduces the change in n ToB with drain bias.

7 1000 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 4, APRIL 2012 VI. CONCLUSION In this paper, the performance of state-of-the-art Si ETSOI MOSFETs has been investigated, followed by a careful study of the ballistic injection velocity in the ETSOI MOSFETs. Comparison of the measured ETSOI I V with 2-D nanomos simulation indicates that these devices operate at about 57% of their ballistic limit. For ballistic conditions, it was further found that the straightforward extraction of the injection velocity from measured I V /C V data produces significantly higher value than the injection velocity at the ToB as obtained from numerical simulation. The velocity extracted from measured I V /C V data corresponds to a location called the VS, which can be different from the top of the barrier under ballistic conditions. The source of this discrepancy comes from the fact that the charge at the top of the barrier is higher than the charge at the VS due to higher ToB gate capacitance at high V DS required to balance the extra source-induced charge at the source/channel junction where the top of the barrier resides. The velocity extracted at the VS with measured I V /C V data assumes that the channel gate capacitance under high V DS is the same as that measured under low V DS, which leads to a lower charge density at the VS than at the top of the barrier, and, therefore, a higher VS velocity. The VS therefore corresponds to a location a short distance into the channel from the ToB. As a result, there is no simple relation between the VS velocity and the band structure [i.e., (5) does not apply]. The effects discussed in this paper become increasingly important as the channel length shrinks. The top of the barrier injection velocity was shown to be sensitive to DIBL-related factors and to details of the source design, whereas their influence on the VS injection velocity is less pronounced. In effect, the VS charge density is calculated using the gate capacitance measured at V DS = 0 V, which is not affected by the source design. It was further shown that the VS and ToB velocities are nearly equal in devices with lower effective mass channel materials than Si such as III V HEMTs. Finally, it is important to realize that, when the ToB moves into the source, it is in a region where the charge density and velocity are changing very rapidly. This can be resolved in numerical simulations, but in practice, the precise doping profile will not be known, and line edge roughness will cause an averaging over the width of the devices. Specifying the actual ToB velocity for such devices is difficult, but the extracted VS velocity seems to be a robust device metric, as long as one realizes that its physical significance in short-channel devices is somewhat unclear. APPENDIX The longer source-to-tob distance observed in devices with smaller effective masses can be qualitatively explained with the presence of screening effects by the following argument. In the source barrier region, the 1-D Poisson equation is d 2 V (x) dx 2 = q ε s (N D (x) n(x)) (A.1) where V (x) is the potential along the transport direction, and N D (x) and n(x) are the doping concentration and electron density (at T = 0 K for simplicity) at x, respectively. Electron density n(x) can then be calculated as n(x) = E F E C (x) m m de = π 2 π 2 (E F + qv (x)). (A.2) Inserting (A.2) into (A.1), the Poisson equation has a form of d 2 V (x) dx 2 V (x) L 2 D = f(x) (A.3) where L D = ε s π 2 /qm is the length characterizing the potential change rate, similar to the Debye length [16]. A smaller effective mass m results in a longer L D, which leads to the ToB being located deeper into the channel and, therefore, a smaller n ToB at high V DS as observed above and in III V HEMTs. ACKNOWLEDGMENT Computational support was provided by the Network for Computational Nanotechnology, which is supported by the National Science Foundation under Grant EEC REFERENCES [1] D. A. Antoniadis and A. Khakifirooz, MOSFET performance scaling: Limitations and future options, in IEDM Tech. Dig., 2008, pp [2] M. S. Lundstrom, Elementary scattering theory of the Si MOSFET, IEEE Electron Device Lett., vol. 18, no. 7, pp , Jul [3] M. S. Lundstrom and Z. Ren, Essential physics of carrier transport in nanoscale MOSFETs, IEEE Trans. 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Magnone, Criticisms on and comparison of experimental channel backscattering extraction methods, Microelectron. Eng., vol. 88, no. 1, pp , Jan [31] A. Rahman, J. Guo, S. Datta, and M. S. Lundstrom, Theory of ballistic nanotransistors, IEEE Trans. Electron Devices, vol. 50, no. 9, pp , Sep [32] Y. Liu, III V nanoscale MOSFETs: Physics, modeling, and design, Ph.D. dissertation, Purdue Univ., West Lafayette, IN, Yang Liu received the B.S. degree in applied physics from the University of Science and Technology of China, Hefei, China, in 2003 and the M.S. degree in mechanical engineering and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in 2005 and 2010, respectively. His Ph.D. dissertation focused on theory, modeling, and design of nanoscale Si silicon-on-insulator field-effect transistors (FETs) and III V highelectron mobility transistors/quantum-well FETs for logic applications. He is currently an Advanced Scientist/Engineer with IBM Research, Semiconductor Research and Development Center, Hopewell Junction, NY and is responsible for the 22nm SOI RAM device R&D. His current research interests are device theory, TCAD modeling, and characterization of deeply scaled metal oxide semiconductor FETs. Dr. Liu was the recipient of the Materials Research Society Graduate Award (Silver Medal) and the Chinese Government Award for Outstanding Ph.D. Students Abroad for his Ph.D. research. Mathieu Luisier received the degree of Dipl.-Ing. degree (with highest honors) in electrical engineering and the Ph.D. degree from Swiss Federal Institute of Technology Zurich, Zurich, Switzerland, in 2003 and 2007, respectively. His Ph.D. thesis was about atomistic and full-band simulations of nanowire transistors. In 2008, he joined the Network for Computational Nanotechnology, Purdue University, West Lafayette, IN, as a Research Assistant Professor. In 2011, he joined ETH Zurich as an Assistant Professor. His current research interests include the quantum transport modeling of nanoscale devices, such as multigate nanowires, III V metal oxide semiconductor (MOS) fieldeffect transistors, or band-to-band tunneling transistors, the development of parallel numerical algorithms, and the implementation of next-generation physics-based computer-aided design tools. He is the main developer of OMEN, which is a novel quantum transport simulator dedicated to postcomplementary MOS devices. Amlan Majumdar received the B.S. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 1995 and the M.A. and Ph.D. degrees in electrical engineering from Princeton University, Princeton, NJ, in 1997 and 2002, respectively. His graduate research was on the electronic properties of 2-D electrons in periodic potentials and the optoelectronic properties of multiple quantum wells consisting of 2-D electrons. In 2003, he was a Postdoctoral Researcher with Princeton University. From 2004 to 2005, he was a Senior Device Engineer with Components Research, Intel Corporation, Hillsboro, OR, where he worked on novel transistors for logic applications. Since 2006, he has been a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY. His current research interests include modeling, fabrication, and characterization of exploratory devices for high-performance and low-power computing. Dimitri A. Antoniadis (M 79 SM 83 F 90) was born in Athens, Greece. He received the B.S. degree in physics from National University of Athens, Athens, in 1970 and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in In 1978, he joined the Massachusetts Institute of Technology, Cambridge, where he currently holds the Ray and Maria Stata Chair in Electrical Engineering and directs the multiuniversity Focus Research Center for Materials, Structures and Devices. He is well known for seminal contributions to field-effect devices and silicon process modeling. His current research interests include physics, technology, and modeling of nanoscale devices in Si, Si/SiGe, and III V materials for complementary metal oxide semiconductor applications. Dr. Antoniadis is a Fellow of the National Academy of Engineering. He was also a recipient of several professional awards. Mark S. Lundstrom (S 72 M 74 SM 80 F 94) received the B.E.E. and M.S.E.E. degrees from the University of Minnesota, Minneapolis, in 1973 and 1974, respectively. He received the Ph.D. degree in electrical engineering from Purdue University, West Lafayette, IN, in From 1974 to 1977, he worked with Hewlett-Packard Corporation, Loveland, CO, on integrated circuit process development and manufacturing support. In 1980, he joined the School of Electrical Engineering, Purdue University, West Lafayette, where he is currently the Don and Carol Scifres Distinguished Professor of Electrical and Computer Engineering. He was the Founding Director of the Network for Computational Nanotechnology and currently serves as the Chairman of the Executive Committee. He served as the Director of the Optoelectronics Research Center, Purdue University, from 1989 to 1993 and as the Assistant Dean of Engineering from 1991 to He also serves on the Leadership Council of the semiconductor-industry-funded Focus Research Center for Materials, Structures and Devices. His current research interests center on the physics of small electronic devices, particularly nanoscale transistors, on carrier transport in semiconductor devices, and on devices for energy conversion, storage, and conservation. Dr. Lundstrom is a Fellow of the American Physical Society and the American Association for the Advancement of Science and a member of the U.S. National Academy of Engineering. He currently serves as an IEEE Electron Devices Society Distinguished Lecturer. Over the course of his career, he has received a number of awards for his contributions to research and education, including the American Society for Engineering Education Frederick Emmons Terman Award, the IEEE Cledo Bruneti Award, the IEEE Electron Devices Society Education Award, and, most recently, the Semiconductor Research Corporation s Aristotle Award.