A Verilog-A Compact Model for Negative Capacitance FET

Transcription

1 A Verilog-A Compact Model for Negative Capacitance FET Version.. Muhammad Abdul Wahab and Muhammad Ashraful Alam Purdue University West Lafayette, IN 4797 Last Updated: Oct 2, 25 Table of Contents. Introduction Terminal Voltages and Parameters List Terminal Voltages Parameters List Model System and Equations Device Characteristics Summary... 9 References... 9 Appendix... A. Transient performance... B. Parameters of Conventional MOSFET... 2 C. HSPICE toolkit... 2 D. Simulating HSPICE netlist... 2 E. Checklist for model analysis... 2

2 . Introduction Continuous downscaling of the physical dimensions of MOSFET has helped to increase the transistor density, and improved the performance of the integrated circuit (IC). It has been difficult however to reduce the supply voltage (V DD ) significantly below V without sacrificing the ON current and the ON/OFF ratio, making it difficult to reduce the power density [], [2]. The increasing thermal resistance of the novel transistors (FINFET, SOI-FET, or Gate-all-around (GAA) FET has further acerbated the problem. Indeed, temperature rise due to self heating (ΔT = P R TH ) affects the reliability of the transistors [3], [4]. Therefore, any scheme to scale down the bias voltage has the potential to reduce power consumption and self-heating significantly. One of the options to reduce V DD involves improving the sub-threshold slope (S) of a transistor by overcoming Boltzmann limit (S=6 mv/dec). Negative capacitance (NC) dielectric such as ferroelectric (FE) material improves S through amplification of gate bias [5] [2] in a NC-FET (Fig. )). In this work, we develop a verilog-a compact model of a generic NC-FET [], [2]. This manual discusses the theoretical model, the circuit representation, and results through illustrative examples of the NC-FET. 2. Terminal Voltages and Parameters List S G(NC) FE G(MOS) OX B D S G (NC) B D (c) S G (NC) V FE G (MOS) D B NMOS Fig. The schematic diagram describes the geometry of the NC-FET. Symbolic representation of the NMOS NC-FET. (c) The NC dielectric is represented as a dependent voltage source (V FE ) for HSPICE simulation. The NC-FET is represented by two seriesconnected components, i.e., the NC dielectric and the MOSFET. G (NC) G (NC) C FE G (MOS) C FE G (MOS) S B D S R S C OV S B D C OV R D D Fig. 2 Ferroelectric acts as an additional gate dielectric capacitor with the conventional MOSFET. All the parasitic components: source resistance (R S ), drain resistance (R D ), gate- 2

3 source overlap and fringing capacitance (C OV ) and gate-drain overlap and fringing capacitance (C OV ) are included in the analysis. 2.. Terminal Voltages The NC-FET has two components: (i) NC dielectric and (ii) the conventional MOSFET. (i) (ii) NC dielectric: The NC dielectric is treated as an external capacitor connected in series to the gate of the conventional MOSFET. For the DC analysis, the inclusion of a capacitor in the gate terminal as an external element cannot provide meaningful results. Therefore, in HSPICE simulation, NC dielectric element is represented as a dependent voltage source which is a function of gate charge. The inclusion of the NC dielectric as a voltage source enables circuit simulation. Using the same concept multiple layers of NC dielectric as dielectric stack can be considered in the model. Conventional MOSFET: The second element is a conventional MOSFET transistor with drain, gate, source, and body terminals. This model and method work for any structure (planar, double gate, FinFET, SOI FET, GAA-FET, etc) and model (MVS/BSIM4/BSIM-CMG/etc) of the MOSFET so long it is supported by the circuit simulator. In addition to the standard elements, we introduce a dummy node to both the NC dielectric and the Conventional MOSFET. Therefore, the NC dielectric is now represented by 3 terminals and the MOSFET by 5 terminals. The dummy node (as a voltage terminal) exchanges information regarding the gate charge between the two elements. HSPICE solves the circuit of the NC-FET self-consistently to compute the unknown variables (voltages, currents, etc). The introduction of the dummy node for the MOSFET requires access to the source code. The modified source code of BSIM4 and MVS are provided along with the source code of NC dielectric. The nodes and corresponding node voltages of the NC dielectric and conventional MOSFET are defined as follows: NC dielectric: Node Description Voltage ncp Electrode with positive bias V(ncp) ncn Electrode with negative (or zero bias) V(ncn) qg_as_v Dummy node to input the gate charge V(qg_as_v) Conventional MOSFET (MVS/BSIM/etc): Node Description Voltage drain Drain voltage V(drain) gate Gate voltage V(gate) source Source voltage V(source) bulk Bulk voltage V(bulk) 3

4 qg_as_v Dummy node to output the gate charge V(qg_as_v) 2.2. Parameters List Parameters used in the negative capacitance FET model are listed below. Table also lists the physical meaning of each parameter. Math Symbol Verilog-A Symbol Description Default Unit α FE alpha Alpha coefficient of the ferroelectric.8 cm/f β FE beta Beta coefficient of the ferroelectric cm 5 /F/Coul 2 t FE tfe Thickness of the ferroelectric dielectric 7 cm For details regarding the physical interpretation of the model parameters, see Ref. [6] [9]. 3. Model System and Equations We develop the model of the NC-FET [], [2] by integrating the BSIM4/MVS model [3] of the conventional short channel MOSFET with the Landau theory of negative capacitor [5]. The subthreshold swing of a MOSFET is defined as S = dv GS dlog (I D ) = (dv GS dψ S ) ( dψ S dlog (I D ) ) = m p () where, V GS is the applied gate bias, for NC-FET it is -S. I D is the drain current, ψ S is the surface potential. The body-factor m can be obtained from the voltage divider rule assuming the gate-source and gate-drain overlap capacitances (C OV ) have negligible effect on gate charge (Q G ). m = ( dv GS dψ S ) = ( + C S ( C OX + C FE )) (2) Landau model for the negative capacitor: The Gibb s free energy of a ferroelectric material is represented by a two well energy landscape, as follows, U = α FE Q G 2 + β FE Q G 4 V FE t FE Q G. (3) 4

5 The potential (V FE ) - charge (Q G ) relation of the ferroelectric material is represented from eq (3) as V FE = 2α FE t FE Q G + 4β FE t FE Q G 3 (4) From eq (4) we can write the capacitance (C FE ) - charge (Q G ) relation of the ferroelectric material as C FE = 2α FE t FE + 2β FE t FE Q G 2 (5) In this work, negative capacitance dielectric and conventional MOSFET are represented as two different components. The I-V and C-V of the NC-FET are computed through charge and potential balance in HSPICE. We represented the ferroelectric dielectric as a dependent voltage source which is a function of Q G. To account this dependency we modified the available verilog- A models of MVS/BSIM4. 5

6 U [J/cm 3 ] P [ C/cm 2 ] P [ C/cm 2 ] P [ C/cm 2 ] C G [ F/cm 2 ] 4. Device Characteristics To illustrate the model of the NC-FET, we simulate the performance of the conventional MOSFET (NCFET with t FE = nm) and the behavior of the NC dielectric capacitor in Fig. 3. Then we evaluated the characteristics of the NMOS NC-FET, PMOS NC-FET, NC-FET CMOS inverter in Figs. 4, 5, and 6, respectively. The improved performance of the NC-FET sustains for different gate lengths (Fig. 7). The transient performance of the NC-FET CMOS inverter is evaluated in Fig. 8 (in Appendix). Conventional MOSFET FE (c) C GSOV +C GDOV +C D t FE = nm P [ C/cm 2 ] V FE = to.2 V (3 steps) C GSOV +C GDOV +C OX L G =32 nm V D = V V G(MOS) t FE =6 nm V FE Fig. 3 C-V characteristics of the conventional MOSFET. At V GS = V, gate capacitance is dominated by the gate-source (C OV ) and gate-drain (C OV ) overlap and parasitic capacitances. Polarization (P) vs applied bias (V FE ) of the ferroelectric dielectric P(VDF-TrFE). α FE and β FE coefficients of the ferroelectric dielectric are extracted through fitting of eq (4) with experiment (from Ref. [], [4]). (c) Energy landscape for different applied bias (V FE ) (eq (3)), Sim. Exp V FE C FE [ F/cm 2 ] 6

7 V S [mv/dec] Q G [ C/cm 2 ] I D [ A/ m] Q G [ C/cm 2 ] polarization (P) vs applied bias (V FE ) (eq 4), and polarization (P) vs capacitance (C FE ) (eq 5) of the ferroelectric dielectric t FE = nm t FE =3 nm.8 V.6 G(MOS) L G = 32 nm V FE t FE =3 nm V D = V BSIM4 t FE = nm t FE =3 nm (c) (d) (e) t FE = nm t FE =3 nm V FE Fig. 4 I D -V GS and Gate charge (Q G ) vs V GS characteristics of the NMOS NC-FET for different t FE using BSIM4 and Landau theory. (c) Different potential components of the NC-FET: applied gate bias ( ), voltage across the ferroelectric dielectric (V FE ), and voltage in the intermediate node G(MOS), V G(MOS). (d) Subthreshold slope (S) vs V GS for different t FE. (e) Q G vs V FE profile from the circuit simulation (red) and from eq (4) (blue) P(VDF-TrFE) Device Material t FE =3 nm 7

8 V out V S [mv/dec] D G (NC) B I D [ A/ m] Q G [ C/cm 2 ] L G = 32 nm V D = V S(c) (d) t FE = nm t FE = nm V G(MOS) V FE (e) BSIM t FE = nm t FE = nm P(VDF-TrFE) Fig. 5 Symbolic representation of the PMOS NC-FET. I D -V GS and (c) Gate charge (Q G ) vs V GS characteristics of the PMOS NC-FET for different t FE using BSIM4 and Landau theory. (d) Different potential components of the NC-FET: applied gate bias ( ), voltage across the ferroelectric dielectric (V FE ), and voltage in the intermediate node G(MOS), V G(MOS). (e) Subthreshold slope (S) vs V GS for different t FE. V DD.8.6 MOSFET NC-FET L G = 32 nm t FE = nm V in V out V in Fig. 6 Symbolic representation of the NC-FET CMOS inverter. Performance comparison of the different CMOS inverters. With the incorporation of NC dielectric, NMOS (black arrow) and PMOS (magenta arrow) are turning-on at lower effective threshold voltage compared to conventional counterpart. 8

9 S [mv/dec] S [mv/dec] I D [ A/ m] I D [ A/ m] (c) L G = 45 nm BSIM4 t FE = nm t FE =3 nm t FE = nm t FE =3 nm V D = V Fig. 7 I D vs V GS characteristics of the NMOS NC-FET from BSIM4 and Landau theory and MVS and Landau theory for 45 nm technology node. Subthreshold slope (S) vs V GS of the NMOS NC-FET from BSIM4 and Landau theory and MVS and Landau theory for 45 nm technology node. (d) P(VDF-TrFE) MVS t FE = nm t FE =3 nm t FE = nm t FE =3 nm Summary The manual describes the electrical model of the NC-FET by integrating MVS/BSIM4 model with Landau theory. Future work involves improving the physics of the model and inclusion of the transient response of the ferroelectric material. Please contact Muhammad A. Wahab (mwahab@purdue.edu) regarding any questions/comments about the negative capacitance FET compact model. References [] International Technology Roadmap for Semiconductors. [Online]. Available: 9

10 [2] Predictive Technology Model (PTM). [Online]. Available: [3] S. H. Shin, M. Masuduzzaman, M. A. Wahab, K. Maize, J. J. Gu, M. Si, A. Shakouri, P. D. Ye, and M. A. Alam, Direct observation of self-heating in III V gate-all-around nanowire MOSFETs, in 24 IEEE International Electron Devices Meeting, pp , December 5-7, 24, San Francisco CA, USA. [4] M. A. Wahab, S. Shin, and M. A. Alam, 3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature, IEEE Trans. Electron Devices, vol. 62, no., pp , Nov. 25. [5] S. Salahuddin and S. Datta, Use of negative capacitance to provide voltage amplification for low power nanoscale devices., Nano Lett., vol. 8, no. 2, pp. 45, Feb. 28. [6] A. Jain and M. A. Alam, Stability Constraints Define the Minimum Subthreshold Swing of a Negative Capacitance Field-Effect Transistor, IEEE Trans. Electron Devices, vol. 6, no. 7, pp , Jul. 24. [7] A. Jain and M. A. Alam, Proposal of a Hysteresis-Free Zero Subthreshold Swing Field- Effect Transistor, IEEE Trans. Electron Devices, vol. 6, no., pp , Oct. 24. [8] A. Jain and M. A. Alam, Prospects of Hysteresis-Free Abrupt Switching ( mv/decade) in Landau Switches, IEEE Trans. Electron Devices, vol. 6, no. 2, pp , Dec. 23. [9] K. Karda, A. Jain, C. Mouli, and M. A. Alam, An anti-ferroelectric gated Landau transistor to achieve sub-6 mv/dec switching at low voltage and high speed, Appl. Phys. Lett., vol. 6, no. 6, p. 635, Apr. 25. [] Y. Li, Y. Lian, K. Yao, and G. S. Samudra, Evaluation and optimization of short channel ferroelectric MOSFET for low power circuit application with BSIM4 and Landau theory, Solid. State. Electron., vol. 4, pp. 7 22, Dec. 25. [] M. A. Wahab and M. A. Alam, Compact Model of Short-Channel Negative Capacitance (NC)-FET with BSIM4/MVS and Landau Theory, in NEEDS Annual Meeting and Workshop, May -2, 25, Cambridge, MA, USA. [2] M. A. Alam, P. Dak, M. A. Wahab, and X. Sun, Physics-Based Compact Models for Insulated-Gate Field-Effect Biosensors, Landau Transistors, and Thin-Film Solar Cells, in IEEE Custom Integrated Circuits Conference (CICC), September 28-3, 25, San Jose, CA, USA. [3] S. Rakheja and D. Antoniadis, MVS Nanotransistor Model (Silicon), nanohub. [4] G. Salvatore, A. Rusu, and A. Ionescu, Analytical model for predicting subthreshold slope improvement versus negative swing of S-shape polarization in a ferroelectric FET., in In: MIXDES, 22, pp

11 V out V out V in Appendix A. Transient performance L G = 32 nm t FE = nm.5 (c) t [ps] t [ps] CMOS Inverter MOSFET NCFET t [ps] Fig. 8 Our developed NC-FET model can be used for transient simulation of CMOS circuits. Results of the transient simulation of the NCFET CMOS inverter of Fig. 6. Input gate pulse (V in ) vs time (t). Inverter output (V out ) vs t. (c) Zoomed version of a cycle from highlights the effect of the negative capacitor on performance of NC-FET inverter. Slow response of the ferroelectric material is neglected in the transient simulation. In practical device material response can be a limiting factor and therefore, must be accounted. Also, the representation of the negative capacitor as dependent source cannot account the transient behavior accurately.

12 B. Parameters of Conventional MOSFET Conventional MOSFET parameters are directly collected or extracted from the predictive technology model ( ). A sample set of parameters for NMOS device is provided below as an illustration. Math Symbol Description L G = 45 nm L G = 32 nm Unit (Default value) (Default value) W Channel width μm EOT Effective oxide thickness.9.75 nm ε OX Oxide dielectric constant ε Free space permittivity F/cm N sub Substrate doping density cm 3 V T Threshold voltage μ Carrier mobility cm 2 /VS v x Saturation velocity cm/s R S = R D Source/Drain resistance Ω μm C GSOV = C GDOV Source/Drain overlap F/cm capacitance n Subthreshold coefficient.5.5 δ DIBL factor V/V β.8.8 α γ.. V C. HSPICE toolkit In order to analyze the HSPICE output data, HSPICE toolkit available in Matlab is used. This can be downloaded from Make sure to add it in the Matlab path. You can use the following Matlab command to add this to the default path: addpath(location_of_hspice_toolbox_folder). D. Simulating HSPICE netlist HSPICE code can be run on file filename.sp using following command: hspice filename.sp E. Checklist for model analysis. Install the HSPICE toolkit to enable data extraction from HSPICE files. 2. Download the complete package in folder NCFET. Compile the following HSPICE files NCFET\Negative Capacitance FET Model.. HSPICE Netlists\ncfet_nmos_bsim4_Lg32nm\ncfet_nmos.sp NCFET\Negative Capacitance FET Model.. HSPICE Netlists\ncfet_pmos_bsim4_Lg32nm\ncfet_pmos.sp 2

13 NCFET\Negative Capacitance FET Model.. HSPICE Netlists\ncfet_inverter_bsim4_Lg32nm\ncfet_inverter.sp NCFET\Negative Capacitance FET Model.. HSPICE Netlists\ncfet_inverter_tran_bsim4_Lg32nm\ncfet_inverter.sp NCFET\Negative Capacitance FET Model.. HSPICE Netlists\ncfet_nmos_mvs_Lg45nm\ncfet_nmos.sp NCFET\Negative Capacitance FET Model.. HSPICE Netlists\ncfet_pmos_mvs_Lg45nm\ncfet_pmos.sp NCFET\Negative Capacitance FET Model.. HSPICE Netlists\ncfet_inverter_mvs_Lg45nm\ncfet_inverter.sp NCFET\Negative Capacitance FET Model.. HSPICE Netlists\ncfet_nmos_bsim4_Lg45nm\ncfet_nmos.sp 3. Compilation of the files will generate the filename.sw and filename.tr files for dc and transient simulations respectively. These files can be analyzed using the perform_analysis.m file. 4. Go to the folder containing the perform_analysis.m file and run it. 3