Characteristics of MOSFET with Non-overlapped Source-Drain to Gate

Transcription

1 IEICE TRANS. ELECTRON., VOL.E85 C, NO.5 MAY PAPER Special Issue on Advanced Sub-0.1 µm CMOS Devices Characteristics of MOSFET with Non-overlapped Source-Drain to Gate Hyunjin LEE a), Nonmember, Sung-il CHANG, Jongho LEE, and Hyungcheol SHIN, Regular Members SUMMARY A MOSFET structure with non-overlapped source-drain to gate region is proposed to overcome the challenges in sub-0.1 µm CMOS device.key device characteristics were investigated by extensive simulation study.fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended S/D region.electrons were induced reasonably under the spacer.internal physics and speed characteristics were studied with the non-overlap distance.the proposed structure had good subthreshold slope and DIBL characteristics compared to those of overlapped structure. key words: non-overlap, 50 nm MOSFET, SCE, extended source/drain 1. Introduction Recently, MOSFET s have been scaled down to sub- 50 nm regime [1]. Ultra shallow source/drain (S/D) extension junction depth is inevitable to suppress socalled short channel effect (SCE) while keeping low S/D parasitic resistance to guarantee current drivability. It has been reported that the current drivability of an MOSFET degrades as the overlap distance of source/drain extension to a gate decreases to less than nm [2]. However, the overlap distance of larger than 15 nm cannot be applied to sub-50 nm device fabrication. Therefore, research on the overlap distance in MOSFET design is needed. First, we begin by checking the device characteristics when the overlap distance is negative (non-overlap) in conventional MOSFET s. Figure 1 shows I D -V DS curves of a conventional 0.3 µm MOSFET with and without LDD region (non overlap distance: 80 nm), respectively. The device without the LDD has a very low current driving capability due to the very low electron concentration in the non-overlap region. Then what will be occurred if the devices shrink to sub-50 nm regime? It is expected that the electron concentration under the dielectric spacer will be increased due to the scaled-down geometry. From the rules of the generalized scaling, electric field intensity increases as the device physical dimensions scales down, even if the supply voltage is reduced [3]. On the other Manuscript received September 25, Manuscript revised January 18, The authors are with KAIST, Yusong-gu, Taejon, , Korea. The author is with Wonkwang University, Iksan, , Korea. a) hjlee@inca.kaist.ac.kr Fig. 1 Simulated IV characteristics of conventional 0.3 µm LDD MOSFET with and without LDD.The MOSFET without the LDD has a non-overlapped S/D to gate structure. hand, the design approach adopting the non-overlap S/D to gate structure can be very useful in designing ultra small size MOSFETs, because it has a positive effect on the SCE. For the suppression of short channel effect, MOSFET with electrically induced source/drain extension region has been reported [4]. In this paper, we introduce a MOSFET with nonoverlapped source-drain to gate structure to reduce the SCE in further device scaling down. The simulation was done by using process [5] and device [6] simulators. Advanced physical models are used in device simulation. 2. Device Design Figure 2 shows the schematic cross-section of the MOS- FET which has non-overlapped S/D to a gate structure. The MOSFET has 50 nm n + poly-si gate, 2 nm gate oxide and 1 nm buffer oxide under the nitride spacer. Here L no represents the non-overlap distance between S/D and gate. The buffer oxide is used to relieve possible problems from stress between the spacer and the substrate, and the process. Without the buffer oxide under the spacer, the vertical E-field of the region is greatly enhanced [7]. Fringing a gate electric field through the nitride spacer induces an inversion layer in the non-overlap region, which acts as an extended S/D region. The electron concentration under the spacer strongly depends

2 1080 IEICE TRANS. ELECTRON., VOL.E85 C, NO.5 MAY 2002 Fig. 2 Schematic cross-section of MOSFET with the non-overlap S/D to gate structure. Fig. 3 Implanted indium contours from process simulation. on the intensity of the fringing field and the non-overlap distance (L no ). Figure 3 shows the 2-D simulated doping profile of the implanted indium. An indium halo implantation was applied to control short channel effects such as punch-through current, DIBL and threshold voltage roll-off. The indium doping concentration is as high as /cm 3 near the junction depth to suppress the punch-through. In this study, 50 nm NMOSFET is designed to have the threshold voltage (V T ) of 0.3 V. We determined V T using linearly extrapolation of the threshold voltage. In general, the V T is determined by depletion charge, which is influenced by maximum depletion width and substrate doping concentration, work function difference between the gate and the substrate, and back bias. In MOSFET with non-overlapped S/D to gate structure, the V T can be also affected by the L no. Figures 4(a) and (b) show the threshold voltage ratio versus the L no. The V T difference (V T,Lno -V T,Lno=10 nm ) was normalized to that of the nitride spacer length of 20 nm where L no is 10 nm. Figures 4(a) and (b) show the optimum process condition for the indium halo im- Fig. 4 Threshold voltage versus non-overlap distance as parameters of indium halo dose (a) and indium halo energy (b). (c) compares I D -V GS with V DS = 1.2 V of 50 nm MOS with L no = 10 nm.at given halo implantation energy of 30 kev, 40 kev and 50 kev. plantation. We consider triangle symbol gives optimum process condition, since the normalized V T changes the most smoothly, which means the V T is less affected by the L no. The y-axis value of about 0 indicates little variation of V T. In Fig. 4(b), result for 50 kev indium halo energy shows less variation than that of 40 kev in the view of V T variation. But Fig. 4(c) with the view of subthreshold current at V DS =1.2V, as the implantation energy increases the off-current is getting larger. Thus, the offcurrent is smaller for 40 kev than for 50 kev. From the Figs. 4(a), (b) and (c), the optimum process condition of the halo implantation is the dose of cm 2 and the energy of kev. In this study, we use the process condition mentioned above and, as an example,

3 LEE et al.:characteristics OF MOSFET WITH NON-OVERLAPPED SOURCE-DRAIN TO GATE 1081 a device with the spacer length of 20 nm (L no = 10 nm) to show the internal physics. S/D implantation was done after defining the spacer region which was formed after the halo implantation. In this case the length of the spacer is related to the non-overlap distance between S/D and gate. To dope the S/D, arsenic ions are implanted with the dose of cm 3 and the energy of 6 kev. 3. Results and Discussion 3.1 Device Characteristics with L no Figure 5 shows the vertical E-field in the non-overlap region with 20 nm nitride spacer (L no = 10 nm). The fringing gate field through the nitride spacer induces inversion layer in the non-overlap region to act as extended S/D region. However, strength of the gate fringing field decreases significantly with the distance from the gate edge. It shows that there is a limited distance of L no to induce sufficient inversion layer. Figure 6 shows electron concentrations along the channel at different V GS from 0 V to 1.2 V and V DS of 0.05 V with V GS step of 0.3 V. Electron concentration below the spacer (L no = 10 nm) increases as the gate bias increases. At V GS =1.2V, electron concentration of larger than /cm 3 is induced under the spacer. Although there is no LDD region under the spacer, electron concentration of the region can be acted as extended S/D region due to the fringing field through the nitride spacer. This figure shows that the gate bias controls inversion layer effectively in the region below the spacer by the fringing E-field. Figure 7 shows the minimum electron concentration (A) in the region below the spacer and the concentration (B) in the channel versus a non-overlap distance at V GS =1.2V and V DS =0.05 V. As the non-overlap distance increases, the gate fringing field effect is reduced and electron concentration below the spacer is decreased. According to the result, the device with the L no of 0 nm has no decrease in electron concentration. This result is inconsistent with that of [2]. Figure 8 shows the conduction band energy along the channel at different V GS from 0 V to 1.2 V with 0.3 V step and V DS of 1.2 V. A small energy barrier exists in the non-overlapped region, and the barrier is lowered as the gate voltage increases. Figure 9 shows the on-current of 50 nm NMOS device versus non-overlap distance at V GS V T =0.9V and V DS = 1.2 V. As the non-overlap distance increases, the I on is degraded due to the increment of effective channel length. For example, the I on at a L no of 5 nm is about 1 ma/µm, which is fairly reasonable. Fig. 5 spacer. Vertical E-field plot in the region below the nitride Fig. 7 Electron concentrations in the regions below the spacer and the gate at V GS =1.2V and V DS =0.05 V. Fig. 6 Electron concentration along the channel at different V GS from 0 V to 1.2 V with 0.3 V step and at V DS of 0.05 V. Fig. 8 Conduction band energy diagram along the channel at different V GS from 0 V to 1.2 V with 0.3 V step and V DS =1.2V.

4 1082 IEICE TRANS. ELECTRON., VOL.E85 C, NO.5 MAY 2002 Fig. 9 On current of 50 nm NMOS device versus non-overlap distance at V GS =1.2V and V DS =1.2V. Fig. 11 Conduction band energy diagram under the gate region with V DS biases of 0.05 V and 1.2 V at a fixed V GS of 0 V. (a) Non-overlap distance of 10 nm.(b) Non-overlap distance of 20 nm. Fig. 10 Subthreshold slope at V DS =1.2V and DIBL characteristics with the non-overlap distance. It is noted that the I on will be improved if the effective channel length is kept the same with the L no. To keep reasonable turn-on current, the L no needs to be smaller than 10 nm. Figure 10 shows the drain induced barrier lowering (DIBL) and subthreshold slope (SS) at V DS =1.2V and V DS =0.05 V versus the L no. These results show that the non-overlapped structure is effective in suppressing the SCE. The physics of the SCE can be understood by considering the potential barrier, which is referred to DIBL. When the L no is about 10 nm, it shows smaller DIBL than that of overlapped structure (L no < 0). It means the suppression of the SCE in the non-overlapped structure. The subthreshold slope (SS) shows small value from the L no of about 0 nm to 10 nm, which also represents one of the positive aspects of the non-overlapped structure. DIBL increases significantly due to the SCE, when the S/D to gate is overlapped (L no < 0). For L no larger than 10 nm, the DIBL becomes degraded because of poor turn-on characteristics. The turn-on characteristics at low V DS (0.05 V) are degraded by the barrier peaks (shown in Fig. 11(b)) under the nitride spacers. As the V DS increases to 1.2 V, the barrier around the drain lowers as shown in Fig. 11(b), resulting in relatively better turn-on characteristics than V DS of 0.05 V. In this situation, the DIBL becomes large even though the V T is high. The SS is related to depletion capacitance, and increases with the L no. As the L no increases, the channel area to be depleted by the vertical and fringing gate field from the gate becomes wide, which in turn increases the depletion capacitance in the subthreshold slope equation. The SS then becomes degraded. Figure 11 shows the conduction band energy along the channel with the L no at given V DS biases of 0.05 V and 1.2 V and V GS of 0 V. As the L no increases from 10 nm to 20 nm, the energy band diagram looks different. The energy band diagram for the L no of 20 nm shows two peaks under both nitride spacers. As the drain bias increases from 0.05 V to 1.2 V, the barrier under the drain-side spacer lowers. The dominant factor in controlling drain current is the barrier height, which should be lowered by the gate bias. Very small DIBL of 30 mv/v and subthreshold slope of 80 mv/dec were obtained for L no = 10 nm. According to these results, it seems that the L no of around 10 nm or less is reasonable. Simulated IV characteristics are shown in Fig. 12. Figure 12(a) shows I D -V GS curves at V DS = 0.05 V and 1.2 V. The on-current at V GS = V DS =1.2V is 700 µa/µm. Even though the S/D is not overlapped to the gate, reasonable IV characteristics were obtained. In the PMOS, vertical E-field in the non-overlap

5 LEE et al.:characteristics OF MOSFET WITH NON-OVERLAPPED SOURCE-DRAIN TO GATE 1083 Fig. 14 On-current, gate capacitance, and intrinsic gate delay time versus dielectric constant. Fig. 12 Simulated IV characteristics.(a) I D -V GS curves at V DS =0.05 V and 1.2 V. (b) I D -V DS curves at V GS V T =0.3, 0.6, and 0.9 V. Fig. 15 Schematic cross-section of the modified non-overlap MOS structure with dual spacer. Fig. 13 Intrinsic gate delay versus the dielectric constant of the spacer as a parameter of the non-overlap distance. region induces inversion layer with holes to act as the extended S/D region. We believe that the same story will be applied to non-overlapped PMOS devices and need some work. 3.2 Intrinsic Gate Delay In Fig. 13, intrinsic gate delay versus the dielectric constant of the spacer is shown as a parameter of the L no. As the L no decreases, the gate delay is improved by a higher drive current due to the lower S/D resistance. The gate delay increases as the dielectric constant increases due to the parasitic fringing gate capacitance. The minimum gate delay is decided from the drive current and the gate capacitance. When the increment of the gate capacitance is smaller than that of the current with the increase of dielectric constant, the minimum gate delay is achieved. As the L no decreases, the intrinsic gate delay is improved due to higher drive current. The DIBL and the SS, however, cannot be an optimum as shown in Fig. 10. Figure 14 shows the drive current and gate capacitance at V GS = V DS =1.2 V, and intrinsic gate delay versus the dielectric constant of the spacer. As the dielectric constant increases the current is saturated with higher rate than the capacitance. With L no = 10 nm, the intrinsic gate delay time has minimum delay at the dielectric constant of 7. To get a smaller gate delay, reducing gate capacitance is needed. The gate to drain and gate to source capacitance is increased due to the overlap region between the nitride spacer and the S/D region. Figure 15 shows modified cross sectional view of MOSFET with the non-overlapped S/D structure, where the spacer consists of about 10 nm nitride and 10 nm oxide spacer regions. The oxide spacer overlaps with the S/D, by which the gate capacitance decreases a little, and the relative decreases of the capacitance becomes significant when the high-k spacer is applied instead of the nitride spacer. Figure 16 shows the drive current and gate capacitance at V GS = V DS =1.2 V, and the gate delay ver-

6 1084 IEICE TRANS. ELECTRON., VOL.E85 C, NO.5 MAY 2002 Fig. 16 On-current, gate capacitance, and intrinsic gate delay time of modified non-overlap MOS device versus dielectric constant. sus the dielectric constant of the spacer on the nonoverlapped region. The gate capacitance of modified structure is reduced, and the drive current is slightly changed. The high-k spacer induces inversion layer in the non-overlap region and the oxide spacer reduces gate capacitance effectively. The dielectric constant of the high-k spacer on the non-overlapped region is about 20 for the minimum gate delay. 4. Conclusions A new MOSFET structure with non-overlap S/D to n + poly gate has been proposed and studied by simulation. A careful optimization of halo implantation was done to suppress short channel effect. The propose structure showed very good subthreshold slop and DIBL compared to those of the overlap structure. By controlling the non-overlap distance, we could obtain reasonable speed and on-current characteristics. We have also proposed a modified non-overlap MOS structure with dual spacers to reduce intrinsic gate delay. It was shown that the utilization of high-k spacer in the MOS device with the dual spacer structure is very useful in reducing the intrinsic gate delay while keeping good short channel effect. Based on the results, we conclude reasonable non-overlap distance is between 0 (just meet the gate edge) to 10 nm. The non-overlap structure also avoids the difficulty in forming ultra shallow S/D junction. Therefore, we consider that the non-overlap structure is suitable for further device scaling. Acknowledgments This work was supported by Tera Level Nanodevices project of MOST in References [1] R.Chau, J.Kavalieros, B.Roberds, R.Schenker, D. Lionberger, D.Barlage, B.Doyle, R.Arghavani, A.Murthy, and G.Dewey, 30 nm physical gate length CMOS transistors with 1.0 ps n-mos and 1.7 ps p-mos gate delays, Electron Devices Meeting 2000, IEDM Technical Digest International, pp.45 48, [2] S.Thompson, P.Packan, T.Ghani, M.Stettler, M.Alavi, I.Post, S.Tyagi, S.Ahmed, S.Yang, and M.Bohr, Source/drain extension scaling for 0.1 /spl mu/m and below channel length MOSFETs, VLSI Technology, pp , [3] Y.Taur and T.H.Ning, Fundamentals of Modern VLSI Devices, Cambridge Univ.Press, pp , [4] S.Han, S.Chang, J.Lee, and H.Shin, 50 nm MOSFET with electrically induced source/drain extensions, IEEE Trans. Electron Devices, vol.48, no.9, pp , Sept [5] Silvaco International, ATHENA User s Manual, version R, [6] Silvaco International, ATLAS User s Manual, version R, [7] S.Chang, J.Lee, and H.Shin GIDL currents in MOSFETs with high-k dielectric, SSDM, pp , Sept Hyunjin Lee was born in Taejon, Korea, in 1979.She received the B.S.degree in electrical engineering from the Korean Advanced Institute of Science and Technology (KAIST), Taejon, in 2001, respectively, where she is currently pursuing the M.S. degree. Hers research interests include device design of nanoscale CMOS devices. Sung-il Chang was born in Pusan, Korea, in 1978.He received the B.S.and M.S. degrees in electrical engineering from the Korean Advanced Institute of Science and Technology (KAIST), Taejon, in 1999 and 2001, respectively, where he is currently pursuing the Ph.D. degree. His research interests include device design and fabrication of nanoscale CMOS devices. Jongho Lee received the B.S. degree in electronic engineering from Kyungpook National University, Taegu, Korea, in He received the M.S. and Ph.D. degrees from Seoul National University, Seoul, in 1989 and 1993, respectively, both in electronic engineering.in 1983, he worked on advanced BiCMOS process development at the Interuniversity Semiconductor Research Center (ISRC), Seoul National University, as an Engineer.In 1994, he joined the School of Electrical Engineering, Wonkwang University, Iksan, Chonpuk, Korea, where he is now an Associate Professor.From 1994 to 1998, he was with ETRI as an Invited Member of Technical Staff, working on deep submicron SOI devices, device isolation, 1/f noise, and device mismatch characterization.from August 1998 to July 1999, he was with the Massachusetts Institute of Technology (MIT), Cambridge, as a Postdoctoral Researcher, where he was engaged in research on sub-100 nm double-gate CMOS devices.his research interests include sub-100 nm device technologies, nanocrystal memory, high performance IC design, and Microsystems.

7 LEE et al.:characteristics OF MOSFET WITH NON-OVERLAPPED SOURCE-DRAIN TO GATE 1085 Hyungcheol Shin received the B.S. degree (magna cum laude) and M.S. degree in electronics engineering from Seoul National University, Seoul, in 1985 and 1987, respectively, and the Ph.D. degree in electrical engineering form the University of California, Berkeley, in 1993.From 1994 to 1996, he was with Motorola Advanced Custom Technologies, as a Senior Device Engineer.In 1996, he joined the Department of Electrical Engineering and Computer Sciences at the Korea Advanced Institute of Science and Technology (KAIST), Taejon, in 1996 as an Assistant Professor and is now an Associate Professor.His current research interests include nano CMOS, CMOS RF modeling, and RF circuits.he has published over 130 technical papers in international journals and conference proceedings and also wrote one chapter in a Japanese book on plasma charging damage.1993.dr.shin has served as a Committee Member of several international conferences, including IEEE Silicon Nano-electronics Workshop and IEEE Symposium on Plasma-Process Induced Damage (P2ID). He is a Lifetime Member of IEEK and received the Second Best Paper Award from the American Vacuum Society in 1991.He also received the Excellent Teaching Award from the Department of Electrical Engineering and Computer Sciences at KAIST in 1998.In 1999, he received The Haedong Paper Award from The Institute of Electronics Engineers of KOREA (IEEK).He has been listed in the Marquis Who s Who in the World and The Outstanding People of the 20th Century, 3rd edition.he will also be listed in International Personality of the Year in 2001.