Lecture 3: Transistor as an thermonic switch

Size: px
Start display at page:

Download "Lecture 3: Transistor as an thermonic switch"

Transcription

1 Lecture 3: Transistor as an thermonic switch Lecture 3, High Speed Devices

2 Lecture 3: Transistors as an thermionic switch Reading Guide: in Jena Transistor metrics Reservoir equilibrium Thermionic switch basics of transistor operation FET/Bipolar Transistor FET Short channel effects Lecture 3, High Speed Devices

3 N-type Field Effect Transistor Large Signal DC I ds =f(v gs,v ds ) +V DS Drain I DS +V gs Gate Source I DS 3

4 I D (ma/µm) g m (ms/µm) N-type Field Effect Transistor Metrics Output Characteristics Transfer Characteristics Transconductance R on V DS = V DS = g d On-resistancece R on = di dv DS 1 V DS 0V Output conductance di D g d = (ms/µm) dv DS VDS,V GS (Wµm) BV DS V T Threshold voltage V T when the current becomes small V GS g m = di D dv GS VDS,V GS A good FET has: Low R ON, low g d, large g m, V T >0V and a large BV DS Voltage gain requires g m >g d V GS (ms/µm) 4

5 I D (ma/µm) Log (I D ) N-type Field Effect Transistor Metrics (off-state) Output Characteristics Transfer Characteristics Transconductance V DS =0.8V V DS =0.8V SS V DS =50 mv V DS =50 mv BV DS V T Threshold voltage V GS V GS I D below V T :Sub threshold current Ideal inverse subthreshold slope: kt q log 10(e) 60 mv/decade Drain Induced barrier lowering DIBL (mv/v) A FET for digital applications has: SS ~60mV/decade Small DIBL (10-40mV/V) 5

6 Npn Bipolar transistor Large Signal DC I ds =f(v BE,V CE ) Collector I B I C V BE Base Emitter I E =I C +I B 6

7 Npn Bipolar transistor Metrics Collector current density: J C (ma/µm 2 ) g m follows from I C : g m = I C V t Output conductance:g d (ms/µm 2 ) HBTs are rarely operated at low V DS -> R on usually not important. Current gain: β F = δi C δi B A good HBT has: Very low g d, large J C, large b F large BV DS Voltage gain requires g m >g d 7

8 Ohmic contact - Reservoir Metal n ++ semiconductor Lightly doped semiconductor +V S E F Ideal ohmic contact Reservoir for electrons E C E v The applied bias sets the metal fermi level with respect to ground. (Electric potential <-> ) An ideal ohmic contact keeps the semiconductor in (Gibbs) equilibrium with the metal <-> Equal E F The n++ doping keeps the semiconductor bands flat for moderate current densities ( de f dx = J μ n n ) 8

9 n + - i n + Resistor: ballistic current n ++ Lightly doped semiconductor n V v X = ħk x m E Positive current: k x >0 Negative current: k x <0 k x E F,L E F,R If no scattering electrons flowing from left to right have positive k x electrons flowing from right to left have negative k x No current flows: +k x and -k x are equally occupied! 9

10 n + - i n + Resistor: ballistic current n ++ Lightly doped semiconductor n ++ +V D v X = ħk x m E Positive current: k x >0 Negative current: k x <0 k x E F,L qv D E F,R An applied bias lowers the drain reservoir by qv D +k x is populated by E F,L. k x is populated by E F,R. This leads to a net electron current from left to right E F,R = E F,L qv D 10

11 General Transistor Model Source Emitter V BE n ++ Channel/Base n ++ Drain Collector V DS V CE V GS Ideal transistor the potential energy of the channel is only controlled by the gate/base terminal. HBT direct control of E C,channel FET indirect control of E C,channel E F,L E F,R E C 11

12 General Transistor Model V GS =0.4V V DS =0V E C V GS =0.4V V DS =0.1V E C V GS =0.4V V DS =0.4V V GS =0.6V V DS =0.4V V GS =0.1V V DS =0.4V E C E C E C 12

13 Bipolar Transistor Realization V BE V CE n ++ p+ n ++ The base is a p+ region The base terminal is connected directly to the base No e-field Diffusion with recombination Recombination: base current This constitutes a reservoir for holes not for electrons V CE J E n n 0 τ J C E C +V CE V BE V BE 13

14 Field Effect Transistors - realization +V GS +V DS +V GS +V DS Insulator n ++ n ++ p Traditional Si-MOSFET +V GS +V DS Insulator/WB n ++ QW n ++ Wide Bandgap/insulator Quantum Well HEMT /SOI MOSFET/ Graphene FET +V GS +V DS n ++ Wide Bandgap n ++ Insulator/WB n ++ QW / Nanowire n ++ Small Bandgap (i) Insulator/WB Traditional HEMT +V GS FinFET / Nanowire FET / Carbon Nanotube FET 14

15 Field Effect Transistors indirect channel potential control x y Positive V GS NegativeV GS Positive V GS NegativeV GS y x 15

16 Field Effect Transistors indirect channel potential control Long channel FET diffusive: potential drop along the channel required. J drift = qμ n n x ε x = μ n n x de c dx Channel potential not 100% controlled by the gate complicates things. n(x) decreases -> pinch off. 16

17 Field Effect Transistors subthreshold current E 1 E FL When E 1 >> E F,L Exponential tail of Fermi-Dirac function: Current decreases exponentially with increasing E 1 This gives ideally a 60 mv / decade slope Theoretical limit for a thermionic switch F j E F E 1 kt e (E F E 1 )/kt 10 5 on-off ratio: at least 0.3 V GS 17

18 Field Effect Transistors indirect channel potential control Ballistic FET diffusive: No potential drop along the channel is required Ideal gate control sets the potential in the channel Source/Drain electrodes injects electrons Short channel effects large a drain potential can pull down E1 output conductance 18

19 Field Effect Transistors Short Channel Effects 1) We want the channel potential to be set by the gate voltage. 2) When the current through the transistor is small very little charge inside the channel. ρ 0 C/m 2. (For simplicity here) V S V G V D ε r ε 0 V = 0 3D Possion equation 3) Both drain, source and gate terminal can influence the potential inside the channel! 4) This is studied by solution to the 2D Possion Equation. ε r ε 0 V = 0 19

20 Analogue: Thermal Conduction x T=+25 C l 1 t 1 Possion Equation: ε r ε 0 V = 0 T=0 C y 2 T 2 x 2 T 2 y 0 T=0 C The linear differential equation for the steady state temperature field is equivalent to Possions equation! We want the temperature (potential) in the channel to be controlled by the temperature (potential) on the gate electrode and NOT by the drain electrode! This makes it very easy to intuivitely understand how to design an transistor! l 2 t 2 T=-25 C Thermal Conduction: λ T = 0 Temperature <-> Voltage Thermal Conductivity <-> Dielectric Constants Lecture 3, High Speed Devices

21 1 minute intuition- geometry T=+25 C T=+25 C (a) t 1 (c) t 1 T=-25 C t 2 T=-25 C t 2 T=0 C T=0 C (b) t 1 t 2 T=+25 C Rank the structures in terms of highest temperature at T=-25 C Lecture 3, High Speed Devices

22 1 minute intuition- thermal conductivity T=+25 C T=+25 C (a) l = small T=-25 C (b) l = small T=-25 C l = small l = large T=0 C T=+25 C T=0 C (c) l = large l = small l: thermal conductivity Rank the structures in terms of highest temperature at T=0 C Lecture 3, High Speed Devices

23 Laplace s Equation is linear 0V -0.5V -0.5V 0.5V 0V 0V 0V 0V 0.5V 2 x y 2 αφ = α 2 x y 2 Φ = 0 The potential at a certain point: Φ x, y = α G (x, y)v G +α D (x, y)v D + α S (x, y)v S 0< α G, D, S < 1 x,y dependence from solution of Laplace s equation Lecture 3, High Speed Devices

24 Potential Distribution V=-0.5 l l Lecture 12, High Speed Devices

25 Potential Distribution Ground plane FET V=-0.5 V=0 V=0.0 Ground Plane V= Lecture 12, High Speed Devices

26 Potential Distribution Double gate FET V=-0.5 V=0 V=0 V= Lecture 12, High Speed Devices

27 Potential Distribution Double gate FET V S V D t s t i ε r ε 0 V = 0 This can be solved easily with e.g. COMSOL. t i Analytical solution through separation of variables + Fourier series expansion. Analytic solution: V x V GS + V GS sinh π L x λ / sinh πl λ + (V DS + V GS ) sinh π L x λ / sinh πl λ λ t s + 2t i λ t s If eri=ers If eri>>ers Geometric Length Scale for the FET Lecture 3, High Speed Devices

28 Short Channel Effects L=20 nm l=10 nm L=50 nm l=10 nm L=30 nm l=10 nm Double Gate λ t s + 2t i L > 2l Short gate lengths requires thin oxide and thin semiconductors λ GAA < λ DG < λ SG Gate All Around Single Gate FinFETs/Nanowire: thicker t i /t s for the same gate length Lecture 3, High Speed Devices

Lecture 8: Ballistic FET I-V

Lecture 8: Ballistic FET I-V Lecture 8: Ballistic FET I-V 1 Lecture 1: Ballistic FETs Jena: 61-70 Diffusive Field Effect Transistor Source Gate L g >> l Drain Source V GS Gate Drain I D Mean free path much shorter than channel length

More information

Lecture 6: 2D FET Electrostatics

Lecture 6: 2D FET Electrostatics Lecture 6: 2D FET Electrostatics 2016-02-01 Lecture 6, High Speed Devices 2014 1 Lecture 6: III-V FET DC I - MESFETs Reading Guide: Liu: 323-337 (he mainly focuses on the single heterostructure FET) Jena:

More information

Metal-oxide-semiconductor field effect transistors (2 lectures)

Metal-oxide-semiconductor field effect transistors (2 lectures) Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -

More information

ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

More information

Current mechanisms Exam January 27, 2012

Current mechanisms Exam January 27, 2012 Current mechanisms Exam January 27, 2012 There are four mechanisms that typically cause currents to flow: thermionic emission, diffusion, drift, and tunneling. Explain briefly which kind of current mechanisms

More information

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

More information

MOSFET Physics: The Long Channel Approximation

MOSFET Physics: The Long Channel Approximation MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

Erik Lind

Erik Lind High-Speed Devices, 2011 Erik Lind (Erik.Lind@ftf.lth.se) Course consists of: 30 h Lectures (H322, and Fys B check schedule) 8h Excercises 2x2h+4h Lab Excercises (2 Computer simulations, 4 RF measurment

More information

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

More information

Spring Semester 2012 Final Exam

Spring Semester 2012 Final Exam Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Scaling Issues in Planar FET: Dual Gate FET and FinFETs Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar

More information

Application II: The Ballistic Field-E ect Transistor

Application II: The Ballistic Field-E ect Transistor Chapter 1 Application II: The Ballistic Field-E ect Transistor 1.1 Introduction In this chapter, we apply the formalism we have developed for charge currents to understand the output characteristics of

More information

Semiconductor Physics fall 2012 problems

Semiconductor Physics fall 2012 problems Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each

More information

ECE 305: Fall MOSFET Energy Bands

ECE 305: Fall MOSFET Energy Bands ECE 305: Fall 2016 MOSFET Energy Bands Professor Peter Bermel Electrical and Computer Engineering Purdue University, West Lafayette, IN USA pbermel@purdue.edu Pierret, Semiconductor Device Fundamentals

More information

Technology Development for InGaAs/InP-channel MOSFETs

Technology Development for InGaAs/InP-channel MOSFETs MRS Spring Symposium, Tutorial: Advanced CMOS Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco Technology Development for InGaAs/InP-channel MOSFETs Mark Rodwell University

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Lecture 11: J-FET and MOSFET

Lecture 11: J-FET and MOSFET ENE 311 Lecture 11: J-FET and MOSFET FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices.

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University

MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Appendix 1: List of symbols

Appendix 1: List of symbols Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

Transistors - a primer

Transistors - a primer ransistors - a primer What is a transistor? Solid-state triode - three-terminal device, with voltage (or current) at third terminal used to control current between other two terminals. wo types: bipolar

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at

More information

MOS CAPACITOR AND MOSFET

MOS CAPACITOR AND MOSFET EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure

More information

FIELD-EFFECT TRANSISTORS

FIELD-EFFECT TRANSISTORS FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Lecture #27. The Short Channel Effect (SCE)

Lecture #27. The Short Channel Effect (SCE) Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

Typical example of the FET: MEtal Semiconductor FET (MESFET)

Typical example of the FET: MEtal Semiconductor FET (MESFET) Typical example of the FET: MEtal Semiconductor FET (MESFET) Conducting channel (RED) is made of highly doped material. The electron concentration in the channel n = the donor impurity concentration N

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

Performance Analysis of 60-nm Gate-Length III-V InGaAs HEMTs: Simulations Versus Experiments

Performance Analysis of 60-nm Gate-Length III-V InGaAs HEMTs: Simulations Versus Experiments Purdue University Purdue e-pubs Birck and NCN Publications Birck Nanotechnology Center 7-2009 Performance Analysis of 60-nm Gate-Length III-V InGaAs HEMTs: Simulations Versus Experiments Neophytou Neophytos

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold

More information

III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis

III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis Microsystems Technology Laboratories, MIT 1 presently with Teledyne Scientific 23rd International

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two - 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large

More information

Lecture 1 Nanoscale MOSFETs. Course Structure Basic Concepts (1-38)

Lecture 1 Nanoscale MOSFETs. Course Structure Basic Concepts (1-38) Lecture 1 Nanoscale MOSFETs Course Structure Basic Concepts (1-38) 1 Course Layout 7.5 ECTS 7 Lectures 7 Excercises Written exam (t.b.d) Textbook: Nanoscale Transistors: Device Physics, Modeling and Simulation

More information

Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007

Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order

More information

Chapter 6: Field-Effect Transistors

Chapter 6: Field-Effect Transistors Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled

More information

ECE 340 Lecture 39 : MOS Capacitor II

ECE 340 Lecture 39 : MOS Capacitor II ECE 340 Lecture 39 : MOS Capacitor II Class Outline: Effects of Real Surfaces Threshold Voltage MOS Capacitance-Voltage Analysis Things you should know when you leave Key Questions What are the effects

More information

Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

More information

Plan Bipolar junction transistor Elements of small-signal analysis Transistor Principles: PETs and FETs Field effect transistor Discussion

Plan Bipolar junction transistor Elements of small-signal analysis Transistor Principles: PETs and FETs Field effect transistor Discussion Physics of silicon transistors - 1 - Plan Bipolar junction transistor homojunction and heterojunction Doping considerations Transport factor and current gain Frequency dependence of gain in a microwave

More information

Schottky diodes. JFETs - MESFETs - MODFETs

Schottky diodes. JFETs - MESFETs - MODFETs Technische Universität Graz Institute of Solid State Physics Schottky diodes JFETs - MESFETs - MODFETs Quasi Fermi level When the charge carriers are not in equilibrium the Fermi energy can be different

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "

More information

Long-channel MOSFET IV Corrections

Long-channel MOSFET IV Corrections Long-channel MOSFET IV orrections Three MITs of the Day The body ect and its influence on long-channel V th. Long-channel subthreshold conduction and control (subthreshold slope S) Scattering components

More information

Drift-diffusion model for single layer transition metal dichalcogenide field-effect transistors

Drift-diffusion model for single layer transition metal dichalcogenide field-effect transistors Drift-diffusion model for single layer transition metal dichalcogenide field-effect transistors David Jiménez Departament d'enginyeria Electrònica, Escola d'enginyeria, Universitat Autònoma de Barcelona,

More information

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling? LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and

More information

This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented.

This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. References IEICE Electronics Express, Vol.* No.*,*-* Effects of Gamma-ray radiation on

More information

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

More information

BJT - Mode of Operations

BJT - Mode of Operations JT - Mode of Operations JTs can be modeled by two back-to-back diodes. N+ P N- N+ JTs are operated in four modes. HO #6: LN 251 - JT M Models Page 1 1) Forward active / normal junction forward biased junction

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects

More information

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6 R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition Figures for Chapter 6 Free electron Conduction band Hole W g W C Forbidden Band or Bandgap W V Electron energy Hole Valence

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

8. Schottky contacts / JFETs

8. Schottky contacts / JFETs Technische Universität Graz Institute of Solid State Physics 8. Schottky contacts / JFETs Nov. 21, 2018 Technische Universität Graz Institute of Solid State Physics metal - semiconductor contacts Photoelectric

More information

ELECTRONICS IA 2017 SCHEME

ELECTRONICS IA 2017 SCHEME ELECTRONICS IA 2017 SCHEME CONTENTS 1 [ 5 marks ]...4 2...5 a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ]...5 3...6 a. [ 3 marks ]...6 b. [ 3 marks ]...6 4 [ 7 marks ]...7 5...8

More information

Performance Analysis of Ultra-Scaled InAs HEMTs

Performance Analysis of Ultra-Scaled InAs HEMTs Purdue University Purdue e-pubs Birck and NCN Publications Birck Nanotechnology Center 2009 Performance Analysis of Ultra-Scaled InAs HEMTs Neerav Kharche Birck Nanotechnology Center and Purdue University,

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

More information

nmosfet Schematic Four structural masks: Field, Gate, Contact, Metal. Reverse doping polarities for pmosfet in N-well.

nmosfet Schematic Four structural masks: Field, Gate, Contact, Metal. Reverse doping polarities for pmosfet in N-well. nmosfet Schematic Four structural masks: Field, Gate, Contact, Metal. Reverse doping polarities for pmosfet in N-well. nmosfet Schematic 0 y L n + source n + drain depletion region polysilicon gate x z

More information

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model Content- MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 2009-2013 Digital Switching 1 Content- MOS

More information

Semiconductor Integrated Process Design (MS 635)

Semiconductor Integrated Process Design (MS 635) Semiconductor Integrated Process Design (MS 635) Instructor: Prof. Keon Jae Lee - Office: 응용공학동 #4306, Tel: #3343 - Email: keonlee@kaist.ac.kr Lecture: (Tu, Th), 1:00-2:15 #2425 Office hour: Tues & Thur

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

ECE 145A/218A Power Amplifier Design Lectures. Power Amplifier Design 1

ECE 145A/218A Power Amplifier Design Lectures. Power Amplifier Design 1 Power Amplifiers; Part 1 Class A Device Limitations Large signal output match Define efficiency, power-added efficiency Class A operating conditions Thermal resistance We have studied the design of small-signal

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007

More information

Chapter 5 MOSFET Theory for Submicron Technology

Chapter 5 MOSFET Theory for Submicron Technology Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are

More information

Research Article Analyses of Short Channel Effects of Single-Gate and Double-Gate Graphene Nanoribbon Field Effect Transistors

Research Article Analyses of Short Channel Effects of Single-Gate and Double-Gate Graphene Nanoribbon Field Effect Transistors Materials Volume 6, Article ID 84469, 8 pages http://dx.doi.org/.55/6/84469 Research Article Analyses of Short Channel Effects of Single-Gate and Double-Gate Graphene Nanoribbon Field Effect Transistors

More information

Electrical Characteristics of MOS Devices

Electrical Characteristics of MOS Devices Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage

More information

MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.

MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM. INEL 6055 - Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ

More information

Microsystems Technology Laboratories, MIT. Teledyne Scientific Company (TSC)

Microsystems Technology Laboratories, MIT. Teledyne Scientific Company (TSC) Extraction of Virtual-Source Injection Velocity in sub-100 nm III-V HFETs 1,2) D.-H. Kim, 1) J. A. del Alamo, 1) D. A. Antoniadis and 2) B. Brar 1) Microsystems Technology Laboratories, MIT 2) Teledyne

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

Technische Universität Graz. Institute of Solid State Physics. 11. MOSFETs

Technische Universität Graz. Institute of Solid State Physics. 11. MOSFETs Technische Universität Graz Institute of Solid State Physics 11. MOSFETs Dec. 12, 2018 Gradual channel approximation accumulation depletion inversion http://lampx.tugraz.at/~hadley/psd/l10/gradualchannelapprox.php

More information

Carbon Nanotube Electronics

Carbon Nanotube Electronics Carbon Nanotube Electronics Jeorg Appenzeller, Phaedon Avouris, Vincent Derycke, Stefan Heinz, Richard Martel, Marko Radosavljevic, Jerry Tersoff, Shalom Wind H.-S. Philip Wong hspwong@us.ibm.com IBM T.J.

More information

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current

More information

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS 98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC

More information

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating ELEC 3908, Physical Electronics, Lecture 18 The Early Effect, Breakdown and Self-Heating Lecture Outline Previous 2 lectures analyzed fundamental static (dc) carrier transport in the bipolar transistor

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

in Electronic Devices and Circuits

in Electronic Devices and Circuits in Electronic Devices and Circuits Noise is any unwanted excitation of a circuit, any input that is not an information-bearing signal. Noise comes from External sources: Unintended coupling with other

More information

GaN based transistors

GaN based transistors GaN based transistors S FP FP dielectric G SiO 2 Al x Ga 1-x N barrier i-gan Buffer i-sic D Transistors "The Transistor was probably the most important invention of the 20th Century The American Institute

More information