IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 7, JULY

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 7, JULY Multiscale Metrology and Optimization of Ultra-Scaled InAs Quantum Well FETs Neerav Kharche, Member, IEEE, Gerhard Klimeck, Senior Member, IEEE, Dae-Hyun Kim, Member, IEEE, Jesús A. del Alamo, Fellow, IEEE, and Mathieu Luisier Abstract A simulation methodology for ultra-scaled InAs quantum well field-effect transistors (QWFETs) is presented and used to provide design guidelines and a path to improve device performance. A multiscale modeling approach is adopted, where strain is computed in an atomistic valence-force-field method, an atomistic sp 3 d 5 s tight-binding model is used to compute channel effective masses, and a 2-D real-space effective mass-based ballistic quantum transport model is employed to simulate three-terminal current-voltage characteristics including gate leakage. The simulation methodology is first benchmarked against experimental I V data obtained from devices with gate lengths ranging from 30 to 50 nm. A good quantitative match is obtained. The calibrated simulation methodology is subsequently applied to optimize the design of a 20 nm gate length device. Two critical parameters have been identified to control the gate leakage current of the QWFETs, i) the geometry of the gate contact (curved or square) and ii) the Schottky barrier height at the gate metal contact. In addition to pushing the threshold voltage toward an enhancement mode operation, a higher Schottky barrier at gate metal contact can help suppress the gate leakage and enable aggressive insulator scaling. Index Terms High electron mobility transistor (HEMT), InAs, InGaAs, nonequilibrium Greens function (NEGF), nonparabolicity, quantum well field effect transistor (QWFET), tight-binding. I. INTRODUCTION AS Si CMOS technology approaches the end of the ITRS roadmap, the semiconductor industry faces a formidable challenge to continue transistor scaling according to Moore s law [1]. Several industry and academic research groups have recently demonstrated high mobility III-V quantum well fieldeffect transistors (QWFETs), which can achieve high-speed operation at low supply voltage for applications beyond the Manuscript received November 17, 2010; revised March 11, 2011; accepted April 11, Date of publication May 23, 2011; date of current version June 22, This work was partially supported by the Semiconductor Research Corporation (SRC) and the MARCO Focus Center on Materials, Structures, and Devices. Computational support was provided by NSF through nanohub.org operated by the Network for Computational Nanotechnology (NCN) and National Institute for Computational Sciences (NICS). N. Kharche is with the CCNI, Rensselaer Polytechnic Institute, Troy, NY USA ( kharcn@rpi.edu). G. Klimeck and M. Luisier are with the Network for Computational Nanotechnology, School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN USA. D.-H. Kim is with the Teledyne Scientific & Imaging, LLC, Thousand Oaks, CA USA. J. A. del Alamo is with the Massachusetts Institute of Technology, Cambridge, MA USA. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED reach of Si CMOS technology [2] [8]. In particular, InGaAs and InAs channel QWFETs scaled down to 30 nm gate lengths have been shown to exhibit superior performance compared to Si MOSFETs and their heterogeneous integration on Si substrate has already been demonstrated [3] [8]. Device simulations provide useful insights into the operation of QWFETs and might guide experimentalists in the process of scaling their gate length below 30 nm [9], [10]. In this paper, the performance of Schottky-gated InAs QWFETs is analyzed using quantum mechanical simulations. Classical approximations such as the drift-diffusion model can neither capture the quantization of the energy levels resulting from the strong confinement of the electrons in a quantum well (QW) nor the tunneling currents in nano-scale devices. To address these limitations quantum mechanical approaches based on the effective mass approximation [10] and on the tightbinding method [9] have already been pursued. While both approaches agree well with experimental data above threshold, they are not able to reproduce the OFF-current region where gate leakage currents dominate. The absence of a real dielectric layer between the channel and the gate contact, contrary to MOSFETs, makes the III-V QWFETs very sensitive to gate leakage currents. To properly account for this effect, a multiport, two-dimensional (2-D) real-space Schödinger-Poisson solver based on the effective mass approximation [11] has been developed. Band-to-band tunneling leakage and impact ionization do not have significant effect on the I V s of the QWFETs in the operating range considered in this work and they are not included in the transport model. Hence, the OFFand gate leakage currents are equivalent. This paper is an expanded version of a recent conference proceeding [11]. A detailed discussion of the simulation methodologies and mechanisms behind the reported scaling trends in [11] are provided. The paper is organized as follows: in Section II, the device structure and its analysis through a decomposition into intrinsic and extrinsic simulation domains are introduced. Section III describes the core techniques used in this work: the 2-D real-space effective mass-based Schrödinger- Poisson solver, the tight-binding technique used to calculate the channel effective masses [12] [14], and the Newton scheme employed to calibrate the simulator to experimental data. In Section IV, the simulator is benchmarked against the measured characteristics of InAs QWFETs with gate lengths ranging from 30 to 50 nm [7]. The calibrated simulator is subsequently used to optimize the logic performance of an InAs QWFET with a gate length scaled to 20 nm. The conclusions and outlook of this work are presented in Section V /$ IEEE

2 1964 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 7, JULY 2011 Fig. 1. Schematic view of an InAs QWFET. The dashed black rectangle encloses the quantum transport simulation domain i.e., the intrinsic device. Thick black arrows depict the direction of the electron injection from the virtual contacts into the simulation domain. Two gate contact geometries curved (solid line) and flat (dotted line) are investigated. II. DEVICE DESCRIPTION The InAs QWFET [7] considered in this work is schematically shown in Fig. 1. The channel region is composed of a 10 nm In 0.53 Ga 0.47 As/InAs/In 0.53 Ga 0.47 As (2/5/3 nm, from top to bottom) QW grown on a 500 nm thick In 0.52 Al 0.48 As layer lattice matched to InP. The In 0.52 Al 0.48 As layer between the QW channel and the gate contact acts as an insulator or barrier. A Si δ-doped layer of concentration cm 2 situated 0.3 nm below the gate contact supplies the channel conduction electrons. The source/drain contacts are located on the top of the device almost 1 μm away from the gated region. To reduce the computational burden, this structure is analyzed by breaking it into two distinct domains. The intrinsic simulation domain is restricted to the region under the gate contact and an extension L side of 50 nm on each side. The ideal contacts, labeled as virtual source/drain in Fig. 1, are placed at the two ends of the intrinsic device. The part of device outside the intrinsic domain is labeled as the extrinsic domain, which is modeled via two series resistances R S and R D following the procedure described in [15]. Due to the idealized contact assumption, phenomena such as source starvation are not included in our simulations [16]. Two gate contact geometries, curved and flat, resulting from different gate-stack fabrication processes are considered. The edges of the curved gate contact are quarter circles with the radius of curvature equal to t InAlAs t ins, where, t InAlAs is the total thickness of the top InAlAs layer and t ins is the thickness of the InAlAs layer between the gate contact and the QW channel. Experimentally, a curved gate contact geometry is expected from the isotropic wet chemical etching process that is used to recess the gate [7]. III. APPROACH A three-step multiscale modeling approach is adopted to simulate the InAs QW FETs. First the strain arising from the growth of an InAs layer in the middle of two In 0.53 Ga 0.47 As layers is computed by an atomistic valence-force-field (VFF) method [17]. Then an atomistic tight-binding method [12], [13] is used to calculate the electron dispersion in the QW channel Fig. 2. (a) Schematic of the strain and electronic structure simulation domains. (b) In-plane lattice constant (a x,a z) through the center of the InAs QW and lattice constant along the growth direction (a y). The unstrained lattice constant of InAs is labeled as a InAs. and the corresponding electron effective masses. In a third step, these effective masses are inserted into a quantum transport simulator that yields the current-voltage characteristics of the devices [18], [19]. A. Strain Relaxation The InAs channel QWFETs are incorporated into an In 0.53 Ga 0.47 As/In 0.52 Al 0.48 As heterostructure system as depicted in Fig. 2, which is epitaxially grown on an InP substrate. The In 0.53 Ga 0.47 As and In 0.52 Al 0.48 As layers are lattice matched to the InP substrate. InAs and InP, however, have a lattice mismatch of 3.2%, which gives rise to a biaxial compressive strain in the InAs channel region. Such biaxial compressive strain is known to increase the band gap of the InAs QW [9]. The valence-force-field (VFF) method with a modified Keating potential is used to compute the relaxed atom positions in the strained heterostructure [12], [13], [17]. The dimensions of the strain relaxation domain are given in Fig. 2(a). Since strain is a long-range effect, a 40 nm thick InAlAs layer below the InGaAs sub-channel is included. Periodic boundary conditions are applied to the axes perpendicular to the growth direction. Their dimensions are L x = L z = 3.5 nm. This domain contains atoms and it is sufficiently large to model the random cations and disordered atom positions in the InGaAs and InAlAs layers [14] and to extract a transport and confinement effective mass, as shown later. In Fig. 2(b), the lattice constants of the relaxed heterostructure are compared to the unstrained InAs lattice constant. The in-plane lattice constant along the center of the InAs QW (a x, a z ) is compressed to the lattice constant of the InP substrate, causing an in-plane biaxial compressive strain of ε = a x /a InAs 1 = The lattice constant along the growth direction (a y ) is extended to nm in the InAs QW region, which corresponds to an orthogonal tensile strain ε = and a Poisson ratio of ν = ε /ε = The value of a y estimated using the continuum deformation theory and the bulk value of the Poisson ratio ν = [20] is nm. The (a y ) fluctuations in the InGaAs and InAlAs regions are induced by the local bond length variation due to the random placement of the In, Ga, and Al cations and by the bi-modal In-As and Ga-As/Al-As bond length distribution [21], [22].

3 KHARCHE et al.: MULTISCALE METROLOGY AND OPTIMIZATION OF ULTRA-SCALED InAs QUANTUM WELL FETs 1965 Fig. 3. (a) Bandstructure (at k z = 0) of a 5 nm thick InAs QW embedded between InGaAs and InAlAs barriers. (b) Transport (m trans ) and confinement (m conf ) effective masses as function of the InAs QW thickness. B. Tight-Binding Based Channel Effective Mass Extraction An accurate computation of the channel effective mass is critical in devices subject to strain and strong bandstructure non-parabolicities, as is the case of InAs. The effective mass determines the channel properties such as injection velocity, source-to-drain tunneling, quantum capacitance, and densityof-states [23]. Here, the effective masses of the multi-quantumwell channel are extracted from a sp 3 d 5 s tight-binding bandstructure that includes strain. The electronic structure simulator NEMO-3D [12] [14] is used for this computation. The InAs, GaAs, and AlAs tight-binding parameters are taken from Refs. [12], [24]. The bulk parameters are fully transferable to nanostructures and have previously been benchmarked against complex experimental devices such as InAs/InGaAs/InAlAs quantum dots [22] and InAs QWFETs [9]. The tight-binding electronic structure calculation domain [Fig. 2(a)] is smaller than the strain relaxation domain. Only 2 nm thick portions of the InAlAs layers on the top and the bottom of the In 0.53 Ga 0.47 As/InAs/In 0.53 Ga 0.47 As QW channel are included since the penetration of the wavefunction beyond this domain is negligible. The in-plane dimensions are the same as the strain relaxation domain. The electronic structure domain contains 7776 atoms. The bandstructure of the QW active region with a 5 nm thick InAs layer is shown in Fig. 3(a). The effect of strain and quantization due to band discontinuities at the InAs/InGaAs and InGaAs/InAlAs heterostructure interfaces are included in the tight-binding Hamiltonian. The bands shown in Fig. 3(a) are the Γ valley sub-bands. The L valley sub-bands (not shown) are at least 0.9 ev higher than the lowest Γ valley sub-band for the InAs channel thicknesses considered here. Due to the large energy separation and the low supply voltages that are applied to the devices (V DD = 0.5 V), thel valleys do not affect the operation of InGaAs based QWFETs [10] and are safely ignored in the transport calculations. The Γ valley transport effective mass (m trans) is extracted by fitting a parabola to the lowest conduction sub-band. The transport effective mass may also be obtained directly from the wavefunctions using the method presented in [25], [26], which is capable of resolving bandstructure degeneracies more accurately than the parabolic fitting method. These degeneracies do not occur in the Γ-valley dominant materials such as InAs therefore the parabolic fitting method suffices for the calculations presented here. The confinement effective mass (m conf ) is fitted to replicate the energy difference between the first two sub-bands [Fig. 3(a)]. The InGaAs and InAlAs layers around the InAs channel are included in the effective mass calculation since the band discontinuities at the interfaces and the wavefunction penetration into these layers affect the confinement in the channel. The values of the band-offsets at the heterostructure interfaces in the effective mass calculation are ΔE C,InGaAs/InAs = 0.4 ev and ΔE C,InGaAs/InAlAs = 0.5 ev, while the transport effective masses of In 0.53 Ga 0.47 As and In 0.52 Al 0.48 As are m 0 and m 0, respectively [27], [28]. The In 0.53 Ga 0.47 As and In 0.52 Al 0.48 As effective masses along the growth direction are used as fitting parameters to obtain the correct gate leakage current as explained later. Such an elaborate, atomistic-based fitting procedure allows for an accurate determination of the channel transport and confinement effective masses. As shown in Fig. 3(b), both the transport and confinement effective masses in the InAs QW are significantly larger than their bulk value (m InAs = m 0 ) due to the strong quantum confinement, the wavefunction penetration into the heavier effective mass InGaAs and InAlAs barrier layers, and the biaxial strain. The effective masses become heavier as the QW thickness is reduced emphasizing the strong non-parabolic dispersion of InAs. C. 2-D Real Space Effective Mass Simulator The Schrödinger and Poisson equations are solved selfconsistently using the effective mass approximation on a 2-D finite-difference grid [18]. The grid is uniform and the spacing along the x and y-directions are Δx = 0.25 nm and Δy = 0.2 nm, respectively. The quantum transport simulation domain is shown in Fig. 1. In the Poisson calculation, Dirichlet boundary conditions are applied to the gate contact (the potential is fixed) while Von Neumann boundary conditions are applied to the remaining boundaries (the electric field is set to 0). Consequently, the potential in the source and drain extensions automatically adjusts itself to ensure charge neutrality and zero electric field at the boundaries [15]. In the ballistic transport model used here, electrons are injected into the device from the source, drain, and gate contacts at different energy values and the resulting contributions are summed up to obtain the carrier and current densities. The real space technique accurately accounts for the longitudinal (x-axis) and transverse (y-axis) mode coupling [18] and for gate leakage currents. D. Calibration Methodology To calibrate the simulator to the experimental data, five fitting parameters are used: i) L g the gate length, ii) t ins the thickness of the InAlAs insulator layer between the QW channel and the gate contact, iii) m ins the effective mass of the InAlAs insulator along the growth direction (y),iv)m buf the effective mass of the InGaAs sub-channels along the growth direction (y), and (v) Φ B the Schottky barrier height at the gate metal contact. The leakage and sub-threshold (low V gs ) regimes of the I d V gs characteristics are chosen as fitting regions because the currents are very sensitive to the device dimensions and material parameters there, but they do not depend on the source and drain series resistances. As a result, the gate leakage current and the subthreshold slope are properly modeled. The currents

4 1966 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 7, JULY 2011 at high V gs are mainly governed by the source and drain series resistances, which are not adjusted but set to the experimentally measured values, R S = 0.21 Ω mm and R D = 0.23 Ω mm. The selection of the fitting parameters is based on two criteria: i) the fabrication process variability and ii) the sensitivity of the drain current. L g and t ins are respectively determined by lithography and wet chemical etching processes, which are prone to variability [7], [29]. Likewise, the difficulty of controlling the surface conditions before metal deposition induces process variability in Φ B [6], [30]. The effective masses of the In 0.53 Ga 0.47 As and In 0.52 Al 0.48 As top layers along the growth direction (m buf and m ins respectively) are not accurately known from the experimental measurements and are also included in the fitting procedure. Their values, however, are allowed to vary only within the experimentally reported ranges [27], [28]. The 2-D electrostatics is governed by L g and t ins, while t ins, m buf, m ins, and Φ B control the electron tunneling probability from the gate into the InAs channel, which in turn determines the gate leakage current. The thickness of the InAs channel and the InGaAs buffer are not included in the fitting procedure because they are determined by the Molecular Beam Epitaxy (MBE) growth, which is a precise atomic layer deposition technique. The electron affinity of the InAs channel (χ = 4.9 ev [28]) and the conduction band offsets at the heterostructure interfaces (ΔE C,InGaAs/InAs = 0.4 ev and ΔE C,InGaAs/InAlAs = 0.5 ev [27], [28]) are not considered as fitting parameters because the drain current is weakly sensitive to them. The drain current is parameterized as I d (L g,t ins,m ins, m buf, Φ B). An iterative approach (Fig. 4) is used where, at each iteration, the subthreshold I d V gs characteristics are computed and compared to the experimental data. If the deviation from the experimental data is larger than the tolerance, a new guess to the parameter vector is computed using a Newton-Raphson scheme [31]. The partial derivatives composing the Jacobian matrix are computed numerically. For example, the partial derivative with respect to the gate length L g is I d / L g = (I i,δl g d Id i)/δl g where, i is the iteration count, Id i is the drain current of the reference device parameterized as Id i(li g, t i ins, m i ins, m i buf, Φi B ), δl g is change in the gate length of a new device from the reference device, and I i,δl g d is the drain current of a new device parameterized as I i,δl g d (L i g + δl g,t i ins,m i ins,m i buf, Φi B ). The same procedure is repeated to compute the partial derivatives with respect to t ins, m ins, m buf, and Φ B. The parameter shifts used to compute the numerical derivatives are (δl g,δt ins,δm ins,δm buf,δφ B)= (0.5 nm, 0.2 nm, m 0, m 0, 0.05 ev), where m 0 is the free electron mass. For each device, the voltage sweep shown in Fig. 4(a) requires typically 4 hours on 40 cores on a 2.5 GHz quad core AMD 2380 processor [32]. IV. RESULTS The methodology presented in Section III is first used to calibrate the simulator against experimental I d V gs from devices with gate lengths ranging from 30 nm to 50 nm [7]. The calibration phase can be seen as a metrology experiment, where Fig. 4. (a) Experimental I d V gs characteristics of the 30 nm gate length device. (b) Flow chart of the parameter fitting procedure. the actual gate lengths and material properties are estimated. The resulting calibrated simulator is then used to optimize the design of a 20 nm gate length device. A. Comparison to Experimental Data Gate leakage currents are much larger in QWFETs than in conventional Si MOSFETs due to the absence of a proper insulator layer such as SiO 2 or HfO 2. Moreover, the gate contact geometry plays an important role in determining the magnitude of the gate leakage currents. The shape of the gate contact depends on the fabrication technique used to thin down the insulator before deposing the gate metal stack. Anisotropic etching and metal gate sinking ideally lead to a flat gate contact while isotropic etching leads to a curved gate contact (Fig. 1). Flat or curved gate contact geometries act differently on the leakage current magnitude as illustrated in Fig. 5(a). Both devices perform similarly in the high V gs regime. The flat gate device exhibits a lower subthreshold slope SS = 83.5 mv/dec as compared to the curved gate device (SS = 89.7 mv/dec), but its gate leakage current is about 2 higher. The difference between the drain currents at low V gs is the result of gate leakage (I g ) suppression in the curved gate contact device. The current distribution in the gate leakage regime is shown in Fig. 5(b) and (c). Gate leakage currents are concentrated at

5 KHARCHE et al.: MULTISCALE METROLOGY AND OPTIMIZATION OF ULTRA-SCALED InAs QUANTUM WELL FETs 1967 Fig. 5. (a) Intrinsic I d V gs and I g V gs characteristics of an InAs QWFET (L g = 51 nm) with a flat (solid lines) and a curved (dashed lines) gate contact. OFF-state (V gs = 0.4 V and V ds = 0.5 V) current distribution in (b) a flat gate contact device and (c) a curved gate contact device. TABLE I DEVICE DIMENSIONS AND MATERIAL PARAMETERS OBTAINED FROM THE FITTING PROCEDURE the edges of the contact due to lower tunneling barriers and higher electric fields there as compared to the central region of the gate contact [11]. The curved gate device is characterized by a thicker insulator at the edges of the gate contact, which leads to a suppression of the leakage current. Thus, an accurate description of the gate contact geometry is crucial to reproduce the experimental I d V gs, especially in the leakage and subthreshold regimes, and can be seen as a design parameter. A curved gate geometry is clearly seen in the TEM micrographs of [7]. A curved gate geometry, which resembles that of the experimental devices, is therefore used in the benchmarking procedure. As shown in Fig. 1, the shape of the edges of the curved gate contact is a quarter circle with the curvature radius equal to t InAlAs t ins, which changes as t ins changes in the fitting procedure. The results of the device metrology for devices with gate lengths ranging from 30 nm to 50 nm are listed in Table I. Here, the transport and confinement effective mass values extracted from the tight-binding bandstructures are used in the InAs channel region, which for a 5 nm thick InAs channel amount to m trans = m 0 and m conf = m 0, respectively [Fig. 3(b)]. The parameter values at the end of the fitting procedure are close to the experimentally reported values, which are used as an initial guess [7]. The effective masses of the InGaAs buffer (m buf ) and the InAlAs insulator (m ins ) layers are not allowed to vary between the different devices since they are all fabricated side by side on the same heterostructure. The effective mass values after convergence of the fitting process are within the ranges reported in the literature, which are m m 0 for In 0.53 Ga 0.47 As and m m 0 for In 0.52 Al 0.48 As [27], [28]. The converged values for the gate length and insulator thickness are within the expected process variability of the wet chemical etching step used to thin Fig. 6. Comparison between the experimental and simulated I d V gs characteristics of (a) 30 nm, (b) 40 nm, and (c) 50 nm QWFETs and I d V ds characteristics of (d) 30 nm, (e) 40 nm, and (f) 50 nm gate length InAs QWFETs. The I d V ds characteristics in figures (d)-(f) are calculated at V gs equal to 0.0 V, 0.1 V, 0.2 V, 0.3 V, and 0.4 V. TABLE II DEVICE PERFORMANCE PARAMETERS OF THE SIMULATED AND EXPERIMENTAL DEVICES down the InAlAs insulator prior to gate metal deposition [7]. Slightly different values of Φ B are justified because of the lack of precise control of the surface oxides, which modify its value from device to device [7]. The experimental transfer I d V gs and output I d V ds characteristics are compared to the simulation results in Fig. 6. It should be noted that only the low V gs regime is used in the fitting procedure as described in Fig. 4. The performance parameters extracted from the experimental and simulated I d V gs in Fig. 6 agree reasonably well, as shown in Table II. The injection velocity (v inj = I ON /Q top ) is calculated at the top of the potential barrier in the InAs channel [23]. At high biases, the I V characteristics are dominated by the source and drain contact resistances, which are modeled as two external series resistances R S and R D attached to the intrinsic device (Fig. 1). The I d V gs and I d V ds characteristics of the intrinsic device are calculated for the bias ranges 0.4 V int gs 0.3 V and 0 V int ds 0.5 V. The extrinsic

6 1968 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 7, JULY 2011 device characteristics are then computed from the drain current, I d, at given extrinsic terminal voltages (V gs and V ds )using V gs = Vgs int + R S I d and V ds = Vds int +(R S + R D )I d [15]. The good quantitative agreement shown in Fig. 6 is enabled by the consideration of a curved gate contact geometry, an accurate estimation of the channel effective masses, as well as the parameter adjustments listed in Table I. The simulated I d V ds characteristics show a very good agreement with the experimental I d V ds at low bias voltages while I d is overestimated at high bias voltages (Fig. 6). The overestimation of I d is related to the fact that scattering is not included in the ballistic quantum transport model. Electronphonon, interface roughness, and alloy disorder scattering appear to play a non-negligible role at high biases. The deviation between the simulated and experimental I d is larger in devices with a longer gate contact. In effect, electron transport in longer devices is more affected by scattering than in shorter devices, which operate closer to their ballistic limit. B. Design Optimization of a 20 nm Device After benchmarking the simulation approach and providing metrology insight into experimental devices, we explore the performance of a hypothetical 20 nm gate length device. The effects of the InAs channel thickness (t InAs ), the InAlAs insulator thickness (t ins ), and the Schottky barrier height at the gate metal contact (Φ B ) are investigated. A flat gate contact geometry provides a superior gate control of the channel potential as compared to a curved contact (Fig. 5) at the price of higher gate leakage current. Since the leakage can be reduced through Schottky barrier engineering, as explained later, a flat gate geometry will be used in the performace evaluation of the 20 nm gate length device. A flat gate contact can be easily fabricated by replacing the isotropic wet chemical etching step used to thin down the InAlAs insulator layer by an anisotropic etching or by a metal gate sinking technique [6]. These advanced fabrication techniques will result in smaller radius of curvature or near ideal flat contact. The performance parameters (SS, DIBL, and I ON /I OFF ratio) are calculated by using the constant overdrive voltage method [33]. The threshold voltage V T is determined from a linear extrapolation of the I d V gs characteristics at the peak transconductance to zero I d (maximum-g m method [34]) and a supply voltage V DD of 0.5 V is used. The ON-state is defined as V gs = V T + 2V DD /3, V ds = V DD while the OFF-state is defined as V gs = V T V DD /3, V ds = V DD. The capacitances are defined as i) the gate capacitance: C g = dq s /dv gs, ii) the insulator capacitance: C ins = ε ins /t ins, and iii) the inversion layer capacitance: C inv = dq s /dψ s [35]. Here, Q s is the sheet charge density in the InGaAs/InAs/InGaAs composite channel, ε ins is the dielectric constant of the InAlAs barrier, and ψ s the surface potential at the interface between the barrier and the composite channel. 1) InAs Channel Thickness (t InAs ): The effect of scaling down t InAs can be analyzed by noting that the QWFET is electrostatically very similar to a fully depleted silicon on insulator (FD-SOI) MOSFET [29], [36], [37]. In a QWFET, the InAs channel thickness plays a role similar to the Si body Fig. 7. (a) (c) InAs QW thickness (t InAs ) scaling. (a) SS and DIBL. (b) V T and I ON /I OFF ratio. (c) C g and C inv as function of the gate overdrive (V gs V T ). The same device dimensions (except t InAs ) as in Fig. 1 are used. t ins = 4nm.Φ B = 0.7 ev. (d) (f) InAlAs insulator thickness (t ins ) scaling. (c) SS and DIBL and (d) I ON /I OFF ratio of devices with Φ B = 0.7 ev and 1.1 ev. (e) C g and C inv as function of (V gs V T ). The same device dimensions (except t ins ) as in Fig. 1 are used. L g = 20 nm. thickness in a FD-SOI MOSFET. Higher gate length to channel thickness ratio in a thin InAs channel QWFET results in a stronger gate control of the channel surface potential, which improves SS and DIBL [Fig. 7(a)]. The strong electrostatic confinement of electrons in thin InAs QW devices pushes the channel conduction subbands to higher energies, which subsequently results in higher V T and facilitates enhancement mode operation of such devices [Fig. 7(b)]. The channel effective mass along the transport direction increases as t InAs decreases (Fig. 3), which leads to a lower electron injection velocity (v inj ), but a higher carrier density (N inv ) at the QWFET virtual source [38]. The net effect is a higher I ON in thin InAs channel devices. The 2-D electron gas in thinner channel devices is located closer to the gate, resulting into a higher gate leakage and I OFF.Ast InAs is slightly reduced, the higher I ON more than compensates the larger I OFF, so that the I ON /I OFF ratio actually increases. However, if t InAs is further reduced, the increase of I OFF becomes more important and the I ON /I OFF ratio starts to saturate [Fig. 7(b)]. The total gate capacitance, C g, which is the series combination of C ins and C inv, increases as t InAs decreases due to the increase in C inv [Fig. 7(c)]. The increase in C inv in thin t InAs devices is attributed to the increase of both its components, namely the quantum capacitance C Q and the centroid capacitance C cent. C Q increases because of a higher effective mass while C cent increases because the electron gas is closer to thegateinthint InAs devices [39].

7 KHARCHE et al.: MULTISCALE METROLOGY AND OPTIMIZATION OF ULTRA-SCALED InAs QUANTUM WELL FETs 1969 Fig. 8. (a) I d V gs and I g V gs characteristics of InAs QWFETs with Φ B = 0.7 ev and 1.1 ev. (b) V T and I ON /I OFF ratio as function of Φ B. The device dimensions are the same as in Fig. 1 with L g = 20 nm and t ins = 3nm. 2) InAlAs Insulator Thickness (t ins ): The scaling behavior of t ins in devices with Φ B of 0.7 ev and 1.1 ev is illustrated in Fig. 7(d) (f). When Φ B = 0.7 ev, the performance metrics SS, DIBL, and I ON /I OFF ratio improve as t ins is scaled down until 3.4 nm. This can be attributed to a better electrostatic control of the channel in thin insulator devices. When t ins is scaled below 3.4 nm, DIBL keeps decreasing, while the SS and I ON /I OFF ratio, which are affected by the electron tunneling across the InAlAs insulator, start degrading due to an excessive gate leakage. This degradation can be controlled by increasing Φ B to 1.1 ev, which increases the tunneling barrier height between the gate and the InAs channel, reduces the gate leakage, and therefore improves the SS and I ON /I OFF ratio even with the InAlAs layer scaled down to 3 nm [Fig. 7(d) and (e)]. Since III V devices are characterized by a small density-ofstates effective mass and therefore small C inv, the down scaling of t ins does not significantly increase C g [Fig. 7(f)]. Similar trends in C g are observed in the experiments [39]. 3) Schottky Barrier at the Gate Metal Contact (Φ B ): As shown in Fig. 7(d) and (e), a device with Φ B = 1.1 ev shows a significant improvement in SS and I ON /I OFF ratio compared to a device with Φ B = 0.7 ev. To explain this effect the I d V gs and I g V gs characteristics of devices with the same t ins = 3 nm, but different Φ B (0.7 and 1.1 ev) are compared in Fig. 8. Under the same bias conditions, the device with Φ B = 1.1 ev shows a 100 smaller gate leakage current (I g ) as compared to the device with Φ B = 0.7 ev. The longitudinal and transverse band-diagrams of the same devices in the OFF-state (V ds = V DD, V gs V T = V DD /3) are shown in Fig. 9. The same V ds and V gs V T result in almost the same band bending along the channel ensuring the same source to drain current in both devices. Electrons tunneling from the gate terminal into the channel experience a higher energy barrier in the Φ B = 1.1 ev device as compared to the Φ B = 0.7 ev device because of the metal gate Fermi level offset equal to the Schottky barrier difference (ΔΦ B = 0.4 ev). With Φ B = 0.7eV,thegate electrons must tunnel through the InAlAs insulator layer only to reach the InAs channel while they must tunnel through the InAlAs and InGaAs layers when Φ B = 1.1 ev, considerably reducing the gate leakage current. Although I g of the device with Φ B = 1.1 ev shows a 100 reduction, its I ON /I OFF ratio shows only a 7 improvement compared to the device with Φ B = 0.7 ev [Fig. 7(e)]. This is due to the fact that the OFF-current, when Φ B = 1.1 ev, is no longer dominated by gate leakage currents, but by the thermionic emission of electrons from the source to the drain. Fig. 9. (a) Conduction band diagrams along three horizontal lines through the center of i) the InAlAs insulator, ii) the top InGaAs barrier, and iii) the InAs channel of a L g = 20 nm InAs QWFET with Φ B = 0.7 ev in the OFF-state. (b) Same as (a) but for Φ B = 1.1 ev. (c) Band diagram of the device in (a) along a vertical line near the drain side edge of the gate contact. (d) Same as (c) but for Φ B = 1.1 ev. The thickness of the arrows in [(c), (d)] schematically shows the direction and the magnitude of the electron tunneling current. In addition to a larger I ON /I OFF ratio, a higher Φ B pushes the threshold voltage V T toward positive values. In Fig. 8, the V T values of the devices with Φ B = 0.7 ev and Φ B = 1.1 ev are 0.11 V and 0.29 V, respectively. The positive shift in V T is equal to the Schottky barrier difference ΔΦ B = 0.4 ev. Such a positive V T shift is highly desirable for the enhancement mode operation of the n-type FET in CMOS logic applications [4], [6]. The variation of the I ON /I OFF ratio and V T for the intermediate values of Φ B are shown in Fig. 8(b). A higher Φ B linearly pushes V T toward a positive value while the I ON /I OFF ratio increases in a nonlinear fashion. Higher Φ B values can be achieved by using higher work function metals and semiconductor surface treatments [6], [30], [40]. V. C ONCLUSION The performances of InAs QWFETs have been analyzed by using a multiscale device simulation approach. The effective mass of the InAs channel raises significantly from its bulk value due to strong confinement effects, which are included on the atomistic scale through a sp 3 d 5 s tight-binding model. The gate tunneling is critical in the device analysis and is included in a 2-D Schrödinger-Poisson solver by injecting carriers from the gate contact in addition to the source and drain contacts. The simulation approach is calibrated against experimental devices with gate lengths ranging from 30 to 50 nm. A good quantitative match between the experimental and simulated current-voltage characteristics is reported. The accurate description of the shape of the gate contact is essential to replicate the experimental results. The calibrated simulation methodology has been used to investigate the design optimizations of a hypothetical 20 nm gate length InAs QWFET. The scaling of the InAs channel thickness and the InAlAs insulator thickness improve the logic

8 1970 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 7, JULY 2011 performance due to a stronger gate control of the channel potential. An excessive scaling, however, leads to higher gate leakage current, which degrades the device performances. The gate leakage current can be suppressed by increasing the Schottky barrier height at the gate metal contact, which also pushes the threshold voltage toward the enhancement mode operation. As a result of the reduced gate leakage, devices with higher Schottky barrier can be scaled more aggressively compared to devices with lower Schottky barrier. The simulation tool, OMEN_FET, that generated the results presented in this paper is available on nanohub.org [19]. REFERENCES [1] ITRS, International Technology Roadmap for Semiconductors, [Online]. Available: [2] S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. J. Phillips, D. Wallis, P. Wilding, and R. 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9 KHARCHE et al.: MULTISCALE METROLOGY AND OPTIMIZATION OF ULTRA-SCALED InAs QUANTUM WELL FETs 1971 Neerav Kharche (M 10) received the B.Tech. and M.Tech. degrees in materials science and engineering from the Indian Institute of Technology, Bombay, India, in 2003 and the Ph.D. degree in electrical engineering from Purdue University, West Lafayette, IN, in In 2010, he joined the Computational Center for Nanotechnology Innovations, Rensselaer Polytechnic Institute, Troy, NY, as a Computational Scientist. His main research interests include electronic structures and quantum-transport in nanoscale devices. His current research interests include modeling graphene, III V, and SiGe devices using ab inito and tight-binding methods. Gerhard Klimeck (SM 04) received the B.S. degree in electrical engineering from Ruhr-University Bochum, Bochum, Germany, in 1990 and the Ph.D. degree from Purdue University, West Lafayette, IN, in He was a member of the technical staff with the Central Research Laboratory, Texas Instruments Incorporated. He was the Technical Group Supervisor with the Applied Cluster Computing Technologies Group and has been continuing to hold his appointment as a Principal Member with the Jet Propulsion Laboratory, National Aeronautics and Space Administration, Pasadena, CA, on a faculty part-time basis. He is the Director with the Network for Computational Nanotechnology, Purdue University, and a Professor of electrical and computer engineering with Purdue University. He leads the development and deployment of web-based simulation tools, research seminars, tutorials, and classes that are hosted on which is a community website that is utilized by over users annually. He has been the lead on the development of NEMO 3-D, which is a tool that enables the simulation of tens of million of atoms in quantum-dot systems, and NEMO 1-D, the first nanoelectronic computer-aided-design tool. His research interest include the modeling of nanoelectronic devices, parallel cluster computing, and genetic algorithms. He is the author of more than 250 peer-reviewed publications and over 400 conference presentations. Dr. Klimeck is a member of the American Physical Society, the Eta Kappa Nu Society, and the Tau Beta Pi Society. Dae-Hyun Kim (M 08), photography and biography not available at the time of publication. Jesús A. del Alamo (F 06) received the B.S. degree in telecommunications engineering from the Polytechnic University of Madrid, Madrid, Spain, in 1980 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Palo Alto, CA, in 1983 and 1985, respectively. From 1985 to 1988, he was with Nippon Telegraph and Telephone Large-Scale Integration Laboratories, Atsugi, Japan. Since 1988, he has been with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, where he is currently a Donner Professor and a MacVicar Faculty Fellow. He is also active in online laboratories for science and engineering education. His current research interests include microelectronic technology for communications and logic processing. Dr. del Alamo is a member of the Royal Spanish Academy of Engineering. He currently serves as an Editor of IEEE ELECTRON DEVICE LETTERS. He was a recipient of the National Science Foundation Presidential Young Investigator Award. Mathieu Luisier received the Dipl.-Ing. degree (with highest honors) in electrical engineering and the Ph.D. degree from the Swiss Federal Institute of Technology Zurich, Zurich, Switzerland in 2003 and His Ph.D. thesis was about atomistic and full-band simulations of nanowire transistors. In 2008, he joined the Network for Computational Nanotechnology, Purdue University, West Lafayette, IN, as a Research Assistant Professor. He is the main developer of OMEN, which is a novel quantum-transport simulator dedicated to postcomplementary MOS devices. His current research interests include the quantum-transport modeling of nanoscale devices, such as multigate nanowires, III V metal oxide semiconductor (MOS) field-effect transistors or band-to-band tunneling transistors, the development of parallel numerical algorithms, and the implementation of next-generation physics-based computeraided-design tools.