Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation

Transcription

1 Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation Alon Vardi, Lisa Kong, Wenjie Lu, Xiaowei Cai, Xin Zhao, Jesús Grajal* and Jesús A. del Alamo Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA, U.S.A *ETSI Telecomunicación, Universidad Politécnica de Madrid, Madrid, Spain Dec. 5, 2017 Sponsors: DTRA (HDTRA ) NSF E3S STC (grant # ) Lam Research Korea Institute of Science and Technology 1

2 FinFETs Intel Si Trigate MOSFETs Double gate Tri gate FinFETs used in state of the art Si CMOS improved short channel effects smaller footprint but higher parasitics 2

3 Si and InGaAs FinFETs normalized by gate periphery [ms/ m] Si FinFETs 14 nm 22 nm Planar Si 32 nm // Planar Si planar FinFET: performance 3

4 Si and InGaAs FinFETs normalized by gate periphery normalized by fin footprint [ms/ m] Si FinFETs 14 nm 22 nm Planar Si 32 nm 0.0 // 0 // Planar Planar / [ms/ m] AR=H c / Si FinFETs (V DD =0.8 V) 4.3 Si planar FinFET: performance, performance per footprint Key challenge for FinFETs efficient transport on sidewalls H c 4

5 Si and InGaAs FinFETs normalized by gate periphery normalized by fin footprint [ms/ m] Si FinFETs 14 nm 22 nm 0.0 // 0 // Planar Planar III V planar ~ Si planar Planar InGaAs (V DD =0.5 V) Lin, EDL2016 Planar Si 32 nm / [ms/ m] AR=H c / Si FinFETs (V DD =0.8 V) 4.3 H c 5

6 Si and InGaAs FinFETs normalized by gate periphery normalized by fin footprint [ms/ m] Si FinFETs 14 nm 22 nm Planar InGaAs (V DD =0.5 V) Lin, EDL2016 Planar Si 32 nm 0.0 // 0 // Planar Planar / [ms/ m] (III V FinFETs) < (Si) Target of =5 nm yet to be demonstrated Target: W F =5 nm Si FinFETs (V DD =0.8 V) 4.3 InGaAs FinFETs H c 6

7 Si and InGaAs FinFETs normalized by gate periphery normalized by fin footprint [ms/ m] Si FinFETs 14 nm 22 nm Planar InGaAs (V DD =0.5 V) Lin, EDL2016 Planar Si 32 nm InGaAs FinFETs 0.0 // 0 // Planar Planar / [ms/ m] Target: W F =5 nm Si FinFETs (V DD =0.8 V) 4.3 III V FinFET: < 20 nm Challenge: Improve III V sidewall conductivity InGaAs FinFETs H c 7

8 SiO 2 Mo/W SiO 2 Mo/W cap Mo L f,g InGaAs channel Mo L g InGaAs channel InAlAs MIT InGaAs FinFET s Gen. #2 vs. #1 SiO 2 Mo/W InGaAs InAlAs Wet recess Gen. #1: Vardi et al., VLSI 2016, EDL nm Gen #2: L f HSQ SiO 2 HfO 2 Mo/W Cap Channel Dry+DE recess InP 40nm ~20 nm ~5 nm Gen #1: Wet cap recess 3 Digital etch cycles 40 nm channel height δ doping Dry cap recess 5 Digital etch cycles 50 nm channel Fin top passivation Remove δ doping (in 2 nd stage) Gen. #2: This work 8

9 Process Technology: contact-first W direction L g direction InP stopper Doping SiO 2 Mo/W InGaAs cap InGaAs channel InAlAs Contact deposition Yield R C < 10 Ω µm Lin, IEDM 2013 Lu, EDL 2014 Vardi, EDL

10 W direction Dry+Digital Etch cap recess L g direction InP stopper Doping Mo/W InGaAs cap InGaAs channel InAlAs Contact etch Reactive ion etching No metal pullback III V cap pullback only during digital etch L f L g Digital etching SiO 2 Mo/W Cap Channel Dry+DE recess 40nm ~5 nm (Lin, IEDM 2013) 10

11 Dry+Digital Etch fin definition direction HSQ H c Fin H f L g direction SiO 2 Mo/W L g cap InGaAs channel HSQ Zhao, EDL 2014, Vardi, VLSI nm 8 nm InAlAs Cap recess Fin etch fin 100 nm BCl 3 /SiCl 4 /Ar RIE + 5 DE cycles : smooth, vertical sidewalls and high aspect ratio (>10) 11

12 Gate stack - Double gate FinFET W direction HSQ Top fin passivation HfO 2 H f H c InP stopper L g direction SiO 2 Mo/W InGaAs cap InGaAs channel L g HSQ Mo Doping InAlAs Contact deposition Cap recess Fin etch Gate stack HSQ stays on top of fins double gate FinFET Gate oxide 3 nm HfO 2 (vs. 2.3 nm in EDL2016) fin 12

13 Device cross section TEM of finished device in direction FIB cross section in L g direction 5 nm Fin pitch: 200 nm fins/device : 5 25 nm L g : 30 nm 5 µm Contact to channel separation set by DE : ~5 nm 13

14 Electrical characteristics: =5 nm, L g =50 nm I d [ A/ m] V GS =-0.2 to 0.5 V V GS =0.1 V Normalized by gate periphery V GS [V] I d [A/ m] 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 L g =50 nm =5 nm V DS =500 mv S sat =100 mv/dec S lin =73 mv/dec V GS [V] 50 mv [ S/ m] Well behaved devices with =5 nm V DS =0.5 V L g =50 nm =5 nm,max =600 µs/µm V GS [V] 14

15 On/Off performance: fin width scaling S sat [mv/dec] V DS = 0.5 V L g =40 60 nm [ms/ m] 2.0 V DS = 0.5 V L g =40 60 nm : S sat : 15

16 To improve Off performance: remove δ-doping Gen. #1 Gen. #2 δ doped SiO 2 Mo cap InGaAs Mo HSQ Gen. #2 Undoped SiO 2 Mo cap InGaAs Mo HSQ InAlAs Doping fin Extrinsic area δ doping R sd Dry gate recess allows to remove δ doping Impact on the intrinsic fin transport 16

17 W F =5 nm FinFET: Electrical characteristics: δ-doped vs. undoped I d [ A/ m] V GS =-0.2 to 0.5 V V GS =0.1 V Normalized by gate periphery V GS [V] I d [A/ m] 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 Undoped fins: L g =50 nm =5 nm V DS =500 mv S sat =100 mv/dec S lin =73 mv/dec S sat =75 mv/dec S lin =65 mv/dec V GS [V] 50 mv [ S/ m] better OFF performance Undoped Similar ON performance V DS =0.5 V L g =50 nm =5 nm,max =600 µs/µm,max =500 µs/µm doped undoped V GS [V] 17

18 Electrical characteristics: δ-doped vs. undoped S sat [mv/dec] 180 Undoped -doped L g =40 60 nm [ms/ m] Undoped -doped V DS = 0.5 V L g =40 60 nm Undoped fin: improved electrostatics For <20 nm undoped fin ON performance also better 18

19 Electrical characteristics: V T rolloff Undoped δ doped V T,lin [V] W F L g V T,lin [V] =5 nm =9 =13 =17 =21 =25 W F L g Undoped fins smaller variation of V T with W F Improved V T rolloff 19

20 normalized by gate periphery Benchmarking H c H c [ms/ m] Undoped -doped Si FinFETs InGaAs FinFETs Systematic degradation for < 15 nm for both δ doped and undoped structures No improvement from increased #DE cycles Higher EOT lower w.r.t. to Gen. 1 20

21 H c H c [ms/ m] normalized by gate periphery Undoped -doped Si FinFETs Benchmarking InGaAs FinFETs / [ms/ m] Record with good electrical performance Approaching Si FinFETs even at V DD =0.5 V Record AR= Target: W F =5 nm Si FinFETs (V DD =0.8 V) 4.3 Undoped -doped InGaAs FinFETs

22 Long-channel Mobility vs. Capacitance 1GHz δ doped undoped =25 nm =9 nm Strong µ degradation as < 10 nm µ independent of n l 22

23 Simulations charge distribution =25 nm undoped ON state: n l =3x10 7 cm 1 δ doped y Undoped fin: better use of sidewalls δ doped fin: conduction close to lower facet of channel 23

24 Simulations charge distribution =25 nm ON state: n l =3x10 7 cm 1 undoped undoped =9 nm δ doped δ doped y Narrow fin: volume inversion in both δ doped and undoped fins 24

25 undoped Simulations capacitance =25 nm ON state: n l =3x10 7 cm 1 (V GT ~0.4V) undoped undoped =9 nm undoped δ doped Simulation δ doped δ doped δ doped Simulation E s (y) Simulation y Simulation Reasonable agreement between measurement and simulations extract n l E s relation 25

26 Simulations Mobility vs. Field δ doped undoped Body conductance δ doped undoped =25 nm =25 nm =9 nm =9 nm At similar n l : Wide fin: E S (δ doped) < E S (undoped) Narrow fin: E S (δ doped) ~ E S (undoped) 26

27 Long-channel Mobility vs n l = 3x10 7 cm 1 V GT ~ 0.4 V 1500 n l = 3x10 7 cm 1 V GT ~ 0.4 V [cm 2 /Vsec] δ doped -doped [cm 2 /Vsec] Undoped Undoped Large over drive: µ(δ doped) ~ µ(undoped) Strong µ degradation as < 10 nm µ saturate 27

28 Conclusions Self-aligned gate-last InGaAs FinFET: Self-aligned gate and contact trough precision RIE and digital etch Record AR=10 Record =5 nm InGaAs FinFET with good electrical performance Performance enhancement in narrow fins via δ-doping removal Thank you! 28