High aspect-ratio InGaAs FinFETs with sub-20 nm fin width

Transcription

1 High aspect-rati InGaAs FinFETs with sub-2 nm fin width Aln Vardi, Jianqiang Lin, Wenjie Lu, Xin Zha and Jesús A. del Alam Micrsystems Technlgy Labratries, MIT June 15, 216 Spnsrs: DTRA (HDTRA ), NSF E3S STC (grant #939514) Lam Research

2 Outline Mtivatin Prcess technlgy Electrical characteristics Late news Cnclusins 2

3 InGaAs planar Quantum-Well MOSFETs MIT MOSFETs del Alam, J-EDS 216 Superir electrn transprt prperties in InGaAs InGaAs planar MOSFET perfrmance exceeds that f High Electrn Mbility Transistrs (HEMT) 3

4 InGaAs planar Quantum-Well MOSFETs - shrt-channel effects S min (mv/dec) nm t c =12 nm t c V ds =.5 V L g (µm) Lin, IEDM 214 Shrt-channel effects limit scaling t L g ~4 nm 3D transistrs required fr further scaling 4

5 FinFETs Intel Si Trigate MOSFETs FinFETs are use in mdern state-f-the-art technlgies Gd balance f SCE and high ON current per ftprint 5

6 InGaAs FinFETs ~3 nm ~5 nm Thathachary, VLSI 215 Waldrn, VLSI 214 ~5 nm Radsavljevic,IEDM 211 Kim, IEDM 213 Kim, TED 214 Demnstratins t date: 25 nm, AR c 1 6

7 Gal: Sub-2 nm Self-aligned III-V FinFETs High -K HSQ SiO 2 W/M cap channel L g AR c = H c / AR f = H f / H c InAlAs H f Deeply scaled fin width, gate length and gate xide High channel t fin width aspect rati (AR c ) Self-aligned cntacts CMOS-cmpatible prcesses and materials in frntend 7

8 Fin definitin: Dry etch + Digital etch 25 nm 17 nm 1 nm BCl 3 /SiCl 4 /Ar RIE f InGaAs nanstructures with smth, vertical sidewalls and high aspect rati (>1) Digital etch (DE): self-limiting O 2 plasma xidatin + H 2 SO 4 xide remval 3 nm 8 nm 8

9 Device fabricatin 3 nm In.53 Ga.47 As, Si dped 3e19 cm -3 4 nm InP stpper 4 nm In.53 Ga.47 As, undped 5 nm In.52 Al.48 As Si δ-dping: 4e12 cm -2 In.52 Al.48 As buffer Highly dped cap 4 nm thick channel layer Delta dping underneath InP semi insulating substrate 9

10 Device fabricatin Sputtered W/M cntact L g directin directin SiO 2 CVD SiO 2 hard mask W/M cap channel InAlAs 1

11 Device fabricatin L g directin directin Sputtered W/M cntact CVD SiO SiO 2 hard mask 2 35 nm W/M Lg Gate lithgraphy Gate recess (Dry): cap channel SiO SiO 2 2 /W/M Active area definitin W/M InAlAs 11

12 Device fabricatin L g directin SiO 2 W/M cap channel Lg InAlAs directin SiO 2 W/M 35 nm Sputtered W/M cntact CVD SiO 2 hard mask Gate lithgraphy Gate recess (Dry): SiO 2 /W/M Active area definitin Gate recess (Wet): Cap etch L g 6 nm SiO 2 W/M InGaAs InP 2 nm 12

13 Device fabricatin HSQ H f H c 1 nm Sputtered M cntact CVD SiO 2 hard mask Gate lithgraphy Gate recess (Dry): SiO 2 /W/M Active area definitin Gate recess (Wet): Cap etch Fin Lithgraphy Fin etch 13

14 Device fabricatin HSQ High-k/M H f H c HSQ 1 nm M 2 nm Sputtered W/M cntact CVD SiO 2 hard mask Gate lithgraphy Gate recess (Dry): SiO 2 /W/M Active area definitin Gate recess (Wet): Cap etch Fin lithgraphy Fin etch Digital etching ALD gate dielectric depsitin M gate sputtering Duble gate FinFET Al 2 O 3 /HfO 2, EOT = 1 nm 14

15 Device fabricatin Via SiO 2 Fin pitch 2 nm 1-5 fins/device Gate hat Sputtered W/M cntact CVD SiO 2 hard mask Gate lithgraphy Gate recess (Dry): SiO 2 /W/M Active area definitin Gate recess (Wet): Cap etch Fin Lithgraphy Fin etch Digital etching ALD gate dielectric depsitin M gate sputtering Gate head pht and pattern ILD1 depsitin Via pening Pad frmatin 15

16 Lng channel characteristics, =22 nm, L g =2 μm 25 2 Al 2 O 3 /HfO 2 EOT = 1 nm V GS =.75 V 1E-4 1E-5 1E-6 V DS =5 mv 5 mv I d [µa/µm] V I d [A/µm] 1E-7 1E-8 S lin =68 mv/dec 5 V.25 V V DS [V] 1E-9 1E-1 DIBL~ V GS [V] S lin =68 mv/dec Negligible DIBL Gd electrstatic cntrl ver dry etched sidewalls 16

17 Shrt channel characteristics, =22 nm, L g =3 nm 12 V GS =.75V 1 16 H c I d [µa/µm] AR c ~ V DS [V] -.25 Current nrmalized by 2xH c g m,max = 1.4 ms/µm at V DS =.5 V R n =17 Ω µm -.5 I d [µa/µm] I d [A/µm] E-3 1E-4 1E-5 1E-6 1E-7 V DS =5mV =22 nm L g =3 nm V GS [V] V DS =5 mv DIBL=22 mv/v S=14 mv/dec 1E V GS [V] 5 mv =22 nm L g =3 nm g m [µs/µm]

18 Mst aggressively scaled device, =7 nm, L g =2 nm I d [µa/µm] 4 V GS =.75 V V DS [V] I d [A/µm] 1E-5 1E-6 1E-7 1E-8 1E-9 =7 nm L g =2 nm S=12 mv/dec DIBL~15 V DS =5 mv 1E V GS [V] 5 mv AR c ~6 Pr drive current Increased line edge rughness fr <1 nm 18

19 L g and scaling g m [µs/µm] g m,max at V DS =.5 V =22 nm =17 nm =12 nm =7 nm L g [nm] L g g m g m 19

20 g m [µs/µm] g m,max at V DS =.5 V =22 nm =17 nm =12 nm =7 nm L g [nm] L g g m g m S sat [mv/dec] L g and scaling S sat at V DS =.5 V 2 15 =22 nm =17 nm =12 nm =7 nm L g [nm] L nset f SCE 2

21 g m [µs/µm] g m,max at v DS =.5 V =22 nm =17 nm =12 nm =7 nm L g [nm] L g g m g m S min [mv/dec] L g and scaling S sat at V DS =.5 V 2 15 =22 nm =17 nm =12 nm =7 nm L g [nm] L nset f SCE I n [µa/µm] I n at I ff =1 na/μm I ff =1 na/µm c c c c =22 nm =17 nm =12 nm =7 nm L g [nm] L max I n c c 21

22 ON resistance scaling R n [Ω-µm] R n 35 =7 nm L g [nm] Fr all, R sd =1 Ω µm Extremely lw series resistance due t cntact first and self-aligned apprach 22

23 .8 V T rllff.6.4 V T [V] =7 nm =12 nm =17 nm =22 nm L g [nm] V T delta dping, quantizatin V T rllff line edge rughness? A. Vardi, IEDM

24 g m [ms/µm] Benchmark Physical g m : nrmalized by gate periphery Si FinFETs InGaAs FinFETs [nm] g m f Si ~ g m f III-V III-V FinFET AR c H c H C W F 24

25 g m [ms/µm] Benchmark Physical g m : nrmalized by gate periphery Si FinFETs MIT InGaAs FinFETs InGaAs FinFETs [nm] Our results: AR c >1 fr the first time in III-V Sub-2 nm g m 1.18 H c H C W F 25

26 g m [ms/µm] Benchmark Physical g m : Ftprint g m : nrmalized by fin width Si FinFETs MIT InGaAs FinFETs InGaAs FinFETs g m / [ms/µm] [nm] Fr g m / : Si FinFETs InGaAs FinFETs [nm] Si >> III-V MIT FinFETs > all ther III-V gd use f sidewall cnductance Our results imprve the state-f-art

27 Pst-submissin results I d [µa/µm] V GS =-.5 t.75 ΔV GS =.25 V I [A/µm] I d V DS =5 mv 5 mv S=1 mv/dec DIBL=9 mv/v I g V DS [V] =7 nm L g =3 nm EOT=.6 nm (HfO 2 ) g m [µs/µm] V GS [V] g m max =.9 ms/μm V DS =5 mv 5 mv V GS [V] 27

28 Benchmark with latest results g m [ms/µm] Physical g m : Ftprint g m : Si FinFETs [nm] 1 InGaAs FinFETs g m / [ms/µm] Si FinFETs EOT=1 nm (HfO 2 /Al 2 O 3 ) EOT=.6 nm (HfO 2 ) InGaAs FinFETs [nm] New recrd results fr sub-1 nm InGaAs FinFETs

29 Cnclusins Nvel self-aligned gate-last FinFET: Self-aligned gate t cntact metals CMOS prcess cmpatibility Sub-1 nm fin width AR c >1 fr the first time in III-V Duble-gate FinFET Outstanding perfrmance and shrt-channel effects in devices with L g =3 nm and =22 nm Demnstrated subthreshld swing f 68 mv/dec in lng channel devices 29

30 Thank yu! 3