Lecture 02 CSE 40547/60547 Computing at the Nanoscale


 Garry Jackson
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1 PN Junctin Ntes: Lecture 02 CSE 40547/60547 Cmputing at the Nanscale Letʼs start with a (very) shrt review f semicnducting materials:  Ntype material: Obtained by adding impurity with 5 valence elements t a valence 4 semicnductr This will increase the amunt f negative charge carriers  Ptype material: Obtained by adding impurity t increase the number f psitive charge carriers Accepts nly weakly bnded, uter electrns frm ther semicnductr atms Semicnductr atms that lse electrns are hles Purpse f ptype dping is t create an abundance f hles Brn r aluminum substituted int a silicn crystal lattice Result: 1 electrn missing frm 1 f 4 cvalent bnds Dpant can accept electrn frm neighbring atm t cmplete the 4 th  Bringing PN type material tgether creates a PN junctin and dide Picture: (1), (2) tw dide symbls, (3) dide crsssectin, (4) Lewis structure  Bringing P, Ntype material tgether causes a large cncentratin at the gradient bundary Thereʼs a higher electrn cncentratin in N material, lwer electrn cncentratin in P material Gradient causes: Electrns t diffuse frm N P Hles t diffuse frm P N When a hle leaves the P material, it leaves behind an immbile acceptr in (with a negative charge) Therefre, a negative charge will exist in the P material near the vicinity f the PNbundary Similarly, psitive charge builds up n the N side as a diffusing electrn leaves a psitive charge behind Picture: PNjunctin with depletin regin
2  At the depletin regin, there is an electric field acrss the bundary directed frm N P Picture: Depletin regin; field will cunteract diffusin, and eventually there is 0 net current flw Therefre, under 0 bias, a vltage φ 0 exists which serves as a builtin ptential.  If we raise the ptential f the P regin with respect t the N regin, we lwer the ptential barrier I.e. given a frward vltage V d applied t the junctin The flw f mbile barriers acrss the junctin increases as diffusin current is dminated by drift current The net result is current flwing in the dide frm P N in this frward biased mde  In reverse bias mde, the depletin regin increases, and current flw is shut ff Dides fr Blean Lgic: Questins t cnsider: (1) Hw can we make lgic gates frm dides? (2) Are dides a gd switch fr making lgic gates? (Why r why nt?) Answer t Questin (1): Picture: (a) dide based OR gate, (b) dide based AND gate  OR gate peratin: If 1 input (A r B) is high, current flws thrugh the assciated, (frward biased) dide and brings the utput nde up.  AND gate peratin: If 1 input (A r B) is grunded, current flws thrugh the dide and utput X is at a lw vltage (assumes that dides in the abve picture are frward biased) The nly way t bring / keep utput X high is fr bth inputs t be high (i.e. the dides need t be reverse biased)  Freshadwing: What if I tld yu, that yu culd build a dide in an area thatʼs apprximately 25 nm 2? Keep in mind, that the minimum feature size (which represents just 1 part f 1 device) fr the current technlgy nde is ~ 16 nm. This is an appealing thught, but dides have their issues i.e. hw is gain achieved?
3 Picture: Experimental results f didebased, OR gate made frm nanwires Example setup:  Fr bth AND, OR gates, letʼs assume V high = 5V 1, V lw = 0V  Als, (fr nw) weʼll assume that dides dnʼt intrduce any errrs r lses int circuits  In actuality, this is nt really the case a silicnbased dide wuld have a drp f ~0.7V while cnducting  Maybe we culd vercme this prblem by saying: If vltage is >> 3.5V, we have a lgic 1 If vltage is << 1.5 V, we have a lgic 0 Example:  Hw wuld we use dides t implement the lgic functin: AB + CD Picture: (a) AB+CD based n dide lgic; (b) vltage divider Example discussin:  If all inputs are lgic 0 (a lw vltage) the utput will be held at lgic 0.  If bth inputs t ne f the AND gates are a lgic 1, what will the utput be? Dide in OR gate will becme frward biased fr the AND gate where bth inputs are at a high vltage Current flws thrugh the AND gate resistr and the OR gate dide Current flws thrugh the OR gate resistr  If all resistrs are the same value, we have a vltage divider and equally share a (5V) supply  After the OR gate dide inserts its lss, the utput vltage may be n the rder f ~2.1V 2.2 V Questin:  What lgic state is represented by 2.1V? 1 In reality, mre like 0.9V, 1V nw, but 5V is fine fr illustrative purpses.
4 Take Aways:  Fr dide lgic, itʼs difficult t create cascades f multiple lgic levels (The vltage drps add up)  This leads us t 3 terminal devices  Ging back t the nanwire example: Itʼs great t have junctins that are 10s f nm 2 But, as seen abve, didebased lgic may be limited as an infrmatin prcessing technlgy Mrever, hw d yu d inversin? Fr a functinally cmplete lgic set, need AND, OR, + NOT.  Can engineering gain, inversin int nanwirebased circuits (as yu will see later), but verhead strips away ptential density and perfrmance gains Digressin: S, ideally, what features shuld a device have it is t be used t implement a digital lgic system? Cnsider 5 tenets f digital lgic: 1. a device shuld have nnlinear respnse characteristics 2. a device shuld enable a functinally cmplete lgic set 3. pwer amplificatin (r gain) is needed 4. the utput f ne device must drive anther (i.e. with n state variable change) 5. dataflw directinality must be well defined Use nanmagnet lgic as an example Transistr Basics: Disclaimer: This discussin is by n means meant t replace an electrnics r VLSI design curse. Rather, it is just meant t briefly review/intrduce material frm these curses, and set the stage fr a discussin f radblcks t transistrbased scaling and cmputatin. Devices at a glance:  At the mst superficial level, transistrs can be thught f as a switch  If a vltage is applied t a gate (that is greater than sme threshld vltage V t ), a cnducting channel is frmed between drain and surce  If the vltage difference between drain and surce, than current flws between them The greater the vltage difference between gate and surce, the smaller the resistance f the channel and the greater the current  If the gate vltage is lwer than the threshld, n channel exists and the switch is pen (Assuming an NMOS device, current is carried by electrns mving thrugh an Ntype channel between the transistrʼs surce and drain.)
5 Threshld Vltage:  Cnsider V gs = 0 the drain, surce, and bulk are all cnnected t grund  The drain and surce are effectively cnnected by backtback PN junctins (substratesurce and substratedrain)  With the cnditins abve, bth junctins have 0 bias and the device can be cnsidered ff (i.e. there is a high resistance between surce and drain indicative f an pen switch) See Slides Nw, assume that a psitive vltage is applied t the gate (with respect t the surce) The gate and substrate frm plates f a capacitr where the gate xide frms the dielectric A psitive gate vltage causes +/ charge t accumulate n gate/substrate side respectively See Slide 6  When the gate vltage becmes sufficiently high, the ptential at the silicn surface reaches a critical value, and the semicnductr surface inverts t Ntype (strng inversin) Further increases t the gate vltage prduce n mre changes in the depletin layer width, but results in a thin inversin layer under the xide Drawn int inversin layer frm heavily dped N surce regin Ntype channel frmed between surce and drain, mdulated by V gs Value f V gs where strng inversin ccurs = threshld vltage V t 5 See Slide 6 Resistive / Linear Operatin:  Nw, assume V gs > V t and a small vltage is applied between drain and surce  Vltage difference causes current i D t flw frm drain t surce  At a pint x alng the channel, the vltage V(x) at gatetchannel vltage at that pint = V gs V(x)  If vltage exceeds V t at all pints alng the channel, current can be calculated See Slides 913 Saturatin Regin:  As the value f the drainsurce vltage is further increased, the assumptin that the channel vltage is greater than the threshld vltage at all pints ceases t hld Occurs if V gs V(x) < V t  Here, the cnducting channel is pinched ff  Cnditins must be met at the drain regin therefre V gs V ds <= V t E.g. if V gs = 5V, V ds = 5V, and V t = 0.7V 5V 5V < 0.7V  Nw, the transistr is in the saturatin regin, and current is n lnger a functin f V ds (it acts as a current surce) See Slides 1416
6 Hw scaling impacts transistr parameters, perfrmance: See Slide 17  Letʼs talk mre abut the vltage scaling factr U. Assumes all vltages scale by the same factr U Prduct cmpatibility might be ne reasn A bit mre n 3 mdels in the chart: Full scaling:  Vltages and dimensins are reduced by the same factr S; leads t: Greater density Better perfrmance (intrinsic delay gets better) Pwer cnsumptin reduced t (and chiplevel pwer density stays cnstant as mre devices placed in same area)  Fr a lng time, this mdel held  Cnsider impact n smething like Pwer: P = I sat x V I sat scales as 1/S V scales as 1/S Therefre P scales as 1/S 2 seemingly great! What abut t x? Affects ther parameters which influence delay and pwer What if it desnʼt scale in lckstep (as it must) See Slide 18 fr t x scaling trends Fixed Vltage Scaling:  T keep new parts cmpatible with existing cmpnents, V cannt be scaled arbitrarily  Can be hard, expensive t supprt multiple supplies (e.g. 5V, 3V)  What if vltage des nt scale? Lk at example: P density P density = P / Area Scales as 1 / (1/S 2 ) increases as S 2! General Scaling:  Supply vltage scales, but nt at the same rate as technlgy  Sme fundamental limits cme int play here Yu canʼt make V t arbitrarily lw as yuʼll see, yu culdnʼt turn the transistr ff There are intrinsic device vltages Material parameters canʼt be changed Need new materials
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