Modeling and Analysis of Total Leakage Currents in Nanoscale Double Gate Devices and Circuits

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1 Modeling and Analysis of Total Leakage Currents in Nanoscale Double Gate Devices and Circuits Saibal Mukhopadhyay 1, Keunwoo Kim, Ching-Te Chuang, and Kaushik Roy 1 1 Dept. of ECE, Purdue University, West Lafayette, IN; IBM T. J. Watson Research Center, Yorktown Heights, NY 1 <sm,kaushik>@ecn.purdue.edu; <kkim,ctchuang>@us.ibm.com ABSTRACT In this paper we model (numerically and analytically and analyze sub-threshold, gate-to-channel tunneling, and edge direct tunneling leakage in Double Gate (DG devices. We compare the leakage of different DG structures, namely, doped body symmetric device with polysilicon gates, intrinsic body symmetric device with metal gates and intrinsic body asymmetric device with different front and back gate material. It is observed that, use of (near-midgap metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG circuits. Categories & Subject Descriptor: B.6.3 [Logic Design]: Design Aids Estimation B.7. [Integrated Circuits]: Design Aids Estimation General Terms: Performance, Design, Theory. Keywords: Double-Gate devices, Gate leakage, subthreshold leakage, quantum effect, stacking effect, SRAM. 1. INTRODUCTION Due to excellent control of the short channel effect (SCE, higher ON current and better subthreshold slope, Double-Gate (DG devices are very promising for nano-scale circuit design [1]. Depending on the gate materials and body doping, primarily three types of DG device structures have been pr oposed (Table-I, namely, doped body symmetric device with poly gates (n+ poly for NMOS (; intrinsic body symmetric device with (near midgap metal gates (; intrinsic body asymmetric device with different front and back gate workfunctions (e.g. n+ poly/p+ poly, [1]. In this paper, we analyze total leakage current of, and devices. In particular: We have developed numerical and analytical models to estimate the subthreshold, gate-to-channel and edge direct tunneling (EDT leakage in, SymSG, and devices. We have compared the different leakage component, the total leakage and the sensitivity of the leakage components to device parameter variations in different DG devices. We have applied the models to analyze the effect of different device structure on the total leakage in DG circuits. Our analysis shows that, the device has lower subthreshold and gate leakage compared to the other two structures. Hence, the metal gate and intrinsic body structure is very efficient for lowpower circuit design in sub-5nm regime. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED 5, August 1, 5, San Diego, California, USA. Copyright 5 ACM /5/...$5.. Source. LEAKAGE CURRENTS IN DGMOS The major leakage mechanisms in DG devices are the subthreshold leakage and the gate leakage (gate-to-channel + edge direct tunneling (Fig. 1. We have compared the leakage currents of, and devices (L gate =3nm, L eff = nm, T si = 5nm, T ox =1nm, V DD =1V designed in MEDICI [] for equal ON current..1 Modeling of Quantum Confinement Considering the quantization of electron energy in the silicon body due to DG structure and band-bending (i.e. effect of electric field, the energy (E (j,i and the charge associated (Q (j,i with the j-th subband of the i-th valley (longitudinal or transverse is given by [3]: nind j ( h 3hqεoxE π ox 3 E( ji, == + j+ * mt * i si ε si m i Structural Quantization (1 Field Quantization * ηm E dikt F E( j, i Qinv = Q( j, i = q ln 1 exp + i j i j π h kt q where, m i * is the electron effective mass, η is the valley degeneracy, m di * is the density of effective mass, and nind ( /3 is a fitting factor. The oxide field at the front gate (E ox is given by [4] : ε E = Q + Q = Q + qn T ; ox ox inv b inv body si ( : ε E = Q ; and : ε E = Q + ε E ox ox inv ox ox inv si where, E is the built-in field due to workfunction asymmetry [4].. Modeling of Subthreshold Leakage The subthreshold current in a DG device is given by [5]: kt V V gs th qvds ( ( ( W I = C µ exp 1 exp sub g L q S kt q kt eff T ox Edge direct tunneling Gate-to-channel tunneling Front Gate Leff T si Back Gate Subthreshold leakage. where, C g is the effective gate capacitance and S is the subthreshold Drain VBET VBHT Gate SiO Body SiO VBET VBHT Gate Fig. 1: DG device structure and different leakage mechanisms. Table-I: Device Structure Gate Material Body Doping Vth Control Metal Intrinsic body Metal Workfunction N+ poly Doped ( Halo Body doping Front n+ poly Intrinsic body Workfunction difference Back p+ poly of front and back gates (3

2 V ox from quasi-bound V poly E C µ G Electron energy quantization in drain accumulation E C µ D V GD =1V from quasi-bound µ G Electron energy quantization in drain accumulation V GD =1V E C µ D E C E C µ D V GD =1V µ G Metal Gate n+ poly gate N+drain N+drain p+ poly gate N+drain Fig. : Edge direct tunneling current in the ON state (i.e. Vgd=1V n+ poly-n+ drain metal gate-n+ drain, and p+ poly-n+drain swing factor (estimated using [6]. Considering the short channel effect (SCE and the quantum mechanical ( effect, the V th of a short channel ultra-thin body DG device is given by [4-7]: Eg kt Nbody 1 Qb Qb th = + ln + Φ Gfs + ΦGbs q q ni 1+ r Cox Csi εsitt si oxf VDS εsitt si oxf Eg Eg kt Qinv ( EF = ln ε q q nt oxαleff εoxγl eff i si Effect V r r + + SCE Electron energy quantization in poly accumulation E C µ G V poly V GD =-1V n+ poly gate from quasi-bound where, r (=3T ox /(3T ox +T si is the gate-gate coupling factor..3 Modeling of Gate-to-Channel Leakage The gate-to-channel current is due to conduction band electron tunneling ( from the quasi-bound in the inverted channel in the ON state (V gs = V DD []. The tunneling current is given by: ref Igc = WL eff 1 atsi ln( Tsi T si Q( j, i f( j, i T( j, i (5 where, f (j,i (=E (j,i /h is the impact frequency of electron [9]. T (j,i (=T WKB T R is the transmission probability from (j,i state estimated using WKB method and depends on T ox and E ox as shown below [9]: eox = qφ cat EGox ( m ox 1 TWKB = exp ( γ ' γ + EG( ox sin γ ' 4hqE ox eox = qφan (6 γ = eox ( 1 eox EG( ox and γ ' = ( 1 eox EG( ox qφ = qφ E and qφ = qφ E qe T cat ox ( j, i cat ox ( j, i ox ox where, E G(ox and m ox are the band-gap and effective mass in oxide, and φ ox is the barrier height for. T R is the interface reflection coefficient [9]. The T si dependent empirical function in (5 is used to model the effect of silicon thickness on the gate current (T si Ref =5nm. j n+ drain i E E C µ D V φ EVB =Φ M -χ ox = =3.6eV E max =µ G E av V GD =-1V Metal Gate (4 T eff (E Tunneling from free E min =E C µ D n+ drain E C E max = µ G V GD =-1V E g =1.1eV E av p+poly gate.4 Modeling of Edge Direct Tunneling Leakage The Edge Direct Tunneling (EDT occurs through the gate and drain (or source extension region, both in the ON (V gs =V DD, V gd =V DD or and the OFF (V gs =, V gd =-V DD state. The E ox across the 1-D gate-sio -drain extension structure (Table-I depends on the voltage drop in poly gate (V poly and drain extension ( as [1] (Fig., 3: V V = V + E T + V (7 gd FB poly ox ox DE where, V FB is the workfunction difference between the gate and drain. In the ON state EDT is due to from the quasi-bound in the accumulated n+ drain extension region (Fig.. Solving ε ox E ox =Q s (assume only (1,1 state is occupied we obtain: E kt ε E π h E T eff (E VBET from free n+ drain E min =E C µ D Fig. 3: EDT in the OFF state (i.e. Vgd=-1V n+ poly-n+ drain metal gate-n+ drain, and p+ poly-n+drain F B 11 V = ln exp 1 + DE q q q m k T q ox ox * η d1 B where, E 11 ( E /3 ox is obtained from (1 (only field quantization. Using ( and considering poly-depletion (V poly =ε ox E ox /qε si N gate, E ox and the tunneling current is estimated using (7 and (5. The from the accumulated n+-poly gate to n+ drain ( OFF state is estimated similarly (Fig. 3a [1]. In the OFF state of the metal gate-n+ drain (or p+ poly-n+ drain, back gate in structure electrons from the free below the Fermi level in metal (or in the valence band of p+ poly, valence band electron tunneling VBET constitute EDT (Fig. 3b,c. Electron tunneling form the above the metal Fermi level (or from the conduction band in p+ poly is negligible due to the lack of electrons. The current density due to tunneling from free can be given by [11]: q Emax J Free = T ( E D( E ( f ( E µ G f ( E µ D E de (9 min valleys h where, D(E is the density of, f is the Fermi function, µ G and µ D are the gate and drain Fermi levels (µ G = µ D V gd, respectively. The tunneling probability for metal electron tunneling (or VBET in p+ poly gate is less than that in principally due to a higher barrier height (Fig. 3 & (6. Moreover, in case of the tunneling from metal gate or VBET from p+ poly, the effective tunneling ( 9

3 thickness (T eff is higher than T ox due to the drain depletion (Fig. 3b,c. The higher T eff reduces the tunneling current. To consider this effect, we model T eff as a function of as: T eff =T ox +θ ND DE, where θ NDE is a fitting factor. Using (1 we model EDT current as: Φ V E drain gd av 1 * ( + exp kt q E - E q m kt max min m I = WL VBET SDET ln 3 π h Φ E drain av (1 1 + exp kt q E = Φ or E ( p + poly; E = E ( n + drain; E = ( E + E max gate V min C av max min where, the transmission probability (T=T WKB T R is estimated at an average energy E av using T eff as the oxide thickness (using (5..5 Model Verification The analytical models to estimate the sub-band energy levels were verified against quantum mechanical solver SCHRED [1] for,, and devices (Fig. 5. The subthreshold current in different DG devices estimated using the models (3-(4 closely follows the MEDICI simulation results for different V ds, T ox, T si and L eff (Fig. 6, 9. To verify the proposed gate-to-channel current models, we developed numerical quantum mechanical simulator to estimate tunneling through the 1-D gate-sio Si-SiO -gate structure []. The developed simulator estimates the tunneling from the quasi-bound using Quantum Transmitting Boundary Method (QTBM, Fig. 4a [13]. The developed simulator is verified against the measurement and simulation results from []. The gate-to-channel current estimated using the proposed analytical models (in (5-(6 closely follows the QTBM based numerical simulation results for different V gs, T ox and T si (Fig. 6b, 1 To verify the proposed EDT models, we developed numerical simulator to solve the quantum transport problem in the 1-D gate- SiO -drain structure using Non-Equilibrium Green s Function (NEGF method (Fig. 4b [11]. Using NEGF we can simultaneously Gate Current Density [A/cm ] Edge Direct Tunneling Leakage [A] Simulation results from [] DG device (T si =5nm, T ox =1.5nm DG device (T si =5nm, T ox =1nm Ultra thin body device (Tsi=1nm, Tox=.5nm 1 5 Measured results from[] Discrete Points Results from [] Solid Lines QTBM based numerical results Inversion Charge Density [1/cm ] x EDT Leakage from n+poly gate to n+ drain Discrete Points Measurement result from [1] Solid Lines NEGF based numerical result T ox =1.47nm T ox =.4nm (d Electric Field [MV/cm] Fig. 4: Numerical simulators for gate leakage: gate-to-channel leakage, edge direct tunneling leakage, verification for the gate-to-channel leakage, (d verification for the EDT leakage. Subband Energy [mev] Discrete Points Numerical result (SCHRED Solid Lines Analytical Models nd valley (E (1, nd subband of 1 st valley (E (,1 1 st valley (E (1, Gate Voltage (V gs [V] Subband Energy [mev] Discrete Points Numerical result (SCHRED Solid Lines Analytical Model nd valley (E (1, nd subband of 1 st valley (E (,1 1 st valley (E (1, Gate Voltage (V [V] GS Fig. 5: Model verification for sub-band energies,,, and devices (Tsi=5nm,Tox-1nm Drain to Source Bias (Vds [V] Gate to Channel Current (µa/µm.5 Soild lines Analytical model Gate Voltage (V GS [V] Edge Direct Tunnelng Current (µa/µm s n+ poly structure metal gate structure p+poly structure Gate to Drain Voltage (Vgd [V] Fig. 6: Model verification for subthreshold leakage, gate-to-channel tunneling and Edge direct tunneling. 1

4 Gate Leakage (µa/mum Total Leakage (µa/mum n+ poly solve the tunneling from the quasi-bound (from n+ poly gate or n+ drain and free (from metal or p+ poly gate [1]. This is not possible by the methods developed to estimate gate-to-channel tunneling from quasi-bound [, 13]. We verified the developed simulator using the measurement results [1] for the tunneling from n+ poly to n+ drain structure (Fig. 4d. The EDT current estimated using the proposed analytical models closely follows the NEGF based simulation results for different V gd and T ox in both OFF state and ON state (Fig. 6c, COMPARISON OF DG DEVICES In this section, analytical models are used to compare the leakage currents of three DG devices designed for equal ON current. V th (V th : V gs at I ds =(1µm/L eff.1µa, subthreshold slope and DIBL values are: :-.V, 6mV/dec, 46mV/V; :-.35V, 6mV/dec, 17mV/V; and :-.3V, 64mV/dec, 3mV/V. 3.1 Comparison of Subthreshold Leakage For an equal ON current, and devices require a Gate to channel tunneling OFF state EDT 1 4 SiO Si N SiO 3 4 Si N SiO High K n+ poly Fig. : Comparison of gate leakage, and total leakage in DG devices Effective Channel Length (Leff [nm] Metal lower V th than devices due to: poly depletion; mobility degradation due to higher surface scattering as conduction in the and devices are closer to surface, and existence of only one conducting channel in. Due to the higher V th the subthreshold leakage in is significantly lower than that in (~X and (~1X devices (Fig. 6a 3. Comparison of Gate-to-Channel Leakage Due to the presence of bulk-charge, the oxide field (hence, band bending in device is higher than that in (( & Fig. 7 []. Moreover, due to the larger band bending (higher Eox, the sub-bands in are at a higher energy than the sub-bands in (see (1, Fig. 5. Electrons at higher energy levels (lower lifetime have a higher tunneling probability (see (6. In device the electric field at the front surface is higher due to the built-in electric field []. However, due to negligible field across the back oxide at inversion (Fig. 7c, the back gate has negligible gateto-channel leakage. Thus the has less gate to-channel leakage compared to (~3X and (~X (Fig. 7b, 1. Since only the front gate contributes to tunneling, has less current than. 3.3 Comparison of the EDT leakage At the ON state V ox in the metal gate n+drain (V FB =Φ drain - Φ G Eg/q> or p+-poly-n+drain (V FB E g /q>v DD is lower than that in the n+-poly-n+ drain (V FB structure (Fig.. Hence, the ON state EDT (I EDT-ON in metal-gate or p+-poly (negligible leakage gate is less than that in the n+-poly gate structure (Fig. 6c. Due to the higher barrier height and effective tunneling thickness (Fig. 3, the OFF state EDT (I EDT-OFF due to VBET from the p+ poly gate or due to electron tunneling from metal gate is lower than that due to from n+ poly gate (Fig. 6c. Hence, and have lower EDT leakage than. 3.4 Use of High-K Dielectric For the same electrical oxide thickness (EOT=ε ox /T ox, reduction in the gate-to-channel leakage in from (~1X or (~X is higher when high-k dielectric (, K~7 is used (Fig. a, 1. This is because of the fact that, with as the dielectric, due to a higher physical oxide thickness, tunneling is a stronger function of the electric field []. Moreover, with the relative increase in the barrier height for electron tunneling from metal (.76eV for, 3.76 for SiO assuming mid-gap metal from (.ev for Si3N4, 3.14 for SiO is higher (~5% compared to SiO (~1%.Hence, OFF state EDT leakage reduction Metal Oxide Thickness (Tox [nm] N+ poly Fig. 7: Gate-to-channel leakage in DG NMOS devices:, and Silicon Thickness (Tsi [nm] Fig. 9: Variation of the subthreshold current with Leff, Tox and Tsi. p+ poly 11

5 Stack Factor for Subthreshold Gate to Channel Current (µa/µm Gate to Channel Current (µa/µm SiO Oxide Thickness (Tox [nm] 1 1 SiO in the metal (or p+-poly gate from n+ poly gate is higher with Si3N4 (Fig. a, 11 Hence, is more effective in reducing gate leakage if high-k dielectric is used. For same EOT, effect of high-k (to the first-order on the Vth and subthreshold leakage is not high (see ( Comparison of the Total Leakage Considering ON and OFF, we define the total leakage as: I = I + I ( F & B + I + I ( F & B TOTAL sub EDT OFF gate gate GC EDT ON gate gate (11 OFF state ON state The total leakage in is less (reduction increases with compared to the and devices (Fig. b. 3.6 Effect of Parameter Variation Variation in Channel Length: Due to the higher sensitivity of the V th and subthreshold slope to the SCE (I sub is stronger function of V ds Fig. 6a, subthreshold current in is more sensitive to L variation compared to and devices (Fig. 9a. Variation in Oxide Thickness: In and devices increasing T ox increases subthreshold current due to higher SCE. However, in devices due to the presence of bulk charge, a higher T ox increases Q b /C ox which masks the effect of higher SCE. Hence, V th increases resulting in a lower subthreshold current (Fig. 9b. A higher T ox reduces both the gate-to-channel and the overlap tunneling (Fig. 1a, 11 in the three DG devices. Variation in Silicon Thickness: A higher T si in and devices increases the SCE and reduces the V th shift due to quantum confinement, thereby increasing the subthreshold leakage (Fig. 9c. However, in devices increasing T si also increases the bulk charge resulting in a higher V th and lower subthreshold current (Fig. 9c. A higher T si increases the Q inv in and Si N Silicon Thickness (Tsi [nm] Fig. 1: Gate-to-channel current with Tox and, Tsi Effective Channel Length (L [nm] eff Stack Factor for Total Leakage 1..6 Overlap Tunnelng Current (µa/µm n+ poly gate (lower effect which tends to increase the gate-tochannel current. However, with higher T si the electron distribution shifts away from the surface, thereby lowering the tunneling probability in []. For a higher T si reduces the built-in electric field. Due to these opposing effects gate-to-channel leakage in and is not very sensitive to T si variation (Fig. 1b. In devices, a higher T si reduces the inversion charge (higher Vt and shifts the electron distribution away from the surface resulting in a reduction of the gate-to-channel leakage (Fig. 1b. From the above discussion, we can observe that leakage in device has a weaker sensitivity to parameter variation. 4. LEAKAGE IN DG CIRCUITS In this section we analyze the total leakage current in logic (transistor stack and SRAM circuits using the analytical models. 4.1 Leakage in DG Logic Circuits Stacking Effect In a stack of two DG NMOS transistor the stack-factor (SF = leakage of -T stack / leakage of single device [14] is given by: I I + I exp( q( 1+ η V S kt SF = = I I + I V M SiO 1 6 metal gate p+ poly gate 1 s Oxide Thickness (Tox [nm] 1 n+ poly gate SiO 1 ON state EDT at V gd =V DD (µa/µm V M > metal gate 1 V M = V M =V DD -V th 1 Subthreshold Solid Lines Analytical Gate-to-channel models EDT Oxide Thickness (Tox [nm] Fig. 11: Variation of EDT with Tox in : OFF state, and ON state.4. Solid lines SiO Broken lines Si N Effective Channel Length (L [nm] eff Fig. 13: Stacking effect for subthreshold, and total leakage. STACK EDT OFF sub DIBL M VDD SINGLE EDT OFF sub V ( S S + η V ε T T = ; η = + η S + η S αε L th VDD DIBL DD si si ox DIBL ( 1 V M > BL WL DIBL DIBL VDD ox eff (1 where, I sub is the subthreshold leakage of a NMOS device V ds =V DD, V M is the voltage at the intermediate node (Fig. 1, V th is V th value at V ds =, S VDD and S are the subthreshold swing factor at V ds =V DD and V ds =, respectively. The negative V gs operation of the top transistor (V M > reduces the subthreshold current in the - Transistor stack [14]. Hence, the stack factor for subthreshold (neglecting I EDT-OFF in (1 is less than 1 for all devices (Fig. 13. However, due to the lower SCE (lower η DIBL and S VDD -S stacking effect is minimum if is used (maximum if is used (Fig. 13a. Moreover, with SiO as the dielectric, the stacking effect on the total leakage is negligible due to the high gate leakage. The stacking effect is more significant with high-k dielectric (low EDT, Fig. 13b. In a stack of -NMOS devices, the gate leakage is maximum with input 1 (bottom and top NMOS contributes to the leakage, Fig. 1. The gate leakage with input is higher than that with 1 due to the higher EDT of the top transistor with ( V gd =V DD for top transistor with while V gd =V DD -V th for 1 V M = Subthreshold Gate-to-channel P L z N L 1 V M =V DD -V th EDT AX L 1 Subthreshold Gate-to-channel EDT P R N R AX R BLB Fig.1: Leakage in DG circuits: NMOS stack, and SRAM cell. 1

6 Subthreshold Leakage [na/µm] Total Leakage [na/µm] I sub /I EDT OFF INPUT="" INPUT="1" INPUT="1".3..1 MG Sym Asym the bottom transistor with 1 (Fig. 1a, 13a [15]. Due to the stacking effect minimum subthreshold leakage occurs with input (Fig. 14b [14, 15]. Due to higher EDT, 1 is the minimum leakage vector with SiO as the dielectric (Fig. 14c. However, if is used the gate leakage becomes comparable to (or less than the subthreshold leakage and is the minimum leakage vector (Fig. 14d. The leakage of the stack of devices is significantly less than that of the and the devices. However, due to the lower stacking effect, the leakage reduction with is minimum for (Fig. 14d. 4.. DG SRAM Cell Statistical Analysis The total leakage of NMOS transistors in an SRAM cell is given by: I = ( W + W I + W I + ( 6W + W I + 4W I N Cell npd nax sub npd gc nax npd EDT OFF npd EDT ON (13 subthreshold Dielectric SiO INPUT="" INPUT="1" INPUT="1" Gate Leakage [na/µm] where, W npd and W nax are widths of the pull-down and access transistors (Fig. 1b. Use of the devices significantly reduces the cell leakage (Fig. 15. The distribution of the cell leakage due to parametric variation is an important parameter for SRAM design. Along with the L eff, T si and T ox variations, the effect of V th variation (δv th due to Random Dopant Fluctuations (RDF Total Leakage [na/µm] INPUT="" INPUT="1" INPUT="1" 1 5 I sub /I EDT OFF 15 MG Sym Asym gate Gate leakage with SiO INPUT="" INPUT="1" INPUT="1" High K Dielectric Fig. 14: Input vector dependence of leakage in a -Transistor stack Subthreshold, gate leakage, total leakage with SiO and (d. Cell Leakage Current(nA/mum SiO W npd =1nm W nax = 6nm Subthreshold Gate Leakage Gate Leakage Cell Leakage Current (NMOS [na/mum] X 15X.3X.7X SiO High K Si N 3 4 Fig. 15: Leakage (NMOS in SRAM Cell: leakage components, and total leakage. Spread in Leakage (σ/µ [%] Solid lines represent T si variations Broken lines represent L variations eff results with Si N 3 4 STD in Leakage [na/µm] (d Results with in devices (as body is doped need to be considered for the statistical analysis of the cell leakage [1]. Using [3], the standard deviation of δv th due to RDF (assumed to be Gaussian random variable, mean= can be given by: σ Vt =(q/c g (N Body T si /WL eff. Due to the intrinsic body, the RDF induced variations are not present in the and devices. Due to the lower SCE, the sensitivity (standard deviation/mean of the cell leakage to T si and L eff variation reduces when the devices are used (Fig. 16a. Considering simultaneous variation of all parameters, the standard deviation of the leakage of the cell designed with device is significantly higher than that with devices (Fig. 16b. This is attributed to the lower SCE and elimination of RDF in. Although the sensitivity of the and devices are comparable, the leakage is larger with the devices as shown in Fig CONCLUSIONS In this paper, we have developed analytical and numerical models to analyze the total leakage in DG devices and circuits. Our analysis shows that, use of the metal gate intrinsic body devices can significantly reduce the subthreshold and gate leakage in DG circuits. Hence, the metal gate intrinsic body DG devices are promising for low-power logic and memory circuits in nano-meter regime Acknowledgement: Saibal Mukhopadhyay and Kaushik Roy would like to thank Semiconductor Research Corporation (#17.1 and IBM PhD Fellowship program for their support. Keunwoo Kim and Ching-Te Chuang are partially supported by the DARPA contract NBCH3394 for this work. REFERENCES [1] E. Nowak, et. al, Turning silicon on its edge, IEEE Circuits & Device Magazine, Jan/Feb 4, pp [] MEDICI: -D device simulation program, Synopsys Inc. [3] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, New York: Cambridge Univ. Press, 199. [4] Y. Taur, Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs, IEEE TED, vol. 4, Dec. 1, pp [5] G. Baccarani, A Compact Double-Gate MOSFET Model Comprising Quantum-Mechanical and Nonstatic Effects, IEEE TED, vol. 49, Aug. 1999, pp [6] Q. Chen, Nanoscale metal-oxide-semiconductor field-effect transistor: scaling limits and opportunities, Nanotechology, vol. 15, Oct. 4, pp-s545-s555. [7] K. Kim, et. al., Process/physics-based threshold voltage model for nano-scaled double-gate devices, International Journal of Electronics, vol. 91, Mar. 4, pp [] L. Chang, et. al., Direct tunneling gate leakage current in double-gate and ultrathin body MOSFETs, IEEE TED, vol. 49, Dec., pp [9] L. F. Register, et. al., Analytic model for direct tunneling current in polycrystalline silicon-gate meta-oxide-semiconductor devices, Applied Physics Letter, vol. 74, Jan. 1999, pp [1] K. Yang, et.al, Characterization and modeling of edge direct tunneling (EDT leakage in ultrathin gate oxide MOSFETs,, IEEE TED, vol. 4, June. 1, pp [11] S. Datta, Electronic Transport in Mesoscopic Systems, Cambridge Unversity Press, Cambridge, [1] SCHRED [Online]. Available: [13] S. Mudanai, et.al, Modeling of direct tunneling current through gate dielectric stacks, IEEE TED, vol. 47, Oct., pp [14] S. Narendra, et.al. Scaling of stack effect and its application for leakage reduction, ISLPED, 1, pp [15] S. Mukhopadhyay, et.al, Accurate modeling of transistor stacks to effectively reduce total standby leakage in nano-scale CMOS circuits, Symp. of VLSI Circuits, 3, pp Spread in Paramters (σ/µ [%] Spread in Paramters (σ/µ [%] Fig. 16: Statistical analysis of cell leakage: L eff and T si, and simultaneous variation of all parameters (including RDF 13