III-V FET Channel Designs for High Current Densities and Thin Inversion Layers

Transcription

1 IEEE Device Research Cnference, June -3, Ntre Dae, Indiana III-V FET Channel Designs fr High Current Densities and Thin Inversin Layers Mark Rdwell University f Califrnia, Santa Barbara Cauthrs: W. Frensley: University f Texas, Dallas S. Steiger, S. Lee, Y. Tan, G. Hegde, G. Kliek Netwrk fr Cputatinal Nantechnlgy, Purdue University E. Chagarv, L. Wang, P. Asbeck, A. Kuel, University f Califrnia, San Dieg T. Bykin University f Alabaa, Huntsville J. N. Schulan The Aerspace Crpratin, El Segund, CA. Acknwledgeents: Herb Kreer (UCSB), Bbby Brar (Teledyne) Art Gssard (UCSB), Jhn Albrecht (DARPA) rdwell@ece.ucsb.edu , fax

2 Thin, high current density III-V FET channels InGaAs, InAs FETs THz & VLSI need high current lw * high velcities FET scaling fr speed requires increased charge density lw * lw charge density Density f states bttleneck (Sln & Laux IEDM ) Fr <.6 n EOT, silicn beats III-Vs Open the bttle! lw transprt ass high v carrier ultiple valleys r anistrpic valleys high DOS Use the L valleys.

3 Siple FET Scaling Gal: duble transistr bandwidth when used in any circuit reduce : all capacitances and all transprt delays keep cnstant all resistances, vltages, currents gate-surce, gate-drain fringing capacitances:.5-.5 ff/ C / W gd g ~ ust increase gate capacitance/area g / Wg ~ v( Cgs / LgWg ) C gs / W C gs / W, f g g ( C / W L ) L ~ gs g g g ust reduce gate length Tduble speed,we ust duble ( g / Wg ), ( ID / Wg ), ( Cgs / LgWg ), ns.

4 FET Scaling Laws L G Changes required t duble device / circuit bandwidth. laws in cnstant-vltage liit: FET paraeter change gate length decrease : current density (A/), g (S/) increase : channel DEG electrn density increase : electrn ass in transprt directin cnstant gate-channel capacitance density increase : dielectric equivalent thickness decrease : channel thickness decrease : channel density f states increase : surce & drain cntact resistivities decrease 4: Current densities shuld duble Charge densities ust duble gate widthw G

5 Seicnductr Capacitances Must Als Scale ( V V ) th gs c x (unidirectinal tin) cdepth / T inversin ( E f Ewell) / q c ds q g * / channel charge qn s c ds ( V f V well ) q( E f E well ) ( g * / ) Inversin thickness &density f states ust als bthscale.

6 Calculating Current: Ballistic Liit Natri Channel Feri vltage vltage applied tc deterines Feri velcity v f thrugh E ds f qv f * v f / ean electrn velcity v (4/3 )v f Channel charge : s c ds ds equiv V V V V f c c c equiv c c ds gs th c ds q g* / c, ds g ( */ ), where g is the# f band inia J / 3/ A g ( * / ) Vgs V th 84 3/ ( cds, / cx) g ( * / ) V D we get highest current with high r lw ass?

7 Drive current versus ass, # valleys, and EOT nralized drive current K J K A 84 V V InGaAs MOSFETs: superir I d t Si at large EOT. InGaAs MOSFETs: inferir I d t Si at sall EOT. gs V th 3/ InGaAs <--> InP, where EOT includes the wavefunctin depth ter (ean wavefunctin depth* SiO / seicnductr ) K * / g * ( c / c ) g ( / ) 3/ ds,.4 n.6 n equiv EOT=. n g= g=.. */ Si.3 n Sln / Laux Density-f-States-Bttleneck III-V lses t Si. c equiv ( /c ε SiO x /c /EOT depth )

8 Transit delay versus ass, # valleys, and EOT ch Nralized transit delay K Q I ch D.5.5 K / / / * * L Vlt, where 7.5 c/s g cds K g Vgs Vth ceq EOT includes wavefunctin depth ter (ean wavefunctin depth* SiO / seicnductr ) EOT=. n g=, istrpic bands g=, istrpic bands.6 n n.4 n.6 n.4 n c equiv ( /c ε SiO x /c /EOT sei ) */ Lw * gives lwest transit tie, lwest C gs at any EOT.

9 Lw effective ass als ipairs vertical scaling Shallw electrn distributin needed fr high I d, high g / G ds rati, lw drain-induced barrier lwering. Energy f L th well state L * / T well. Fr thin wells, nly st state can be ppulated. Fr very thin wells, st state appraches L-valley. Only ne vertical state in well. Miniu ~ 3 n well thickness. Hard t scale belw -6 n L g.

10 III-V Band Prperties, nral {} Wafer X L aterial aterial In Ga.5 InAs GaAs Si.5 As substrate substrate InP InP GaAs Si valley * / l / X valley t / Ex E.83 ev.87 ev.47 ev (negative) l / L valley t / EL E.47 ev.57 ev.8 ev L- valley transverse asses are cparable t valleys

11 Cnsider instead: valleys in {} Wafer X L aterial aterial In Ga.5 InAs GaAs Si.5 As substrate substrate InP InP GaAs Si valley * / l / Orientatin : ne L valley has high X valley t / Ex E.9.83 ev.6.87 ev..47 ev.9 (negative) vertical ass l / L valley t / EL E.47 ev.57 ev.8 ev X valleys & three L valleys have derate vertical ass

12 Valley in {} wafer: with quantizatin in thin wells X L aterial aterial In Ga.5 InAs GaAs Si.5 As substrate substrate InP InP GaAs Si valley * / l / X valley t / Ex E.83 ev.87 ev.47 ev (negative) l / L valley t / EL E.47 ev.57 ev.8 ev Selects L[] valley; lw transverse ass

13 {} -L FET: Candidate Channel Materials aterial In aterial.5.5 Ga GaAs GaSb Ge.5.5 As valley * / l / l / LL valley t / t / EE L L E E.47eVeV.8eVeV.7eV ev (negative) Well thickness fr L alignent n (?) n 4 n - - -

14 Wavefunctins Energy, ev Standard III-V FET: valley in [] rientatin 3 n GaAs well AlSb barriers = ev L=77 ev X[]= 64 ev X[] = 337 ev X[] X[] L L -

15 st Apprach: Use bth and L valleys in [].3 n GaAs well AlSb barriers [] rientatin = 4 ev L[] ()= ev L[] ()= 84 ev - X L[] L[] L[] L[], etc. =75 ev X=88 ev - L[]

16 n GaAs /L well g =, */ =.7 4 n GaSb /L well */ =.39, L,t */ =. Cbined -L wells in {} rientatin vs. Si J K Nralized current density K A V gs V V th 3/ GaSb, where GaAs cbined ( -L) transprt EOT includes the wavefunctin depth ter (ean wavefunctin depth* SiO / seicnductr ) K * / g * ( c / c ) g ( / ) 3/ ds, equiv.4 n.6 n EOT=. n g=.. */ Si.3 n c equiv ( /c ε SiO x /c /EOT ) sei

17 nd Apprach: Use L valleys in Stacked Wells Three.66 n GaAs wells.66 n AlSb barriers [] rientatin X L[] L[] L[]() = ev L[]()= 6 ev L[](3)= 99 ev =338 ev L[], etc =3 ev X=84 ev - - All L[]

18 Increase in C ds with and 3 wells 3 3 wells C ds,n-well /C ds,-well.5 wells.5 n well pitch n well pitch 3 n well pitch.. */

19 3 High Current Density () GaAs/AlSb Designs N s (/c ) Energy, ev Wavefunctins () rientatin 3 n GaAs well AlSb barriers X[] X[] L L -.3 n GaAs well AlSb barriers X L[] L[] L[] - () rientatin Tw.66 n GaAs wells.66 n AlSb barriers X L[] L[] L[] - Three.66 n GaAs wells.66 n AlSb barriers X L[] L[] Charge density, /c psitin, n 8 L valleys filling (V -V ), V gs th - L[] psitin, n (V -V ), V gs th - bth L[] - All L[] psitin, n psitin, n (V -V ), V gs th (V -V ), V gs th

20 Cncerns Nnparablic bands reduce bund state energies Failure f effective ass apprxiatin:- n wells - nlayer fluctuatins in grwth scattering cllapse in bility

21 Purdue Cnfiratin

22 Purdue Cnfiratin Steiger, Klieck, Bykin Ryu, Lee, Hegde, Tan

23 -D FET array = -D FET with high transverse ass -D FET -D Array FET Weak cupling narrw transverse-de energy distributin high density f states

24 3 rd Apprach: High Current Density L-Valley MQW FINFETs Drain current, A/ n well pitch.5 n well pitch EOT includes wavefunctin depth ter (ean wavefunctin depth* SiO / seicnductr ).3 n EOT.6 n EOT V gs -V th =.3 V.. */ valley energies E in, i qvin, i i gq * current I W V f Vin, i i charge : Q ch i gl * q V f V in, i gate vltage :V V Q / C gs f ch x

25 4 th Apprach: {} Orientatin Anistrpic Bands P. Asbeck transprt L[], L[]: derate vertical ass valleys ppulate High in - plane ass perpendicular t transprt high density f Lw in - plane ass parallel t transprt high carrier velcity states L[],[]:lw vertical ass deppulate High in - plane ass parallel t transprt lw carrier velcity Challenge : nly derate energy separatin between desired and undesired valleys.

26 Anistrpic bands, e.g. {} J K A 84 nralized drive current K V gs V V th.6 n 3/ EOT=. n, where.3 n.4 n K EOT includes wavefunctin depth ter (ean wavefunctin depth* SiO / seicnductr ) ( c / c ) g ( / / / ) 3/ ds, g ( equiv / / g=, / =.7 perpendicular g=, / =.6 perpendicular g=, perpendicular / =.5.. c equiv / ) Transprt in {} riented L valleys ( /c ε SiO x /c /EOT ) sei */ GaAsand Ge{}MOSFETswith L - valley transprt GaAs: n, t /.75, l /.9 Ge: n, t /.8, l /.58

27 THz FET scaling: with & withut increased DOS Gate length n Gate barrier EOT n well thickness n S/D resistance W effective ass * # band inia cannical fixed DOS stepped #

28 f, GHz drain current density, A/ Scaled FET perfrance: fixed vs. increasing DOS Increased density f states needed fr high drive current, fast 6,, 8 n ndes f ax, GHz SCFL static divider clck rate, GHz 3 cannical scaling 5 stepped # f bands transprt nly 5 5 f f ax.5 A/ VLSI etric 8 SCFL divider speed V gate verdrive gate length, n gate length, n

29 n / 3 THz III-V FETs: Challenges & Slutins T duble the bandwidth: gate dielectric: decrease EOT : S/D access regins: decrease resistivity : S/D regrwth Wistey et al Singisetti et al channel: keep sae velcity, but thin channel : increase density f states : L

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31 Purdue Cnfiratin

32 MOSFET Scaling Laws Cnstant- vltage / cnstant - velcity scaling laws : Changes required fr :increased bandwidth in an arbitrary circuit paraeter law paraeter law gate length L g, surce-drain cntact lengths gate-channel capacitance Cg ch L S / D (n) [/ C x / C sei / C ] DOS gate width W (n) g transcnductance g ~ Cg chvinjectin / L (S) g equivalent xide thickness Teq T x SiO / xide gate-surce, gate-drain fringing capacitances (n) Cgs f W,, g Cgd W (ff) g dielectric capacitance C x SiO LgWg / T (ff) eq S/D access resistances R, s R ( W ) d S/D cntact resistivity (ff) R s / W, g d Wg R / ( W ) inversin thickness T inv ~ T well / (n) S/D cntact resistivity ( c W ) seicnductr capacitance drain current I d ~ g ( Vgs Vth ) (A) C L W / T (ff) sei sei DOS capacitance electrn density g g inv * CDOS q n LgWg / (ff) - n ( c ) s drain current density ( A/ ) ~ W teperature rise (ne device, K) g

33 . n GaAs well, AlAs barriers, n {} GaAs Bund state energy, ev. valley L(l) valley : well thickness, eters n well : and L(l) inia bth ppulated. * /.67 L(l) : lw * high carrier ve lcity tw band inia dubles c ds * lateral / n well gd electrstatics at ~ 5-7 n.75 L g.

34 GaSb well, AlSb barriers, n {} GaSb Bund state energy, ev.6.5 GaSb well, AlSb barriers, n () GaSb L [], L[-] X [], X[].4.3. X [] L [-], L[-] well thickness, eters