Description Absolute Maximum Ratings Parameter Max. Units Thermal Resistance Parameter Typ. Max. Units

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1 l Advanced Prcess Technlgy l Dynamic dv/dt Rating l 175 C Operating Temperature l Fast Switching l Fully Avalanche Rated l Lead-Free Descriptin Fifth Generatin HEXFETs frm Internatinal Rectifier utilize advanced prcessing techniques t achieve extremely lw n-resistance per silicn area This benefit, cmbined with the fast switching speed and ruggedized device design that HEXFET Pwer MOSFETs are well knwn fr, prvides the designer with an extremely efficient and reliable device fr use in a wide variety f applicatins The TO-220 package is universally preferred fr all cmmercial-industrial applicatins at pwer dissipatin levels t apprximately 50 watts The lw thermal resistance and lw package cst f the TO-220 cntribute t its wide acceptance thrughut the industry G PD HEXFET Pwer MOSFET D S TO-220AB V DSS = 150V R DS(n) = 0 042Ω I D = 43A Abslute Maximum Ratings Parameter Max Units I T C = 25 C Cntinuus Drain Current, V V 43 I T C = C Cntinuus Drain Current, V V 30 A I DM Pulsed Drain Current 150 P C = 25 C Pwer Dissipatin 200 W Linear Derating Factr 1 3 W/ C V GS Gate-t-Surce Vltage ± 20 V E AS Single Pulse Avalanche Energy 590 mj I AR Avalanche Current 22 A E AR Repetitive Avalanche Energy 20 mj dv/dt Peak Dide Recvery dv/dt ƒ 5 0 V/ns T J Operating Junctin and -55 t 175 T STG Strage Temperature Range C Sldering Temperature, fr secnds 300 (1 6mm frm case ) Munting trque, 6-32 r M3 srew lbf in (1 1N m) Thermal Resistance Parameter Typ Max Units R θjc Junctin-t-Case 0 75 R θcs Case-t-Sink, Flat, Greased Surface 0 50 C/W R θja Junctin-t-Ambient 62 1/30/04

2 Electrical T J = 25 C (unless therwise specified) Parameter Min Typ Max Units Cnditins V (BR)DSS Drain-t-Surce Breakdwn Vltage 150 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdwn Vltage Temp Cefficient 0 17 V/ C Reference t 25 C, I D = 1mA R DS(n) Static Drain-t-Surce On-Resistance Ω V GS = V, I D = 22A V GS(th) Gate Threshld Vltage V V DS = V GS, I D = 250µA g fs Frward Transcnductance 19 S V DS = 50V, I D = 22A I DSS Drain-t-Surce Leakage Current 25 V µa DS = 150V, V GS = 0V 250 V DS = 120V, V GS = 0V, T J = 150 C I GSS Gate-t-Surce Frward Leakage V GS = 20V na Gate-t-Surce Reverse Leakage - V GS = -20V Q g Ttal Gate Charge 200 I D = 22A Q gs Gate-t-Surce Charge 17 nc V DS = 120V Q gd Gate-t-Drain ("Miller") Charge 98 V GS = V, See Fig 6 and 13 t d(n) Turn-On Delay Time 12 V DD = 75V t r Rise Time 55 I D = 22A ns t d(ff) Turn-Off Delay Time 71 R G = 2 5Ω t f Fall Time 69 R D = 3 3Ω, See Fig Between lead, L D Internal Drain Inductance 4 5 6mm (0 25in ) nh G frm package L S Internal Surce Inductance 7 5 and center f die cntact C iss Input Capacitance 2400 V GS = 0V C ss Output Capacitance 640 pf V DS = 25V C rss Reverse Transfer Capacitance 340 ƒ = 1 0MHz, See Fig 5 D S Surce-Drain Ratings and Characteristics Parameter Min Typ Max Units Cnditins I S Cntinuus Surce Current MOSFET symbl 43 (Bdy Dide) shwing the A G I SM Pulsed Surce Current integral reverse 150 (Bdy Dide) p-n junctin dide V SD Dide Frward Vltage 1 3 V T J = 25 C, I S = 22A, V GS = 0V t rr Reverse Recvery Time ns T J = 25 C, I F = 22A Q rr Reverse RecveryCharge µc di/dt = A/µs D S Ntes: Repetitive rating; pulse width limited by max junctin temperature ( See fig 11 ) V DD = 25V, starting T J = 25 C, L = 2 4mH R G = 25Ω, I AS = 22A (See Figure 12) ƒ I SD 22A, di/dt 820A/µs, V DD V (BR)DSS, T J 175 C Pulse width 300µs; duty cycle 2%

3 I D, Drain-t-Surce Current (A) VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5 0V 5.5V BOTTOM 4.5V 4.5V I D, Drain-t-Surce Current (A) VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5 0V 5.5V BOTTOM 4.5V 4.5V 20us PULSE WIDTH T = 25 1 V DS, Drain-t-Surce Vltage (V) 20us PULSE WIDTH T = V DS, Drain-t-Surce Vltage (V) Fig 1 Typical Output Characteristics Fig 2 Typical Output Characteristics I D, Drain-t-Surce Current (A) T J = 25 C T J = 175 C V DS= 50V 20µs PULSE WIDTH V GS, Gate-t-Surce Vltage (V) R DS(n), Drain-t-Surce On Resistance (Nrmalized) 3.0 I D = 37A V GS = V T J, Junctin Temperature ( C) Fig 3 Typical Transfer Characteristics Fig 4 Nrmalized On-Resistance Vs Temperature

4 C, Capacitance (pf) 6000 VGS = 0V, f = 1MHz Ciss = Cgs Cgd, C ds SHORTED C = 5000 rss Cgd Css = Cds Cgd 4000 C iss C ss C rss 0 1 V DS, Drain-t-Surce Vltage (V) V GS, Gate-t-Surce Vltage (V) I = D 22A V DS = 120V V DS = 75V V DS = 30V FOR TEST CIRCUIT SEE FIGURE Q G, Ttal Gate Charge (nc) Fig 5 Typical Capacitance Vs Drain-t-Surce Vltage Fig 6 Typical Gate Charge Vs Gate-t-Surce Vltage I SD, Reverse Drain Current (A) 1 T = 175 T = 25 V GS = 0 V V SD,Surce-t-Drain Vltage (V) I D, Drain Current (A) OPERATION IN THIS AREA LIMITED BY R DS(n) us us 1ms T = 25 C ms C T = 175 Single Pulse 1 1 V DS, Drain-t-Surce Vltage (V) Fig 7 Typical Surce-Drain Dide Frward Vltage Fig 8 Maximum Safe Operating Area

5 50 V DS R D I D, Drain Current (A) Fig a Switching Time Test Circuit V DS 90% R G V GS V Pulse Width 1 µs Duty Factr 0.1 % D U T - V DD T C, Case Temperature ( C) Fig 9 Maximum Drain Current Vs Case Temperature % V GS t d(n) t r t d(ff) t f Fig b Switching Time Wavefrms 1 Thermal Respnse (Z thjc ) 0.1 D = PDM t SINGLE PULSE t (THERMAL RESPONSE) Ntes: 1. Duty factr D = t 1 / t 2 2. Peak T J = P DM x Z thjc TC t 1, Rectangular Pulse Duratin (sec) Fig 11 Maximum Effective Transient Thermal Impedance, Junctin-t-Case

6 15V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.01Ω Fig 12a Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) TOP BOTTOM I D 9.0A 16A 22A Starting T, Junctin Temperature ( J C) Fig 12c Maximum Avalanche Energy Vs Drain Current I AS Fig 12b Unclamped Inductive Wavefrms Current Regulatr Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF V Q GS Q GD D.U.T. V - DS V G V GS 3mA Charge I G I D Current Sampling Resistrs Fig 13a Basic Gate Charge Wavefrm Fig 13b Gate Charge Test Circuit

7 Peak Dide Recvery dv/dt Test Circuit D U T ƒ - Circuit Layut Cnsideratins Lw Stray Inductance Grund Plane Lw Leakage Inductance Current Transfrmer - - R G dv/dt cntrlled by R G Driver same type as D U T I SD cntrlled by Duty Factr "D" D U T - Device Under Test - V DD Driver Gate Drive Perid P.W. D = P.W. Perid V GS =V * D.U.T. I SD Wavefrm Reverse Recvery Current Bdy Dide Frward Current di/dt D.U.T. V DS Wavefrm Dide Recvery dv/dt V DD Re-Applied Vltage Inductr Curent Bdy Dide Frward Drp Ripple 5% I SD * V GS = 5V fr Lgic Level Devices Fig 14 Fr N-Channel HEXFETS

8 TO-220AB Package Outline Dimensins are shwn in millimeters (inches) 2.87 (.113) 2.62 (.3).54 (.415).29 (.405) 3.78 (.149) 3.54 (.139) - A (.185) 4.20 (.165) - B (.052) 1.22 (.048) (.600) (.584) (.555) (.530) (.255) 6. (.240) 1.15 (.045) MIN 4.06 (.160) 3.55 (.140) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CPACK 1 - GATE 1- GATE 2 - DRAIN 1- GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR 3X 1.40 (.055) 1.15 (.045) 2.54 (.) 2X NOTES: 3X 0.93 (.037) 0.69 (.027) 0.36 (.014) M B A M 0.55 (.022) 3X 0.46 (.018) 2.92 (.115) 2.64 (.4) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Infrmatin EXAMPLE: T HIS IS AN IRF LOT CODE 1789 AS S EMBLED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Nte: "P" in assembly line psitin indicates "Lead-Free" INT ER NAT IONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C Data and specificatins subject t change withut ntice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segund, Califrnia 90245, USA Tel: (3) TAC Fax: (3) Visit us at fr sales cntact infrmatin.01/04

9 Nte: Fr the mst current drawings please refer t the IR website at:

Description Absolute Maximum Ratings Parameter Max. Units Thermal Resistance Parameter Typ. Max. Units

Description Absolute Maximum Ratings Parameter Max. Units Thermal Resistance Parameter Typ. Max. Units l l l l l Advanced Prcess Technlgy Dynamic dv/dt Rating 175 C Operating Temperature Fast Switching Fully Avalanche Rated Descriptin Fifth Generatin HEXFETs frm Internatinal Rectifier utilize advanced prcessing