THz Bipolar Transistor Circuits: Technical Feasibility, Technology Development, Integrated Circuit Results

Transcription

1 Plenary, 2008 IEEE-SI Symposium, October 12, 2008 THz Bipolar Transistor ircuits: Technical Feasibility, Technology Development, Integrated ircuit Results Mark Rodwell University of alifornia, Santa Barbara oauthors E. Lobisser, M. Wistey, V. Jain, A. Baraskar, J. Koo University of alifornia, Santa Barbara E. Lind Lund University Z. Griffith, J. Hacker, M. Urteaga, D. Mensa, Richard Pierson, B. Brar Teledyne Scientific ompany , fax

2 The End is Near (! ) The End (of Moore's Law) is Near (?) It's a great time to be working on electronics! Things to work on: InP HEMTs & HBTs: extend (f τ, f max ) to 2-3 THz, build THz Is GaN HEMTs: develop V- and W-band power amplifiers Si MOSFETs: work to keep them scaling past 22 nm MOS I design: build Is which bury the III-V's InGaAs MOSFETs: help keep VLSI scaling (maybe)

3 Scaling for THz Transistors

4 Simple Device Physics: Resistance bulk resistance contact t resistance contact t resistance -perpendicular - parallel bulk T R = ρ ρ R = A A contact R ρcontact = ρ A sheet W ' 3L Good approximation for contact widths less than 2 transfer lengths.

5 Simple Device Physics: Depletion Layers capacitance transit time space-charge limited current = ε A T T I 2εv τ = max = ( V 2φ ) 2 2v applied Vdepletion A T I = Δ V ΔT where I = τ max V applied V depletion 2φ

6 Simple Device Physics: Thermal Resistance Exact arslaw & Jaeger 1959 Long, Narrow Stripe HBT Emitter, FET Gate R th 1 πk th L ln L W 1 πk th L cylindrical heat flow near junction spherical heat flow far from junction R th = 1 πk th 1 πk th W sinh L 1 sinh 1 L W W L Square ( L by L ) I on heat sink R th 1 4K th L 1 πk th L planar heat flow spherical heat flow near surface far from surface

7 Simple Device Physics: Fringing apacitance L W ε 1. 5 εε T parallel - plate fringing L slowly - varying function ε of W1 / G and W2 / G (1 to 3) ε wiring capacitance FET parasitic capacitances / L > ε parasitic / L ~ ε VLSI power-delay limits FET scaling constraints

8 Frequency Limits and Scaling Laws of (most) Electron Devices τ thickness area / thickness R / area R I Δ T top ρ contact bottom ρ area contact max, space-charge-limit power length ρ 4 sheet area / width length length egt log width ( thickness) PIN photodiode 2 R top R bottom To double bandwidth, reduce thicknesses 2:1 Improve contacts 4:1 reduce width 4:1, keep constant length increase current density 4:1

9 Bipolar Transistor Design

10 Bipolar Transistor Design We τ τ b c I 2 T 2D D b = T 2v c εa n sat cb = c /Tc c, max vsat Ae ( Vce,operating V ce,punch-through ) / T T b 2 c W bc ( ) emitter length L E T c ΔT P L E L e 1 ln We R ex = ρ contact / A e W W e bc ρ Rbb = ρ sheet 12Le 6L e A contact contacts

11 Bipolar Transistor Design: Scaling We τ τ b c 2 T 2D D b = T 2v c εa I n sat cb = c /Tc c, max vsat Ae ( Vce,operating V ce,punch-through ) / T T b 2 c W bc ( ) emitter length L E T c ΔT P L E L e 1 ln We R ex = ρ contact / A e W W e bc ρ Rbb = ρ sheet 12Le 6L e A contact contacts

12 Bipolar Transistor Scaling Laws W e T b W bc T c hanges required to double transistor bandwidth: ( ) emitter length L E parameter change collector depletion layer thickness decrease 2:1 base thickness decrease 1.414:1 emitter junction width decrease 4:1 collector junction width decrease 4:1 emitter contact resistance decrease 4:1 current density increase 4:1 base contact resistivity decrease 4:1 Linewidths scale as the inverse square of bandwidth because thermal constraints dominate.

13 Thermal Resistance Scaling : Transistor, Substrate, Package cylindricall heat flow near junction spherical flow for r > L e planar flow for r > D HBT / 2 P L e P 1 1 P Tsub D / 2 ΔTsubstrate ln 2 π K InPLE We πk InP LE D K InP D increases logarithmically insignificant variation increases quadratically if T sub is constant ΔT package π K P u chip W chip junctio on temperature ris se, Kelvin 140 Tsub = 40 μm (150 GHz / f clock ) HBT ML I total substrate: cylindricalspherical regions package 20 substrate: planar region master-slave D-Flip-Flop clock frequency, GHz Wiring lenghts scale as 1/bandwidth. Power density, scales as (bandwidth) 2.

14 Thermal Resistance Scaling : Transistor, Substrate, Package cylindricall heat flow near junction spherical flow for r > L e planar flow for r > D HBT / 2 P L e P 1 1 P Tsub D / 2 ΔTsubstrate ln 2 π K InPLE We πk InP LE D K InP D increases logarithmically insignificant variation increases quadratically if T sub is constant ΔT package π K P u chip W chip junctio on temperature ris se, Kelvin 140 T sub = 40 μm (150 GHz / f clock ) 120 total HBT ML I 100 Probable best solution: 80 substrate: cylindricalspherical regions package 20 substrate: planar region Wiring lenghts scale as Thermal Vias ~500 nm below InP subcollector 1/bandwidth. Power density,...over full active I area. master-slave D-Flip-Flop clock frequency, GHz scales as (bandwidth) 2.

15 InP Bipolar Transistor Scaling Roadmap industry university university appears maybe industry feasible emitter nm width Ω μm 2 access ρ base nm contact width, Ω μm 2 contact ρ collector nm thick, ma/μm 2 current density V, breakdown f τ GHz W e f max GHz T b power amplifiers GHz digital 2:1 divider GHz W bc T c

16 an we make a 1 THz SiGe Bipolar Transistor? Simple physics clearly drives scaling transit times, cb /I c thinner layers, higher current density high power density narrow junctions small junctions low resistance contacts Key challenge: Breakdown 15 nm collector very low breakdown (also need better Ohmic contacts) InP SiGe emitter nm width Ω μm 2 access ρ base nm contact width, Ω μm 2 contact ρ collector nm thick ma/μm ??? V, breakdown f τ GHz f max GHz PAs GHz digital GHz (2:1 static divider metric) Assumes collector junction 3:1 wider than emitter. Assumes SiGe contacts 2:1 wider than junctions

17 HBT Design For I Performance from charge-control analysis: ) / 0.5 )(0.5 / ( ) 6 6 )( / ( L f cbi cbx je f cbi cbx je L gate V I qi kt I V T Δ Δ τ τ ). / 0.5 (0.5 ) / (0.5 L f cbi je bb L f cbi cbx ex V I R V I R Δ Δ τ τ

18 InP HBT: Status

19 z) f max (GH InP DHBTs: September GHz 500 GHz 600 GHz 125 nm 250 nm 700 GHz 800 GHz 900 GHz = f max f τ Teledyne DBHT UIU DHBT NTT DBHT ETHZ DHBT 600 UIU SHBT Updated Sept nm 250 nm 350 nm USB DHBT NGST DHBT HRL DHBT IBM SiGe Vitesse DHBT popular metrics ti : fτ or fmax alone ( f f ) / 2 τ (1 f τ f τ f max max 1 f t (GHz) ( τ τ ) f max ) 1 much better metrics : power amplifiers: PAE, associated gain, mw/ μm low noise amplifiers: Fmin, associated gain, digital : fclock, hence ( cbδv / Ic ), ( RexIc / ΔV ), ( R I / Δ V ), b bb c c

20 512 nm InP DHBT Laboratory Technology 500 nm mesa HBT 150 GHz M/S latches 175 GHz amplifiers USB / Teledyne / GS USB 500 nm sidewall HBT DDS I: 4500 HBTs GHz op-amps Production ( Teledyne ) Z. Griffith M. Urteaga P. Rowell D. Pierson B. Brar V. Paidi Teledyne f τ = 405 GHz f max = 392 GHz V br, ceo = 4 V Teledyne / BAE 20 GHz clock Teledyne / USB dbm 2 GHz with 1 W dissipation

21 150 nm thick collector 256 nm Generation 40 InP DHBT GHz Amplifier 200 GHz master-slave latch design Z. Griffith, E. Lind J. Hacker, M. Jones db H 21 f τ = 424 GHz U f max = 780 GHz nm thick collector Hz 30 db U f τ = 560 GHz H 21 f max = 560 GHz Hz 60 nm thick collector db U H 21 Hz m 2 ma/μ ma/μm 2 ma/μm V ce V ce 10 f = 218 GHz 10 max f = 660 GHz t V ce

22 324 GHz Medium Power Amplifiers in 256 nm HBT Is designed by Jon Hacker / Teledyne Teledyne 256 nm process flow- Hacker et al, 2008 IEEE MTT-S ~2 mw saturated output power Power (dbm m), PAE (%) 20 )Output Power (dbm) Gain (db) Drain urrent (ma) 10 PAE (%) urrent, ma Gain (db), Input Power (dbm) 0

23 128 / 64 / 32 nm HBT Technologies

24 onventional ex-situ contacts are a mess THz transistor bandwidths: very low-resistivity contacts are required textbook contact with surface oxide with metal penetration Interface barrier resistance Further intermixing during high-current operation degradation

25 Improvements in Ohmic ontacts 128 nm generation requires ~ 4 Ω - μm 2 emitter & base resistivities iti 64 nm generation requires ~ 2 Ω - μm 2 ontacts to N-InGaAs*: Mo MBE in-situ 0.3 (/- 0.7) Ω - μm 2 TiW ex-situ / NH4 pre-clean ~1 to 2 Ω - μm 2 variable between process runs ontacts to P-InGaAs: Mo MBE in-situ below 2.5 Ω - μm 2 Pd/Ti... ex-situ ~4 Ω - μm 2 *measured emitter resistance remains higher than that of contacts.

26 Mo Emitter ontacts: Robust Integration into Process Flow Proposed Process Integration: ti

27 Process Must hange Greatly for 128 / 64 / 32 nm Nodes control undercut thinner emitter thinner emitter thinner base metal thinner base metal excess base metal resistance Undercutting of emitter ends {101}A planes: fast {111}A planes: slow

28 128 nm Emitter Process: Dry Etched Metal & Semiconductor Litho pattern sidewall dry etch wet etch metal 3 4 BHF SiO2 TiW Ti InGaAs n InGaAs n InGaAs n InP n InP n InP n InP n InGaAs p Base InGaAs p Base InGaAs p Base InGaAs p Base InGaAs p Base Recent 128 nm emitter width to be submitted db U f max = 560 GHz f τ = 560 GHz H ma/μ μm Hz c.a. 200 nm emitter metal width V ce

29 Planarization E/B Processes for 64 & 32 nm Planarization boundary

30 What about InGaAs HEMTs?...& InGaAs MOSFETS?

31 InGaAs HEMTs and InGaAs MOSFETs high-k h gate barrier N source/ drain by MBE regrowth Source Gate Drain K Shinohara sub-22-nm InGaAs MOSFETs being developed for potential use in VLSI Efforts may: improve understanding di HEMT & MOSFET scaling limits it produce process modules which aid THz HEMTs Key III-V MOSFET scaling limits: low density of states limits g m fringing /g m does not scale low m* high well energy minimum well thickness Additional HEMT scaling limits: Additional HEMT scaling limits: high access resistance: barriers, recess regions, contacts limits to sheet concentration from small hetero-barrier energy

32 HBT Applications

33 Applications of THz InP HBTs Mixed-Signal Is (ADs, DAs, DDS) benefit in high-clock-rate Is with 1k-3k devices lack of MOS integration a major limitation Mark Rosker's talk Precision GHz analog Is using THz transistors Sanjay Raman's talk, Zach Griffith's talks mm-wave Power: 60 GHz & up GaN threatens, but f max gain PAE GHz transceiver Is for low-volume military / scientific applications

34 Few-THz Bipolar Transistors THz InP Bipolar Transistors: can it be done? Scaling limits: contact resistivities, device and I thermal resistances. 62 nm (1 THz f τ, THz f max ) scaling generation is feasible. 700 GHz amplifiers, 450 GHz digital logic Is the 32 nm (1 THz amplifiers) generation feasible? THz InP Bipolar Transistors: what would we do with it? Mixed-Signal I Power density & MOS integration are serious challenges Precision GHz analog systems mm-wave power Sub-mm-wave electronics