Transistors - a primer
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1 ransistors - a primer What is a transistor? Solid-state triode - three-terminal device, with voltage (or current) at third terminal used to control current between other two terminals. wo types: bipolar junction transistors and field effect devices. We concentrate on FEs: source drain gate
2 he history: vacuum tubes Basic idea of three-terminal devices for current control goes back to 1906, when Lee deforest invented the vacuum triode: grid (base) cathode (emitter) heater anode (collector) Ground anode; bias cathode to large negative voltage w.r.t anode. Heater boils electrons off cathode (thermionic emission); accelerated through grid toward anode. ac voltage on grid can modulate electron current! hree-terminal device with gain: dawn of the information age.
3 he history: vacuum tubes Problems with vacuum tubes: Bulky Fragile Long warm-up times High power consumption, largely wasted High speeds difficult - require extra plates, grids to minimize capacitances (pentodes) Miniaturization very challenging. here must be a better way. acuum tubes still best for: High powers (ex.: e-gun power supplies) Radiation-hardened electronics (ex.: B-52s)
4 he history: Lillienfeld Basic idea proposed (1930): Method and apparatus for controlling electric currents Use third electrode to modulate current between ohmic contacts on a semiconductor. Solid-state triode. from Pierret.
5 Basic field effect transistor idea Normally off: Gate acts like capacitor plate - applied voltage creates channel with free carriers, connecting source and drain. Lilienfeld Normally on: Gate acts like grid - applied voltage restricts flow of (lightly doped) carriers from source to drain. Shockley (grid-like) Why did these ideas first run into trouble? Surface states! Materials quality prevented practical FEs until 1955.
6 ypes of field effect transistors different metals JFE Junction FE MESFE MEtal Semiconductor FE Channel, source, drain all same type of doped semiconductor. Normally on - requires gate voltage to turn off S conduction; devices operate in depletion mode. Gate can be anywhere between source and drain. Current flow restricted by depletion zone (from pn junction in JFE; from Schottky barrier in MESFE). Fairly robust (no super-thin insulating layers, etc.)
7 ypes of field effect transistors MOSFE or MISFE Metal Oxide or Metal Insulator Semiconductor FE channel Source, drain different doping type than bulk of semiconductor Normally OFF - gate must be biased sufficiently to invert channel region in order to see transistor action; devices operate in accumulation mode. Requires gate to extend over source and drain. hin insulating barrier (gate oxide) necessary. Bulk may be p or n - complementary metal-oxide-semiconductor processing (CMOS).
8 ypes of field effect transistors HEM High Electron Mobility ransistor undoped GaAs Source, drain are ohmic contacts to GaAs 2deg channel. Normally ON device (modulation doping) operates in depletion mode. ery high mobilities can lead to very high speed devices (cell phone electronics). Gate can be anywhere between source and drain.
9 ransistor operation and transconductance Basic transistor operation: I load G One obvious figure of merit for a transistor is transconductance: g m I ransistors with a higher g m are better switches than those with lower values. G
10 he MOS system At left are band diagrams for metal-insulator-semiconductor stacks. n-type p-type hese are drawn assuming flat bands; that is, negligible charge transfer at interfaces to cause band bending, + negligible surface states. For these ideal cases, with no bias on the metal, the charge density of the semiconductor = the full doped density right up to the interface.
11 Band picture + inversion Ideal system when metal is biased: Accumulation mode: gate bias bends bands to enhance free charge density in plane at insulatorsemiconductor interface. epletion mode: gate bias bends bands to reduce free charge density in plane at insulator-semiconductor interface. Inversion mode: gate bias bends bands so much that the free charge density in plane at insulatorsemiconductor interface has the opposite sign as the doping!
12 hreshold voltage he threshold voltage is defined as the gate voltage required to produce inversion in the channel. depends on the band structure, the doping level of the semiconductor, and the geometry of the device (oxide thickness, oxide + SC dielectric constants, etc.). Can be calculated in certain models (will do later). Often determined empirically. For an ideal intrinsic MOS stack, threshold voltage is zero. Assumes no surface states + bands flat when G =0. In following, assume is just a device parameter.
13 Basic transistor operation and the linear regime from Pierret Assume first that S = 0, and ( G - ) >>. gradual channel C x = capacitance per unit area of gate oxide 2d charge density in inversion layer: en C ( ) otal current from this layer: W I d = W en2d µ µ Cx ( G ) L L 2d x G
14 Basic transistor operation and the linear regime So, for small source-drain biases, W I d µ Cx ( G ) L FE acts here like gate-controlled variable resistor: I << I ( G W g m = µ G L ) C x increasing G Higher gate capacitance, higher transconductance! Knowing device dimensions, can measure I vs. G and calculate the mobility from this linear regime. Mobility found in FEs tends to be lower than bulk: Gate field enhances interface scattering.
15 Saturation regime - physical picture from Pierret What happens at higher sourcedrain voltages? hat is, what about when > ~ ( G - )? Physically, the thickness and charge density of the inversion layer (channel) shrinks along the length of the channel. When inversion layer just vanishes at drain, device is at pinch-off. At higher values of, for long channels I stops changing. Result is saturation regime.
16 Saturation regime, quantitative: square law efine the channel direction as y. Local potential in channel = (y) Local charge density = )) ( ( y C G x Local current: = = G x L d C W L I dy y I 0 0 ) ( ) ( µ dy d y C W y I G x µ )) ( ( ) ( = Result: G sat G x L C W I =, 2 0, 2 ) ( µ
17 Square law G sat G x L C W I =, 2 0, 2 ) ( µ Since I only increases until pinch-off, can use above formula to find both pinch-off voltage and saturation current: G sat =, 2, ) ( 2 G x sat L C W I = µ So, assuming constant mobility and ignoring changes in depletion width down length of channel, we find that saturation current scales quadratically with ( G - ). his provides another way of inferring mobility. (acit assumption: source, drain contact resistances are negligible.)
18 What sets equilibrium depletion width? First, recall some definitions: E i = energy of the middle of the gap in the semiconductor. S = potential at sc-oxide interface. F = bulk (E - -E F )/e (x) = (1/e)[E i (bulk)-e i (x) n i = intrinsic carrier density = N N exp( E / 2k ) C g B
19 What sets equilibrium depletion width? For nondegenerate semiconductors, = ) / ln( ) / ln( i B i A B F n N e k n N e k Middle of depletion: F S = Onset of inversion: F S 2 =
20 elta depletion Exact self-consistent solution shows inversion charge confined to very thin layer at interface. epletion width increases only slightly once inversion occurs. Approximation: further gating only affects inversion charge. epletion width at some surface potential: d 2ε ε s 0 = S en A 1/ 2 epletion width at inversion: d 2ε ε s = 0 2 F en A 1/ 2
21 Bulk charge picture akes into account variation in depletion width along channel. Suppose the depletion width near source and drain under no bias is d, and under bias it depends locally on position, d(y). he induced charge density at position y is then ] ) ( [ ) ( A G x d y d qn C + inversion layer free charge additional exposed acceptors efining x A d C d en and substituting our delta-depletion results for the ds gives F W G x C
22 Bulk charge picture With this more careful accounting, we find a more exact expression for the I - characteristics as a function of gate voltage: G sat F F F d G x L C W I + + =, 2 3/ 2 0, ) ( µ Neither the bulk charge picture nor the square law picture predict saturation - it has to be inserted by hand into the model. Complete numerical solution of the whole system does, of course, give pretty nice results, including saturation.
23 What performance issues are important? Speed (10 GHz) hreshold voltage (< ~0.5 ) On-off ratio (> 10000) Off-current & sub-threshold behavior urability (mean time to failure)
24 What limits speed? Gate capacitance Switching FE requires moving charge off and on the gate. Assuming low capacitance and high conductance leads, the maximum frequency possible is set by when the gate admittance becomes comparable to the transconductance: gm µ sat fmax = 2 2πC 2πL ime-of-flight x Clearly in some limit one is limited by the speed with which carriers can traverse the device.
25 Why are low thresholds important? In some sense, threshold voltages show how efficient your switching is - until inversion, one pays the cost of charging up the gate without getting any of the transistor benefit. Also, power dissipation varies like G2, so being able to run at lower voltages would produce a big savings in heating! rend: c. 1980, L logic: G ~ 5. Now, G ~ 2.2 on CPU.
26 On/off ratios and off-currents A transistor is only a good switch if, when it s off, it s really off. ypical on/off current ratios must be ~ 10 4, or else these subthreshold source-drain currents end up dissipating an enormous amount of power. ransistor should also switch sharply - it s subthreshold properties need to be good.
27 urability Commercially viable transistors need to last a long time! Remember, ~ 10 7 transistors per chip, each operating 10 9 times per second. Only a few failures ruin the chip. When was the last time the CPU died in any computer you own? he mean time to failure is extremely long! Most common transistor failure mode: gate oxide breakdown. Not suprising: ~ 3 across 3 nm of oxide = 10 9 /m (!).
28 Summary ransistors are three-terminal devices, and MOSFEs are the most commonly used type in high technology. Normally off devices, with linear source-drain I curves at low source-drain bias once gate voltage exceeds threshold for inversion. I curves saturate at high bias, with saturation currents depending strongly (roughly quadratically) on gate voltage. Performance criteria clearly depend both on device geometry and on materials choices. MOSFEs are only as good as they are because of decades of exacting materials development.
29 Next time: emands of the electronics industry for high performance transistors. he semiconductor roadmap, and signs of trouble ahead.
gate Basic idea of three-terminal devices for current control goes back to 1906, when Lee deforest invented the vacuum triode:
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