Si Nanowire FET Modeling and Technology

Transcription

1 Si Nanowire FET Modeling and Technology November 8, Peking University H. Iwai Tokyo Inst. Tech. 1

2 First Computer Eniac: made of huge number of vacuum tubes 1946 Big size, huge power, short life time filament dreamed of replacing vacuum tube with solid state device Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption 2

3 Downsizing of the components has been the driving force for circuit evolution Vacuum Transistor IC LSI ULSI Tube 10 cm cm mm 10 µm 100 nm 10-1 m 10-2 m 10-3 m 10-5 m 10-7 m In 100 years, the size reduced by one million times. There have been many devices from stone age. We have never experienced such a tremendous reduction of devices in human history. 3

4 Scaling Method: by R. Dennard in S 1 Wdep 1 1 D Wdep: Space Charge Region (or Depletion Region) Width Wdep has to be suppressed Otherwise, large leakage between S and D I Leakage current K=0.7 for example K K Wdep Potential in space charge region is high, and thus, electrons in source are attracted to the space charge region. X, Y, Z : K, V : K, Na : 1/K K Wdep V/Na : K I K 0 0 K V 0 0 V 1 By the scaling, Wdep is suppressed in proportion, and thus, leakage can be suppressed. Good scaled I-V characteristics I : K 4 4

5 Downscaling merit: Beautiful! Geometry & Supply voltage L g, W g T ox, V dd K Scaling K : K=0.7 for example Drive current in saturation I d K I d = v sat W g C o (V g V th ) C o : gate C per unit area W g (t 1 ox )(V g V th )= W g t 1 ox (V g V th )= KK 1 K=K I d per unit W g I d /µm 1 I d per unit W g = I d / W g = 1 Gate capacitance C g K C g = ε o ε ox L g W g /t ox KK/K = K Switching speed τ K τ= C g V dd /I d KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area A chip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/k 2 N α/k 2 = 1/K 2, when α=1 Power per chip P α fncv 2 /2 K 1 (αk 2 )K (K 1 ) 2 = α = 1, when α=1 5 5

6 k= 0.7 and α =1 Single MOFET Vdd 0.7 Lg 0.7 Id 0.7 Cg 0.7 P (Power)/Clock 0.73 = 0.34 τ (Switching time) 0.7 Chip N (# of Tr) 1/0.7 2 = 2 f (Clock) 1/0.7 = 1.4 P (Power) 1 k= =0.5 and α =1 Vdd 0.5 Lg 0.5 Id 0.5 Cg 0.5 P (Power)/Clock = τ (Switching time) 0.5 N (# of Tr) 1/0.5 2 = 4 f (Clock) 1/0.5 = 2 P (Power) 1 6 6

7 Integrated Circuits Technologies are still very important for Green or power saving! 1. Green by Integrated Circuits Power saving by Microprocessor control for all the human systems 2. Green of Integrated Circuits Power saving of Integrated Circuits by Down Scaling of MOSFETs in PC, Data Center, Router, etc.

8 Down scaling is the most effective way of Power saving. It has been always discussed about the limit of downscaling, but the down scaling of MOSFETs is still possible for another 10 or 20 years! 3 important technological items for DS. 1. Thinning of high-k beyond 0.5 nm 2. Metal S/D 3. Si-Nanowire FET

9 Question: How far we can go with downscaling?

10 Many people wanted to say about the limit. Past predictions were not correct!! Period Expected Cause limit(size) Late 1970 s 1µm: SCE Early 1980 s 0.5µm: S/D resistance Early 1980 s 0.25µm: Direct tunneling of gate SiO 2 Late 1980 s 0.1µm: 0.1µm brick wall (various) nm: Red brick wall (various) nm: Fundamental? 10

11 Historically, many predictions of the limit of downsizing. VLSI text book written 1979 predict that 0.25 micrometer would be the limit because of directtunneling current through the very thin gate oxide.

12 VLSI textbook Finally, there appears to be a fundamental limit 10 of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide... begin to make the devices of smaller dimension unworkable. 12

13 Direct tunneling effect Gate Electrode Wave function Gate Oxide Potential Barrier Si Substrate Direct tunneling current Gate Oxide G S D Direct tunneling leakage current start to flow when the thickness is 3 nm. 13

14 Gate electrode Lg Gate oxide Si substrate S MOSFETs with 1.5 nm gate oxide G D Direct tunneling leakage was found to be OK! In 1994! Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm 0.03 Vg = 2.0V Vg = 2.0V 0.3 Vg = 2.0V 1.2 Vg = 2.0V 1.5 V 1.5 V 1.5 V 1.5 V Id (ma / m) V 0.5 V 0.0 V V 0.5 V 0.0 V V 0.5 V 0.0 V V 0.5 V 0.0 V Vd (V) Vd (V) Vd (V) Vd (V) 14

15 S G Ig Gate leakage: Ig Gate Area Gate length (Lg) D Id Drain current: Id 1/Gate length (Lg) Lg small, Then, Ig small, Id large, Thus, Ig/Id very small Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm 0.03 Vg = 2.0V Id Id (ma / m) V 1.0 V 0.5 V 0.0 V Vg = 2.0V 1.5 V 1.0 V 0.5 V 0.0 V Vg = 2.0V 1.5 V 1.0 V 0.5 V 0.0 V Vg = 2.0V 1.5 V 1.0 V 0.5 V 0.0 V Vd (V) Vd (V) Vd (V) Vd (V)

16 5 nm gate length CMOS Is a Real Nano Device!! 5nm Length of 18 Si atoms H. Wakabayashi et.al, NEC IEDM,

17 Predicted limit now Tunneling distance 3 nm S D MOSFET operation Lg = 3 nm? Ultimate Limit Atom distance 0.3 nm Below this, no one knows future! 17

18 ITRS expect Lg less than 10nm 2009 ITRS Technology Trend: MPU gate length MPU physical gate length

19 How far can we go? Past µm 6µm 4µm 3µm 2µm 1.2µm 0.8µm 0.5µm 0.35µm 0.25µm 180nm 130nm 90nm 65nm 45nm Future 0.7 times per 3 years In 40 years: 15 generations, Size 1/200, Area 1/40,000 Now 32nm 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm? At least 5,6 generations, for 15 ~ 20 years Hopefully 8 generations, for 30 years

20 CMOS scaling is the mainstream /JEITA

21 ITRS Vdd (V) Vdd stay high update 2003, 2005, up (bulk) 2008up (UTB) 2008up (DG) (bulk) 2007 (UTB) 2007 (DG) 2005 (bulk) (UTB) 2005 (DG) Year 2008 for HP Logic 21 EOT (nm) ITRS EOT limit = 0.5 nm? 2008up (bulk) 2008up (UTB) 2008up (DG) 2007 (bulk) 2007 (UTB) 2007 (DG) 2005 (bulk) 2005 (UTB) 2005 (DG) 2003 (bulk) Year Is 0.5nm real limit? Delay Saturation

22 Scaling of high beyond 0.5 nm is important Power of FET = CV 2 /2 D 3 (=L 3 ) Problems SCE Variation in Vth Increase in Off-leakage current σvth Normalized σvth Solution ITRS2007

23 Direct contact of high k to Si Power per MOSFET (P) (Scaling) P L g 3 For the past 45 years SiO2 and SiON For gate insulator Today EOT=1.0nm EOT Limit 0.7~0.8 nm One order of Magnitude 45nm node L g =22nm EOT=0.5nm Metal SiO 2 /SiON Si Metal HfO nm SiO 2 /SiON Si Introduction of High-k Still SiO2 or SiON Is used at Si interface Metal High-k Si Direct Contact Of high-k and Si SiO2/SiON interfacial layer Direct contact High-k/Si EOT can be reduced further beyond 0.5 nm by using direct contact to Si By choosing appropriate materials and processes. Now Year 23

24 Cluster tool for high-k thin film deposition Preparation Room Sputter for metal 5 different target Robot room E-Beam Evaporation 8 different target Flash Lamp Anneal Micro to mille-seconds

25 Challenge to ~0.3nm EOT<0.5nm with Gain in Drive Current (a) EOT=0.37nm (b) EOT=0.43nm (c) EOT=0.48nm V th =-0.04V V th =-0.03V V th =-0.02V insufficient compensation region Drain 0.4 voltage (V) 0.2 Drain 0.4 voltage (V) Drain voltage (V) (ma)3.5 Drain current W/L=2.5/50µm W/L=50/2.5µm PMA 300 o C (30min) 4%up 14%up 14% of I d increase is observed even at saturation region EOT below 0.4nm is still useful for scaling 25 1

26 Si Nanowire FET 26

27 Because of off-leakage control, Planar Nanowire S Wdep 1 D Leakage current Source Gate Drain Planar FET Fin FET Nanowire FET

28 Nanowire FET Multiple Gate (Fin)FET Nanowire FET ITRS 2009 Bulk Fin Nanowire Bulk or SOI Fin Si Si Nanowire

29 Si nanowire FET as a strong candidate 1. Compatibility with current CMOS process 2. Good controllability of I OFF S Leakage current Wdep 1 D cut-off Off 3. High drive current source Drain Gate:OFF Gate: OFF drain Source 1D ballistic conduction Multi quantum Channel E Quantum channel Quantum channel Quantum channel k Quantum channel High integration of wires 29

30 Ioff (na/um) Off Current DG ITRS (Bulk) ITRS (SOI) ITRS (DG) dia~10nm bulk FinFET SiNWFET GeNWFET ITRS(Planer) ITRS(SOI) ITRS(DG) 10 Bulk Si Nanowire dia~3nm Ion (ua/um) 30

31 Increase the Number of quantum channels By Prof. Shiraishi of Tsukuba univ. 4 channels can be used Eg Eg Energy band of Bulk Si Energy band of 3 x 3 Si wire 31

32 Maximum number of wires per 1 µm Front gate type MOS 165 wires /µm 6nm 6nm pitch By nano-imprint method Metal gate electrode(10nm) Surrounded gate type MOS 33 wires/µm 30nm High-k gate insulator (4nm) Si Nano wire (Diameter 2nm) 30nm pitch: EUV lithograpy Surrounded gate MOS 32

33 Si/Si 0.8 Ge 0.2 superlattice epitaxy on SOI SiN HM SiN SiGe Si SiGe Si SiGe Si BOX Device fabrication Anisotropic etching of these layers BOX Isotropic etching of SiGe BOX ( ) The NW diameter is controllable down to 5 nm by self limited oxidation. Gate depositions HfO 2 (3nm) TiN (10nm) Poly-Si (200nm) Gate Gate etching Gate S/D implantation Spacer formation Activation anneal Salicidation Standard Back-End of-line Process BOX BOX Process Details : C. Dupre et al., IEDM Tech. Dig., p.749,

34 3D-stacked Si NWs with Hi-k/MG Top view Cross-section SiN HM Source Gate Drain 500 nm <110> Wire direction : <110> 50 NWs in parallel 3 levels vertically-stacked Total array of 150 wires EOT ~2.6 nm 50nm NWs BOX 8

35 SiNW Band structure calculation

36 Cross section of Si NW First principal calculation, D=1.96nm D=1.94nm D=1.93nm [001] [011] [111]

37 Si nanowire FET with 1D Transport Orientation [001] [011] [111] Diameter (nm) Energy (ev) 0-1 G Z G Z G Wave Number (a) Orientation Diameter (nm) 1 Energy (ev) 0 0 [001] [011] [111] G Z G Z G Wave Number (b) Z Z Small mass with [011] Large number of quantum channels with [001]

38 Atomic models of a Si quantum dot and Si nanowires 6.6 nm diameter SiQD 8651 atoms 20 nm diameter Si(100)NW 8941 atoms 10 nm diameter Si(100)NW 2341 atoms

39 RSDFT suitable for parallel first-principles calculation - Real-Space Finite-Difference Higher-order finite difference pseudopotential method Sparse Matrix J. R. Chelikowsky et al., Phys. Rev. B, (1994) FFT free (FFT is inevitable in the conventional plane-wave code) MPI ( Message Passing Interface ) library Kohn-Sham eq. (finite-difference) 3D grid is divided by several regions for parallel computation. 1 2 [ ]( r PP + v ) ˆ ( r ) ( r ) ( r s ρ + v nloc φn = ε nφn ) 2 CPU6 CPU7 CPU8 Higher-order finite difference n m n x ψ ψ m= 6 ( x, y, z) C ( x+ m x, y, z) CPU3 CPU4 CPU5 MPI_ISEND, MPI_IRECV CPU0 CPU1 CPU2 Integration Mesh ψ () rψ () r dr ψ ( r) ψ ( r) x y z m n m i n i i= 1 MPI_ALLREDUCE

40 Massively Parallel Computing Based on the finite-difference pseudopotential method (J. R. Chelikowsky et al., PRB1994) Highly tuned for massively parallel computers with our recently developed code RSDFT Iwata et al, J. Comp. Phys., to be published Real-Space Density-Functional Theory code (RSDFT) Computations are done on a massively-parallel cluster PACS-CS at University of Tsukuba. (Theoretical Peak Performance = 5.6GFLOPS/node) e.g.) The system over 10,000 atoms Si H 1996 (7.6 nm diameter Si dot) Convergence behavior for Si H 1996 Grid points = 3,402,059 Bands = 22,432 Computational Time (with 1024 nodes of PACS-CS 6781 sec. 60 iteration step = 113 hour

41 (ev) (ev) Band Structure and DOS of Si(100)NWs (D=1nm, 4nm, and 8nm) D=1nm D=4nm (ev) (ev) (ev) (ev) D=8nm DOS ( States / ev atom ) (ev) DOS ( States / ev atom ) (ev) DOS ( States / ev atom ) (ev) D=1 nm Si21H20 41 atoms) KS band gap=2.60ev D = 4 nm Si341H atoms) KS band gap = 0.81eV D=8 nm Si1361H164 (1525 atoms) KS band gap=0.61ev KS band gap of bulk (LDA) = 0.53eV

42 Band structure of 8-nm-diameter Si nanowire near the CBM KS band gap = ev (@Γ) Each band is 4-dgenerate. (ev) mev (96 mev) 23 mev (24 mev) kx kz ky kx Effective mass equation 2 h 2m * t x y h 2m * l z 2 2 Φ( r) = ( ε ε CBM ) Φ( r) The band structure can be understood that electrons near the CBM in the bulk Si are Confined within a cylindrical geometry.

43 Si nano wire with surface roughness Si12822H1544 Top View Side View Si12822H ,366 atoms 10nm diameter 3.3nm height (100) Grid spacing 0.45Å (~14Ry) # of grid points 4,718,592 # of bands 29,024 Memory 1,022GB 2,044GB

44 SiNW Band compact model

45 Landauer Formalism for Ballistic FET Q f Q b Energy µ S E 2max µ D E 2min E 2min O x max x min x qv D E 1 µ D E 0 µ S k Q b Q f I D = G 0 kbt q i g i From x max to x min 1+ exp[ ( µ ] S Ei0) / kbt ln 1+ exp[ ( µ E ) / k T ] D i0 B

46 IV Characteristics of Ballistic SiNW FET V g -V t =1.0 V 0.7 V 0.3 V T=1K T=300K 0.05 V Small temperature dependency 35µA/wire for 4 quantum channels

47 Model of Carrier Scattering Linear Potential Approx. Electric Field E F(0) Elastic Backscatt. Elastic Backscatt. Optical Phonon Emission ε~k B T Source Transmission Probability to Drain G(0) 0 V(x) Channel Initial Elastic Zone T ( ε ) = x 0 F(0) G(0) F(0) Optical Phonon ε * Optical Phonon Emission Zone Injection from Drain= 0 Transmission Probability : T i x To Drain

48 Résumé of the Compact Model q I = gi [ f( ε, µ s) f( ε, µ D) ] Td i ε π h ( V G µ S V ) α t i µ 0 = q Q f + Q C (Electrostatics requirement) G b. µ S µ D = C qv G D = ln C G 2π ε ox 2r + tox + 2r + t ox 2π ε ox = r + t ln r ox t t ox ox.. Planar Gate GAA 0 q dk 1 1 Q + Q = g T( ε ( k)) dk f b π i ( ) ( ) ( ) i i i ε i k µ S ε i k µ S ε i k µ D 1+ exp 1 exp 1 exp + + kt B kt B kt B T ( ε ) = ( ) 2DqE 0 qex0 + ε B0 + D0 + D0 qe+ 2mD0B0ln ε (Carrier distribution in Subbands) Unknowns are I D, (µ S -µ 0 ), (µ D -µ 0 ), (Q f +Q b )

49 I-V D Characteritics (RT) Electric current 25 µa No satruration at Large V D

50 SiNW FET Fabrication

51 SiNW FET Fabrication S/D & Fin Patterning Sacrificial Oxidation 30nm Oixde etch back 30nm SiN sidewall support formation 30nm Gate Oxidation & Poly-Si Deposition Gate Lithography & RIE Etching Gate Sidewall Formation Ni SALISIDE Process (Ni 9nm / TiN 10nm) Backend Standard recipe for gate stack formation

52 (a) SEM image of Si NW FET (Lg = 200nm) (b) high magnification observation of gate and its sidewall. 52

53 Fabricated SiNW FET SiNW SiN support SiN Nanowire Poly-Si 30nm

54 Recent results to be presented by ESSDERC 2010 next week in Sevile Wire cross-section: 20 nm X 10 nm 7.E E E E E E E E+00 (µa)70 Drain Current (a) V g -V th =1.0 V 0.8 V 0.6 V V g -V th = -1.0 V 0.4 V 0.2 V Drain Voltage (V) On/Off> uA/wire 1.E-03 1.E E E E E E E E E Drain Current (A) (b) V d =-1V V d =-50mV pfet nfet Gate Voltage (V) L g =65nm, T ox =3nm V d =1V V d =50mV

55 Bench Mark I ON (µa / wire) nmos pmos (34) (13) (10) 102µA (16) (12) (13x20) (8) (8) (10) (10x20) (9x14) (12) (12x19) (12) (12x19) (10) V DD : 1.0~1.5 V (5) (5) (10) (10) (3) (3) (30) (19) Gate Length (nm) Our Work

56 Bench Mark This work Ref[11] Ref[12] Ref[13] Ref[14] Ref[15] Ref[4] NW Cross-section (nm) Rect. Rect. Rect. Cir. Cir. Elliptical Elliptical NW Size (nm) 10x20 10x x20 Lg (nm) EOT or Tox (nm) Vdd (V) Ion(uA) per wire Ion(uA/um) by dia Ion(uA/um) by cir SS (mv/dec.) ~75 85 DIBL (mv/v) Ion/Ioff ~1E6 >1E6 >1E5 ~1E6 >1E7 >1E7 ~2E5 Ref[11] by Stmicro Lg=25nm,Tox=1.8nm This work Lg=65nm,Tox=3nm

57 I ON /I OFF OFF Bench mark Planer FET V S. Kamiyama, IEDM 2009, p. 431 P. Packan, IEDM 2009, p.659 L g =500 65nm This work Si FET V Y. Jiang, VLSI 2008, p.34 H.-S. Wong, VLSI 2009, p.92 S. Bangsaruntip, IEDM 2009, p.297 C. Dupre, IEDM 2008, p. 749 S.D.Suk, IEDM 2005, p.735 G.Bidel, VLSI 2009, p.240

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59 Electron Density (x10 19 cm -3 ) 6 6.E E E E E E E+00 Edge portion Flat portion Distance from SiNW Surface (nm)

60 Primitive estimation! I ON (µa/µm) P-MOS pmos improvement (26) S/D Low resistance (11) (20) (15) bulk Compact model Small EOT for high-k (33) 1µm # of wires /1µm FD SiNW (12nm 19nm) I ON Nanowire Assumption I ON L g -0.5 T ox -1 ITRS MG Year

61 Our roadmap for R &D Source: H. Iwai, IWJT 2008 Current Issues Si Nanowire Control of wire surface property Source Drain contact Optimization of wire diameter Compact I-V model III-V & Ge Nanowire High-k gate insulator Wire formation technique CNT: Growth and integration of CNT Width and Chirality control Chirality determines conduction types: metal or semiconductor Graphene: Graphene formation technique Suppression of off-current Very small bandgap or no bandgap (semi-metal) Control of ribbon edge structure which affects bandgap 61

62 Thank you for your attention