Past and Future of Mirco/Nano- Electronics

Transcription

1 Past and Future of Mirco/Nano- Electronics December 28, Institute of Technology and Management Bhubaneshwar, Orissa, India Hiroshi Iwai, Tokyo Institute of Technology 1

2 Tokyo Institute of Technology Founded in 1881, Promoted to Univ. 1929

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4 Europe 78 Asia 847 North America 12 Africa 16 Oceania 5 South America 24 Total 982 (As of May. 1, 2005)

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7 Cluster tool for high-k thin film deposition Preparation Room Sputter for metal 5 different target Robot room E-Beam Evaporation 8 different target Flash Lamp Anneal Micro to mille-seconds

8 There were many inventions in the 20 th century: Airplane, Nuclear Power generation, Computer, Space aircraft, etc However, everything has to be controlled by electronics Electronics Most important invention in the 20 th century What is Electronics: To use electrons, Electronic Circuits

9 Electronic Circuits started by the invention of vacuum tube (Triode) in 1906 Lee De Forest Thermal electrons from cathode controlled by grid bias Cathode (heated) Grid Anode (Positive bias) Same mechanism as that of transistor

10 4 wives of Lee De Forest 1906 Lucille Sheardown 1907 Nora Blatch 1912 Mary Mayo, singer 1930 Marie Mosquini, silent film actress Mary Marie 10

11 First Computer Eniac: made of huge number of vacuum tubes 1946 Big size, huge power, short life time filament dreamed of replacing vacuum tube with solid state device Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption 11

12 History of Semiconductor devices 1947, 1 st Point Contact Bipolar Transistor: Ge Semiconductor, Bardeen, Brattin Nobel Prize 1948, 1 st Junction Bipolar Transistor, Ge Semiconductor, Schokley Nobel Prize 1958, 1 st Integrated Circuits, Ge Semiconductor, J.Kilby Nobel Prize 1959, 1 st Planar Integrated Circuits, R.Noice 1960, 1 st MOS Transistor, Kahng, Si Semiconductor 1963, 1 st CMOS Circuits, C.T. Sah and F. Wanlass 12

13 J. E. LILIENFELD DEVICES FOR CONTROLLED ELECTRIC CURRENT Filed March 28, 1928 J.E.LILIENFELD 13

14 Capacitor structure with notch Negative bias No current Gate Electrode Gate Insulator Semiconductor Electron Positive bias Electric field Current flows 14

15 Surface Gate electrode Gate Oxd G Source Channel Drain S D Electron flow 0 bias for gate Positive bias for gate Surface Potential (Negative direction) 0V Negative N + -Si P-Si 1V N-Si Source Channel Drain 0V N + -Si P-Si 1V N-Si Source Channel Drain 15

16 However, no one could realize MOSFET operation for more than 30 years. Because of very bad interface property between the semiconductor and gate insulator Even Shockley! 16

17 Very bad interface property between the semiconductor and gate insulator Interfacial Charges GeO Electric Shielding Ge e Even Shockley! Carrier Scattering Drain Current was several orders of magnitude smaller than expected 17

18 However, they found amplification phenomenon when investigating Ge surface when putting needles. This is the 1 st Transistor: Not Field Effect Transistor, But Bipolar Transistor (another mechanism) 1947: 1 st J. Bardeen W. Bratten, transistor Bipolar using Ge W. Shockley 18

19 1958: 1st Integrated Circuit Jack S. Kilby Connect 2 bipolar transistors in the Same substrate by bonding wire. 19

20 1960: First MOSFET by D. Kahng and M. Atalla Top View Si Source Al Gate Al Drain Si Si/SiO2 Interface is extraordinarily good SiO 2 Si 20

21 1970,71: 1st generation of LSIs DRAM Intel 1103 MPU Intel

22 MOS LSI experienced continuous progress for many years Name of Integrated Circuits Number of Transistors 1960s IC (Integrated Circuits) ~ s LSI (Large Scale Integrated Circuit) ~1, s VLSI (Very Large Scale IC) ~10, s ULSI (Ultra Large Scale IC) ~1,000, s?LSI (? Large Scale IC) ~1000,000,000 22

23 Gate Electrode Poly Si Gate Insulator SiO 2 Substrate Si Use Gate Field Effect for switching Gate Electrode Poly Si Gate Insulator SiO 2 Source e e Drain Channel N MOS (N type MOSFET) Si Substrate 23

24 N MOS (N type MOSFET) Source Gate Electron flow Drain P MOS (P type MOSFET) Source Gate Hole flow Current flow Drain Current flow 24

25 CMOS Complimentary MOS Inverter PMOS NMOS When NMOS is ON, PMOS is OFF When PMOS is ON, NMOS is OFF 25

26 Needless to say, but. CMOS Technology: Indispensible for our human society Al the human activities are controlled by CMOS living, production, financing, telecommunication, transportation, medical care, education, entertainment, etc. Without CMOS: There is no computer in banks, and world economical activities immediately stop. Cellarer phone dose not exists 26

27 Downsizing of the components has been the driving force for circuit evolution Vacuum Transistor IC LSI ULSI Tube 10 cm cm mm 10 µm 100 nm 10-1 m 10-2 m 10-3 m 10-5 m 10-7 m In 100 years, the size reduced by one million times. There have been many devices from stone age. We have never experienced such a tremendous reduction of devices in human history. 27

28 Downsizing 1. Reduce Capacitance Reduce switching time of MOSFETs Increase clock frequency Increase circuit operation speed 2. Increase number of Transistors Parallel processing Increase circuit operation speed Downsizing contribute to the performance increase in double ways Thus, downsizing of Si devices is the most important and critical issue. 28

29 Scaling Method: by R. Dennard in S 1 Wdep 1 1 D Wdep: Space Charge Region (or Depletion Region) Width Wdep has to be suppressed Otherwise, large leakage between S and D I Leakage current K=0.7 for example K K Wdep Potential in space charge region is high, and thus, electrons in source are attracted to the space charge region. X, Y, Z : K, V : K, Na : 1/K K Wdep V/Na : K I K 0 0 K V 0 0 V 1 By the scaling, Wdep is suppressed in proportion, and thus, leakage can be suppressed. Good scaled I-V characteristics I : K 29 29

30 Downscaling merit: Beautiful! Geometry & Supply voltage L g, W g T ox, V dd K Scaling K : K=0.7 for example Drive current in saturation I d K I d = v sat W g C o (V g V th ) C o : gate C per unit area W g (t 1 ox )(V g V th )= W g t 1 ox (V g V th )= KK 1 K=K I d per unit W g I d /µm 1 I d per unit W g = I d / W g = 1 Gate capacitance C g K C g = ε o ε ox L g W g /t ox KK/K = K Switching speed τ K τ= C g V dd /I d KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area A chip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/k 2 N α/k 2 = 1/K 2, when α=1 Power per chip P α fncv 2 /2 K 1 (αk 2 )K (K 1 ) 2 = α = 1, when α=

31 k= 0.7 and α =1 Single MOFET Vdd 0.7 Lg 0.7 Id 0.7 Cg 0.7 P (Power)/Clock 0.73 = 0.34 τ (Switching time) 0.7 Chip N (# of Tr) 1/0.7 2 = 2 f (Clock) 1/0.7 = 1.4 P (Power) 1 k= =0.5 and α =1 Vdd 0.5 Lg 0.5 Id 0.5 Cg 0.5 P (Power)/Clock = τ (Switching time) 0.5 N (# of Tr) 1/0.5 2 = 4 f (Clock) 1/0.5 = 2 P (Power)

32 Actual past downscaling trend until year 2000 Minimum logic V dd (V) I d /µm (ma/µm) MPU L g (µm) X j (µm) tox (µm) chip size mm 2 clock frequency (MHz) MIPS power (W) Number of transistors Source. Iwai and S. Ohmi, Microelectronics Reliability 42 (2002), pp Change in 30 years Ideal scaling Real Change Ideal scaling Real Change Past 30 years scaling Merit: Ideal scaling N, f increase Demerit: P increase V dd scaling insufficient Additional significant increase in I d, f, P Real Change L g K 10 2 t ox K(10 2 ) 10 2 V dd K(10 2 ) 10 1 A chip α 10 1 I d I d /µm K (10 2 ) 10 1 f 1/K(10 2 ) N α/k 2 (10 5 ) 10 4 P α(10 1 ) 10 5 = fαncv 2 Vd scaling insufficient, α increased N, Id, f, P increased significantly 32 32

33 Many people wanted to say about the limit. Past predictions were not correct!! Period Expected Cause limit(size) Late 1970 s 1µm: SCE Early 1980 s 0.5µm: S/D resistance Early 1980 s 0.25µm: Direct tunneling of gate SiO 2 Late 1980 s 0.1µm: 0.1µm brick wall (various) nm: Red brick wall (various) nm: Fundamental? 33

34 Historically, many predictions of the limit of downsizing. VLSI text book written 1979 predict that 0.25 micrometer would be the limit because of directtunneling current through the very thin gate oxide.

35 C. Mead L. Conway 35

36 VLSI textbook Finally, there appears to be a fundamental limit 10 of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide... begin to make the devices of smaller dimension unworkable. 36

37 Direct tunneling effect Gate Electrode Wave function Gate Oxide Potential Barrier Si Substrate Direct tunneling current Gate Oxide G S D Direct tunneling leakage current start to flow when the thickness is 3 nm. 37

38 Gate electrode Lg Gate oxide Si substrate S MOSFETs with 1.5 nm gate oxide G D Direct tunneling leakage was found to be OK! In 1994! Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm 0.03 Vg = 2.0V Vg = 2.0V 0.3 Vg = 2.0V 1.2 Vg = 2.0V 1.5 V 1.5 V 1.5 V 1.5 V Id (ma / m) V 0.5 V 0.0 V V 0.5 V 0.0 V V 0.5 V 0.0 V V 0.5 V 0.0 V Vd (V) Vd (V) Vd (V) Vd (V) 38

39 S G Ig Gate leakage: Ig Gate Area Gate length (Lg) D Id Drain current: Id 1/Gate length (Lg) Lg small, Then, Ig small, Id large, Thus, Ig/Id very small Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm 0.03 Vg = 2.0V Id Id (ma / m) V 1.0 V 0.5 V 0.0 V Vg = 2.0V 1.5 V 1.0 V 0.5 V 0.0 V Vg = 2.0V 1.5 V 1.0 V 0.5 V 0.0 V Vg = 2.0V 1.5 V 1.0 V 0.5 V 0.0 V Vd (V) Vd (V) Vd (V) Vd (V)

40 Do not believe a text book statement, blindly! Never Give Up! No one knows future! There would be a solution! Think, Think, and Think! Or, Wait the time! Some one will think for you 40

41 41 Qi Xinag, ECS 2004, AMD

42 Downsizing limit? Channel length? 10 nm Electron wave length Gate Oxd Channel 42

43 5 nm gate length CMOS Is a Real Nano Device!! 5nm Length of 18 Si atoms H. Wakabayashi et.al, NEC IEDM,

44 Electron wave length 10 nm Downsizing limit! Channel length Gate oxide thickness Tunneling distance 3 nm Gate Oxd Channel 44

45 Prediction now! Electron wave length 10 nm Tunneling distance 3 nm Atom distance 0.3 nm MOSFET operation Lg = 2 ~ 1.5 nm? Below this, no one knows future! 45

46 Ultimate limitation Size (µm), Voltage(V) MPU Lg Junction depth ITRS Roadmap (at introduction) Gate oxide thickness Min. V supply However,Gate oxide thickness 2 orders magnitude smaller Close to limitation!! 10 nm Wave length of electron 3 nm Direct-tunneling 0.3 nm Distance between Si atoms ULTIMATE LIMIT Lg: Gate length downsizing will continue to another years 46

47 0.8 nm Gate Oxide Thickness MOSFETs operates!! 0.8 nm: Distance of 3 Si atoms!! 47 By Robert Chau, IWGI 2003

48 So, we are now in the limitation of downsizing? Do you believe this or do not? 48

49 There is a solution! K: Dielectric Constant To use high k dielectrics Thin gate SiO 2 Thick gate high k dielectrics Thick Almost the same electric characteristics Small leakage Current However, very difficult and big challenge! Remember MOSFET had not been realized without Si/SiO 2! 49

50 Choice of High-k elements for oxide Gas or liquid at 1000 K Radio active He B C N O F Ne Unstable at Si interface H Si + MO X M + SiO 2 Li Be Si + MO X MSi X + SiO 2 Na Mg Si + MO X M + MSi X O Y Al Si P S Cl Ar Ca K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe Cs Ba Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn Fr Ra Rf Ha Sg Ns Hs Mt Candidates La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Y Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr R. Hauser, IEDM Short Course, 1999 Hubbard and Schlom, J Mater Res (1996) HfO 2 based dielectrics are selected as the first generation materials, because of their merit in 1) band-offset, 2) dielectric constant 3) thermal stability La 2 O 3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer 50

51 Conduction band offset vs. Dielectric Constant Leakage Current by Tunneling Band offset Si Oxide SiO 2 Band Discontinuity [ev] Dielectric Constant XPS measurement by Prof. T. Hattori, INFOS

52 PMOS High k gate insulator MOSFETs for Intel: EOT=1nm EOT: Equivalent Oxide Thickness 52

53 Power per MOSFET (P) (Scaling) P L g 3 For the past 45 years SiO2 and SiON For gate insulator Today EOT=1.0nm EOT Limit 0.7~0.8 nm One order of Magnitude 45nm node L g =22nm EOT=0.5nm Metal SiO 2 /SiON Si Metal HfO 2 SiO 2 /SiON Si nm Introduction of High-k Still SiO2 or SiON Is used at Si interface Metal High-k Si Direct Contact Of high-k and Si EOT can be reduced further beyond 0.5 nm by using direct contact to Si By choosing appropriate materials and processes. Now Year 53

54 SiO x -IL growth at HfO 2 /Si Interface TEM image 500 o C 30min Intensity (a.u) o C Hf Silicate SiO 2 Si sub Binding energy (ev) Phase separator XPS Si1s spectrum nm W HfO 2 SiO x -IL k=16 k=4 HfO 2 + Si + O 2 HfO 2 + Si + 2O* HfO 2 +SiO 2 SiO x -IL is formed after annealing H. Shimizu, JJAP, 44, pp Oxygen supplied from W gate electrode D.J.Lichtenwalner, Tans. ECS 11, 319 Oxygen control is required for optimizing the reaction 54

55 Choice of High-k elements for oxide Gas or liquid at 1000 K Radio active He B C N O F Ne Unstable at Si interface H Si + MO X M + SiO 2 Li Be Si + MO X MSi X + SiO 2 Na Mg Si + MO X M + MSi X O Y Al Si P S Cl Ar Ca K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe Cs Ba Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn Fr Ra Rf Ha Sg Ns Hs Mt Candidates La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er Tm Y Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr R. Hauser, IEDM Short Course, 1999 Hubbard and Schlom, J Mater Res (1996) HfO 2 based dielectrics are selected as the first generation materials, because of their merit in 1) band-offset, 2) dielectric constant 3) thermal stability La 2 O 3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer 55

56 La-Silicate Reaction at La 2 O 3 /Si Direct contact high-k/si is possible Intensity (a.u) as depo. 300 o C 500 o C XPS Si1s spectra La-silicate Si sub. TEM image 500 o C, 30 min 1 nm W La 2 O 3 La-silicate k=23 k=8~ Binding energy (ev) 1837 La 2 O 3 + Si + no 2 La 2 SiO 5, La 2 Si 2 O 7, La 9.33 Si 6 O 26, La 10 (SiO 4 ) 6 O 3, etc. La 2 O 3 can achieve direct contact of high-k/si 56

57 Current density ( A/cm 2 ) Gate Leakage vs EOT, (Vg= 1 V) Al2O3 1.E+01 HfAlO(N) HfO2 HfO2 1.E+00 HfSiO(N) HfTaO La2O3 La2O3 1.E-01 Nd2O3 Pr2O3 1.E-02 PrSiO PrTiO 1.E-03 SiON/SiN Sm2O3 1.E-04 SrTiO3 Ta2O5 TiO2 1.E-05 ZrO2(N) ZrSiO EOT ( nm ) ZrAlO(N) 57

58 Quantum Effect in Gate Stack Gate metal Charge layer capacitance Thickness shown in EOT Poly-Si(10 20 cm -3 ): 0.3 nm Metal : 0.1 nm K. Natori, SSDM (2005) High-k Gate oxide capacitance High-k (EOT) Si sub. channel Inversion layer capacitance 0.5 ~ 0.6 nm depending on E eff S. Takagi, TED, 46. pp.1446 (1999) Total parasitic capacitance ~ 0.6nm of EOT A question if the performance improvement can be obtained with EOT<0.5nm Is EOT<0.5nm achievable? 58

59 EOT = 0.48 nm Our results Transistor with La2O3 gate insulator 59

60 EOT=0.37nm La2O3 EOT=0.37nm EOT=0.40nm EOT=0.48nm I d (V) 3.5E E E E E-03 Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V W/L = 50µm /2.5µm Vth=-0.06V Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V W/L = 50µm /2.5µm Vth=-0.05V Vg=0V Vg=0.2V Vg=0.4V Vg=0.6V Vg=0.8V Vg=1.0V Vg=1.2V W/L = 50µm /2.5µm Vth=-0.04V 1.0E E E V d (V) V d (V) V d (V) nm Increase of Id at 30% 60

61 µ eff of W/La 2 O 3 and W/HfO 2 nfet on EOT µ eff (cm 2 /Vs) EOT=0.5nm 50 Open: peak mobility Fill: 0.8MV/cm 500 o C annealed W/La 2 O 3 W/La 2 O o C EOT (nm) W/HfO o C annealed W/La 2 O 3 exhibits higher µ eff than W/HfO 2 µ eff start degrades below EOT=1.4nm 61

62 FET characteristics of W/La 2 O 3 on EOT S.S (mv/dec) D it (ev -1 cm -2 ) V fb, V th (V) W/L g =50µm/2.5µm CP@1MHz V d =50mV EOT (nm) N fix =7x10 12 cm -2 Aggressive N fix generation at EOT<1.2nm metal Si sub. N fix and D it All characteristics start to degrade or shift below EOT=1.4nm 62

63 Gate Metal Induced Defects Compensation Metal Gate MgO La2O3 Si W Si TEM 2nm Mg EDX W La Si a.u. Vfb (V) w/ Mg w/o Mg PMA500 o C EOT (nm) Suppression of aggressive shift in V fb 63

64 Mobility Improvement with Mg Incorporation µ eff (cm 2 /Vs) w/ Mg (EOT=1.09nm) universal w/o Mg (EOT=1.04nm) 50 PMA500 o C Recovery of µ eff mainly at low E eff 64

65 6 µm NMOS LSI in 1974 Si substrate Passivation (PSG) Al interconnects ILD (Interlayer Dielectrics) (SiO 2 + BPSG) magnification Poly Si gate electrode Gate SiO 2 Source / Drain Layers 1. Si substrate 2. Field oxide 3. Gate oxide 4. Poly Si 5. S/D 6. Interlayer 7. Aluminum 8. Passivation Materials 1. Si 2. SiO 2 3. BPSG 4. Al 5. PSG Field SiO 2 Atoms 1. Si 2. O 3. P 4. B 5. Al (H, N, Cl) 65

66 New materials Just examples! Many other candidates Ge III-V Semiconductors NiSi silicide La 2 O 3 Ta 2 O 5 Al SiO 2 Si Al SiO 2 Si Si 3 N 4 Poly Si PtSi 2 WSi 2 CoSi 2 TiSi 2 MoSi 2 TaSi 2 Silicides SiGe Semiconductor Air HSQ Polymer TiN TaN Cu W Low-k dielectrics Metals HfO 2 ZrO 2 ZrSi x O y RuO 2 Pt IrO 2 Y1 PZT BST High-k dielectrics Electrode materials Ferroelectrics Y. Nishi, Si Nano Workshop, 2006, (S. Sze, Based on invited talk at Stanford Univ., Aug. 1999) 66

67 What is a roadmap? What is ITRS? Roadmap: Prediction of future technologies ITRS: International Technology Roadmap for Semiconductors made by SIA (Semiconductor Industry Association with Collaboration with Japan, Europe, Korea and Taiwan) Physical Gate Length [nm] nm 10 Gate length EOT [nm] nm Gate oxide thickness

68 :NTRS (National Technology Roadmap) : ITRS (International Technology Roadmap) 2007 ITRS 2006 ITRS update 2008 ITRS update

69 Question: How far we can go with downscaling?

70 -There will be still 4~6 cycles (or technology generations) left until we reach 11 ~ 5.5 nm technologies, at which we will reach downscaling limit, in some year between (H. Iwai, IWJT2008). -Even After reaching the down-scaling limit, we could still continue R & D, seeking sufficiently higher Id-sat under low Vdd. -Two candidates have emerged for R & D 1. Nanowire/tube MOSFETs 2. Alternative channel MOSFETs (III-V, Ge) - Other Beyond CMOS devices are still in the cloud. 5.5nm?* 3 important innovations ITRS figure edited by Iwai Source: 2008 ITRS Summer Public Conf. *5.5nm? was added by Iwai 70 70

71 How far can we go? Past µm 6µm 4µm 3µm 2µm 1.2µm 0.8µm 0.5µm 0.35µm 0.25µm 180nm 130nm 90nm 65nm 45nm Future 0.7 times per 3 years In 40 years: 15 generations, Size 1/200, Area 1/40,000 Now 32nm 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm? At least 5,6 generations, for 15 ~ 20 years Hopefully 8 generations, for 30 years

72 HP, LOP, LSTP for Logic CMOS 100 e) Operation Frequency (a.u.) 10 1 Subthreshold Leakage (A/µm) Source: 2007 ITRS Winter Public Conf. 72

73 Because of off-leakage control, Planar Nanowire S Wdep 1 D Leakage current Source Gate Drain Planar FET Fin FET Nanowire FET

74 Nanowire FET Multiple Gate (Fin)FET Nanowire FET ITRS 2009 Bulk Fin Nanowire Bulk or SOI Fin Si Si Nanowire

75 Si nanowire FET as a strong candidate 1. Compatibility with current CMOS process 2. Good controllability of I OFF S Leakage current Wdep 1 D cut-off Off 3. High drive current source Drain Gate:OFF Gate: OFF drain Source 1D ballistic conduction Multi quantum Channel E Quantum channel Quantum channel Quantum channel k Quantum channel High integration of wires 75

76 Ioff (na/um) Off Current DG ITRS (Bulk) ITRS (SOI) ITRS (DG) dia~10nm bulk FinFET SiNWFET GeNWFET ITRS(Planer) ITRS(SOI) ITRS(DG) 10 Bulk Si Nanowire dia~3nm Ion (ua/um) 76

77 Increase the Number of quantum channels By Prof. Shiraishi of Tsukuba univ. 4 channels can be used Eg Eg Energy band of Bulk Si Energy band of 3 x 3 Si wire 77

78 Maximum number of wires per 1 µm Front gate type MOS 165 wires /µm 6nm 6nm pitch By nano-imprint method Metal gate electrode(10nm) Surrounded gate type MOS 33 wires/µm 30nm High-k gate insulator (4nm) Si Nano wire (Diameter 2nm) 30nm pitch: EUV lithograpy Surrounded gate MOS 78

79 Si/Si 0.8 Ge 0.2 superlattice epitaxy on SOI SiN HM SiN SiGe Si SiGe Si SiGe Si BOX Device fabrication Anisotropic etching of these layers BOX Isotropic etching of SiGe BOX ( ) The NW diameter is controllable down to 5 nm by self limited oxidation. Gate depositions HfO 2 (3nm) TiN (10nm) Poly-Si (200nm) Gate Gate etching Gate S/D implantation Spacer formation Activation anneal Salicidation Standard Back-End of-line Process BOX BOX Process Details : C. Dupre et al., IEDM Tech. Dig., p.749,

80 3D-stacked Si NWs with Hi-k/MG Top view Cross-section SiN HM Source Gate Drain 500 nm <110> Wire direction : <110> 50 NWs in parallel 3 levels vertically-stacked Total array of 150 wires EOT ~2.6 nm 50nm NWs BOX 8

81 SiNW Band structure calculation

82 Cross section of Si NW First principal calculation, D=1.96nm D=1.94nm D=1.93nm [001] [011] [111]

83 Si nanowire FET with 1D Transport Orientation [001] [011] [111] Diameter (nm) Energy (ev) 0-1 G Z G Z G Wave Number (a) Orientation Diameter (nm) 1 Energy (ev) 0 0 [001] [011] [111] G Z G Z G Wave Number (b) Z Z Small mass with [011] Large number of quantum channels with [001]

84 Atomic models of a Si quantum dot and Si nanowires 6.6 nm diameter SiQD 8651 atoms 20 nm diameter Si(100)NW 8941 atoms 10 nm diameter Si(100)NW 2341 atoms

85 RSDFT suitable for parallel first-principles calculation - Real-Space Finite-Difference Higher-order finite difference pseudopotential method Sparse Matrix J. R. Chelikowsky et al., Phys. Rev. B, (1994) FFT free (FFT is inevitable in the conventional plane-wave code) MPI ( Message Passing Interface ) library Kohn-Sham eq. (finite-difference) 3D grid is divided by several regions for parallel computation. 1 2 [ ]( r PP + v ) ˆ ( r ) ( r ) ( r s ρ + v nloc φn = ε nφn ) 2 CPU6 CPU7 CPU8 Higher-order finite difference n m n x ψ ψ m= 6 ( x, y, z) C ( x+ m x, y, z) CPU3 CPU4 CPU5 MPI_ISEND, MPI_IRECV CPU0 CPU1 CPU2 Integration Mesh ψ () rψ () r dr ψ ( r) ψ ( r) x y z m n m i n i i= 1 MPI_ALLREDUCE

86 Massively Parallel Computing Based on the finite-difference pseudopotential method (J. R. Chelikowsky et al., PRB1994) Highly tuned for massively parallel computers with our recently developed code RSDFT Iwata et al, J. Comp. Phys., to be published Real-Space Density-Functional Theory code (RSDFT) Computations are done on a massively-parallel cluster PACS-CS at University of Tsukuba. (Theoretical Peak Performance = 5.6GFLOPS/node) e.g.) The system over 10,000 atoms Si H 1996 (7.6 nm diameter Si dot) Convergence behavior for Si H 1996 Grid points = 3,402,059 Bands = 22,432 Computational Time (with 1024 nodes of PACS-CS 6781 sec. 60 iteration step = 113 hour

87 (ev) (ev) Band Structure and DOS of Si(100)NWs (D=1nm, 4nm, and 8nm) D=1nm D=4nm (ev) (ev) (ev) (ev) D=8nm DOS ( States / ev atom ) (ev) DOS ( States / ev atom ) (ev) DOS ( States / ev atom ) (ev) D=1 nm Si21H20 41 atoms) KS band gap=2.60ev D = 4 nm Si341H atoms) KS band gap = 0.81eV D=8 nm Si1361H164 (1525 atoms) KS band gap=0.61ev KS band gap of bulk (LDA) = 0.53eV

88 Band structure of 8-nm-diameter Si nanowire near the CBM KS band gap = ev (@Γ) Each band is 4-dgenerate. (ev) mev (96 mev) 23 mev (24 mev) kx kz ky kx Effective mass equation 2 h 2m * t x y h 2m * l z 2 2 Φ( r) = ( ε ε CBM ) Φ( r) The band structure can be understood that electrons near the CBM in the bulk Si are Confined within a cylindrical geometry.

89 Si nano wire with surface roughness Si12822H1544 Top View Side View Si12822H ,366 atoms 10nm diameter 3.3nm height (100) Grid spacing 0.45Å (~14Ry) # of grid points 4,718,592 # of bands 29,024 Memory 1,022GB 2,044GB

90 SiNW Band compact model

91 Landauer Formalism for Ballistic FET Q f Q b Energy µ S E 2max µ D E 2min E 2min O x max x min x qv D E 1 µ D E 0 µ S k Q b Q f I D = G 0 kbt q i g i From x max to x min 1+ exp[ ( µ ] S Ei0) / kbt ln 1+ exp[ ( µ E ) / k T ] D i0 B

92 IV Characteristics of Ballistic SiNW FET V g -V t =1.0 V 0.7 V 0.3 V T=1K T=300K 0.05 V Small temperature dependency 35µA/wire for 4 quantum channels

93 Model of Carrier Scattering Linear Potential Approx. Electric Field E F(0) Elastic Backscatt. Elastic Backscatt. Optical Phonon Emission ε~k B T Source Transmission Probability to Drain G(0) 0 V(x) Channel Initial Elastic Zone T ( ε ) = x 0 F(0) G(0) F(0) Optical Phonon ε * Optical Phonon Emission Zone Injection from Drain= 0 Transmission Probability : T i x To Drain

94 Résumé of the Compact Model q I = gi [ f( ε, µ s) f( ε, µ D) ] Td i ε π h ( V G µ S V ) α t i µ 0 = q Q f + Q C (Electrostatics requirement) G b. µ S µ D = C qv G D = ln C G 2π ε ox 2r + tox + 2r + t ox 2π ε ox = r + t ln r ox t t ox ox.. Planar Gate GAA 0 q dk 1 1 Q + Q = g T( ε ( k)) dk f b π i ( ) ( ) ( ) i i i ε i k µ S ε i k µ S ε i k µ D 1+ exp 1 exp 1 exp + + kt B kt B kt B T ( ε ) = ( ) 2DqE 0 qex0 + ε B0 + D0 + D0 qe+ 2mD0B0ln ε (Carrier distribution in Subbands) Unknowns are I D, (µ S -µ 0 ), (µ D -µ 0 ), (Q f +Q b )

95 I-V D Characteritics (RT) Electric current 25 µa No satruration at Large V D

96 SiNW FET Fabrication

97 SiNW FET Fabrication S/D & Fin Patterning Sacrificial Oxidation 30nm Oixde etch back 30nm SiN sidewall support formation 30nm Gate Oxidation & Poly-Si Deposition Gate Lithography & RIE Etching Gate Sidewall Formation Ni SALISIDE Process (Ni 9nm / TiN 10nm) Backend Standard recipe for gate stack formation

98 (a) SEM image of Si NW FET (Lg = 200nm) (b) high magnification observation of gate and its sidewall. 98

99 Fabricated SiNW FET SiNW SiN support SiN Nanowire Poly-Si 30nm

100 Recent results to be presented by ESSDERC 2010 next week in Sevile Wire cross-section: 20 nm X 10 nm 7.E E E E E E E E+00 (µa)70 Drain Current (a) V g -V th =1.0 V 0.8 V 0.6 V V g -V th = -1.0 V 0.4 V 0.2 V Drain Voltage (V) On/Off> uA/wire 1.E-03 1.E E E E E E E E E Drain Current (A) (b) V d =-1V V d =-50mV pfet nfet Gate Voltage (V) L g =65nm, T ox =3nm V d =1V V d =50mV

101 Bench Mark I ON (µa / wire) nmos pmos (34) (13) (10) 102µA (16) (12) (13x20) (8) (8) (10) (10x20) (9x14) (12) (12x19) (12) (12x19) (10) V DD : 1.0~1.5 V (5) (5) (10) (10) (3) (3) (30) (19) Gate Length (nm) Our Work

102 Bench Mark This work Ref[11] Ref[12] Ref[13] Ref[14] Ref[15] Ref[4] NW Cross-section (nm) Rect. Rect. Rect. Cir. Cir. Elliptical Elliptical NW Size (nm) 10x20 10x x20 Lg (nm) EOT or Tox (nm) Vdd (V) Ion(uA) per wire Ion(uA/um) by dia Ion(uA/um) by cir SS (mv/dec.) ~75 85 DIBL (mv/v) Ion/Ioff ~1E6 >1E6 >1E5 ~1E6 >1E7 >1E7 ~2E5 Ref[11] by Stmicro Lg=25nm,Tox=1.8nm This work Lg=65nm,Tox=3nm

103 I ON /I OFF OFF Bench mark Planer FET V S. Kamiyama, IEDM 2009, p. 431 P. Packan, IEDM 2009, p.659 L g =500 65nm This work Si FET V Y. Jiang, VLSI 2008, p.34 H.-S. Wong, VLSI 2009, p.92 S. Bangsaruntip, IEDM 2009, p.297 C. Dupre, IEDM 2008, p. 749 S.D.Suk, IEDM 2005, p.735 G.Bidel, VLSI 2009, p.240

104

105 Electron Density (x10 19 cm -3 ) 6 6.E E E E E E E+00 Edge portion Flat portion Distance from SiNW Surface (nm)

106 Primitive estimation! I ON (µa/µm) P-MOS pmos improvement (26) S/D Low resistance (11) (20) (15) bulk Compact model Small EOT for high-k (33) 1µm # of wires /1µm FD SiNW (12nm 19nm) I ON Nanowire Assumption I ON L g -0.5 T ox -1 ITRS MG Year

107 Our roadmap for R &D Source: H. Iwai, IWJT 2008 Current Issues Si Nanowire Control of wire surface property Source Drain contact Optimization of wire diameter Compact I-V model III-V & Ge Nanowire High-k gate insulator Wire formation technique CNT: Growth and integration of CNT Width and Chirality control Chirality determines conduction types: metal or semiconductor Graphene: Graphene formation technique Suppression of off-current Very small bandgap or no bandgap (semi-metal) Control of ribbon edge structure which affects bandgap 107

108 Thank you for your attention! 108