Department of Electronic Engineering, Chienkuo Technology University, No. 1, Chieh Shou N. Rd., Changhua City, 500 Taiwan, R.O.C.

Transcription

1 Typeset using jjap.cls <ver.1.0.1> Compact Hot-Electron Induced Oxide Trapping Charge and Post- Stress Drain Current Modeling for Buried-Channel p-type Metal- Oxide-Semiconductor-Field-Effect-Transistors Chorng-Jye Sheu Department of Electronic Engineering, Chienkuo Technology University, No. 1, Chieh Shou N. Rd., Changhua City, 500 Taiwan, R.O.C. (Received ) In this paper, we present a complete and physics-based drain current model for hotcarrier damaged buried-channel (BC) p-type metal-oxide-semiconductor-field-effect-transistors (pmosfets) operated in the forward and reverse-biased modes. Experimentally it was found that the post-stress drain current of BC pmosfets increases, this is caused by hotcarrier-induced electron trapping in the oxide. Considering the subthreshold operation, we present an complete electron gate current model and calculate the spatial distribution of oxide-trapping-charges by using an oxide trapping mechanism, and then we can model the hot-carrier damaged drain current by substituting the spatial distribution of oxide-trapping-charges into the damaged BC MOSFET drain current model. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias and stress-time-dependent resistance. The degraded BC MOSFET drain current model is applicable for circuit simulation and its accuracy has been verified by experimental data. KEYWORDS: hot carriers, lifetime, trapping, tunneling, thermionic emission, MOSFET address: cjsheu@ctu.edu.tw 1

2 1. Introduction In p-type metal-oxide-semiconductor-field-effect-transistors (pmosfets), the effect of channel shortening induced by oxide trapped electrons 1,2) is the main cause of device degradation. The oxide trapped electrons attract holes to the semiconductor surface and invert the channel from an n- to a p-channel, this results in current enhancement and frequency shift of ring oscillator, and may play a fundamental limitation in the longterm reliability of very-large-scale-integration/ultra-large-scale-integration (VLSI/ULSI) circuits. 3) That the electrons traversing the gate oxide get trapped in the oxide is responsible for the above-mentioned channel shortening effect. Similarly, in buried-channel (BC) pmosfets, it was found experimentally that the post-stress drain current increases. This indicates that electron injection is the dominant mechanism for pmos degradation in BC devices. It is widely recognized that the pmos hot-carrier degradation has a close correlation with the electron gate current injection, which normally happens at high V DS and low V GS ( V T ). Therefore it is essential to have an accurate gate current injection model for predicting the pmos hot-carrier lifetime at operation conditions. 4) To model the substrate and gate current at low V GS, a drain current model valid in subthreshold region should be used. The subthreshold model is important for low-voltage and analog circuit simulation. The purpose of this paper is to develop a hot-carrier damaged BC pmosfet drain current model based on the electron gate current and an oxide trapping mechanism, which has not been done yet, and to study the related device physics. This model is valid in all regions of operation for a pmosfet operated in forward- and reverse-mode. To obtain this model, the spatial distribution of hot-carrier-induced oxidetrapping-charges must be calculated, because so far no explicit determination method for oxide-trapping-charges in BC pmosfets has been reported. To achieve this goal, we develop an electron gate current model in conjunction with an oxide-trapping-charge generation model. The calculated hot-carrier-induced oxide-trapping-charge density will be inserted into the damaged BC pmosfet model to calculate the post-stress drain current. The device physics of hot-carrier-damaged BC pmosfets can therefore be explicitly explained with our simulation results. 2

3 2. Model Development In the previous work, 5) a complete post-stress BC pmosfet model has been developed. In this section we first adopt this pre- and post-stress drain current model for BC pmosfet shown in Fig. 1 to calculate fresh drain current and channel electric field. To calculate the hot-carrier-damaged drain current, we assume that the spatial distribution of hot-carrier-induced negative oxide trapping charge density, N ot, is shown in Fig. 1, where L ox is the length of hot-carrier induced oxide-trapping charges and N o is the maximum oxide-trapping-charge density as well as the concentration of available traps. We will develop an electron gate current model and use an oxide trapping mechanism to obtain the spatial distribution of hot-carrier-induced negative oxide trapping charge later. By using the N ot shown in Fig. 1, we develop a post-stress drain current for BC pmosfets, where N ot, solved from a first-order rate equation, can be calculated with I DS simultaneously. In what follows, we first calculate the spatial varying electric field along the channel and the drain current, I DS, 5) then we develop the expression of nonlocal impact ionization coefficient and formulate the substrate current model in 2.1 and the tunneling probability useful for the lucky electron model and the gate current model in 2.2. Finally, the electron trapping theory will be described in 2.3 and the post stress drain current model in Substrate current model From refs. 6 and 7, the non-local impact ionization coefficient can be re-expressed as { α (y) = γ l s exp β ( λ )} 0, (2.1) E y l s where y is the direction along the channel, E y is the channel electric field, γ and β 0 are constant, and λ 0 is the energy relaxation length. The characteristic length, l s, is given by ε s (X I + X P0 ) l s =, (2.2) C o ξ s η o where ε s is the permittivity of silicon, X I and X P0 are the depths of implanted channel and depletion region in the substrate, C o is the gate oxide capacitance per unit area, ξ s is a fitting constant, and η o is defined as in ref. 5. According to the non-local impact 3

4 ionization coefficient described in eq. (2.1), the non-local substrate current shown in Fig. 1 can be derived as L I sub = I DS α (y)dy, (2.3) where L is the channel length and I DS is the drain current of buried-channel pmosfet Gate current model Recently we have developed a non-local gate current model for calculating the electron gate currents in silicon-on-insulator pmosfets. 8) Now we extend the equations in ref. 8 to describe the electron gate current in buried-channel pmosfets. The electron gate current for BC pmosfets can be written as I ge = W L 0 J g dy, (2.4) where W is the channel width, L is the whole channel length, and J g is the electron gate current density. The holes in the channel are accelerated by the channel electric field to initiate the electron-hole pair generation, and the hot-hole loses its kinetic energy during the impact-ionization process and flows to the drain. The impact-generated electrons flow to the source, and part of them are injected into the gate oxide becoming electron gate current. The lucky electron model for channel electron injection is based on a number of probabilistic arguments shown in Fig. 1. We can refer to Fig. 2 where a qualitative energy band diagram for electron tunneling after the pinchoff point is shown. The modified lucky electron gate current density, J g, for drain avalanche hot carrier injection (DAHCI) is given by J g = I sub W P 2P 3 0 P 1e P ox de, (2.5) where P 2 is the re-direction probability of an electron per unit length, P 3 is a scattering probability factor weighted by the electron concentration in the channel, P 1e is the probability that an electron with energy between E and E + de, and P ox is the probability that electrons can arrive at the gate electrode from Si/SiO 2 interface. 2.3 Electron trapping theory It was pointed out in ref. 9 that the accumulation of the trapped electrons in the gate oxide can be modeled by the logarithmic growth of a region of filled traps from the drain 4

5 junction toward the source. The region saturated with the trapped electrons is given by [ L ox (t) = l ox ln 2.2 J ] g (y = 0) σ t, (2.6) q where l ox, q, y, σ, and t are the characteristic decay length, elementary charge, distance from drain, capture cross section, and stress time, respectively. The spatial distribution of hot-carrier induced negative oxide trapping charge density, N ot, can be describe as { [ N ot (y,t) = N o 1 exp J g(y = 0) σ t exp ( y q l ox )]}, (2.7) where J g (y = 0) represents the injection current at the drain edge. We can model the hot-carrier damaged drain current by substituting eqs. (2.6) and (2.7) into the damaged BC MOSFET drain current model. 2.4 Post stress drain current model To calculate the drain current, we must calculate the free channel charge density in the undamaged channel. The effective free charge density which is valid in subthreshold, near threshold, and above threshold regions as in dealing with surface-channel MOSFET complete I V model can be given by 5) where Q m = C o η V t ln{ η V t exp[ V GB (VGBT V T ) V CS ]}, η V t η = γ C κ 0 η s + n x L ox L 1 + ζ 1 exp( V GB V GBT n m1 V t ) η x (2.8) (2.9) ζ 1 exp( V GBT V GB n m1 V t ), and VGBT, V T, η x are the effective threshold gate voltage, the effective threshold voltage reduction, the channel-voltage dependent factor for the expression Q m, respectively. In eq. (2.8), γ C = 2qǫ s N C /C o, V t is the thermal voltage, and V CS is the channel-source Fermi-potential. N C is the doping concentration of implanted channel. In eq. (2.9), η s, the subthreshold swing, is given by ref. 5 and κ 0, n x, ζ 1, and n m1 are fitting constants. κ 0 is introduced to improve the accuracy of the subthreshold condition. n x is used to 5

6 describe the relation between the traps occupied length and subthreshold swing. n m1 and ζ 1 are used to improve the transition from below to above-threshold condition. V GBT is the threshold voltage of long channel device. In above-threshold condition, eq. (2.8) is reduced to Q m = C o [V GB (V GBT V T ) η x V CS ]. (2.10) In subthreshold condition, eq. (2.8) is reduced to Q m = 4 3 C oγ C Vt exp[ V GB (V GBT V T ) η s V CS ]. η s V t Now we can get the drain current: (2.11) I DS = A y A 2 y 4A x A z 2A x, (2.12a) where A x = WC o µη (R S + R D ) R S R D 2 + R S + R D E sat A y = WC o µ(r S + R D )[V GB V on +η (V t R D R S + R D V DS )] (2.12b) (L L ox + V DS E sat ) A z = WC o µ[v GB V on + η (V t 1 2 V DS)]V DS. R S, the series source resistance, is equal to R S0 /(R S0 + R ox ) and R D, the series drain resistance, is eqaul to R D0 + R ox /(R D0 ) for forward/(reverse) mode operation where R S0 and R D0 are fresh series source and drain resistances respectivily. In eq. (2.12b), E sat is the critical electric field, and the equivalent resistance R ox of the damaged region and V on can be derived in ref. 5. Replacing L L ox and V DS in eqs. (2.12a) and (2.12b) with L EFF, the effctive channel length, and V DSX, effective drain-source voltage respectively, a smoothly continuous and single-piece drain current can be obtained. The fresh drain current can also be derived by setting L ox and N o to be zero. 3. Results and Discussion The parameter extraction is usually performed by elaboration of experimental measurements, but some parameters are not directly measurable and others are not related to the 6

7 physics of the device but are simply fitting parameters to model the device as close as possible to reality. In this paper, we adopt the numerical method in refs. 10 and 11 as our optimization method to examine how accurately the mathematical model with estimated parameters fits the experiment data set, and the flow chart of parameters extraction algorithm is depicted in Fig. 3. The unknown parameters and fitting parameters can then be found out by using this optimization method. Figure 4 shows the modeled and measured results 12) on the variation of I DS and I sub as a function of V GS with L/W = 0.6/24µm, t ox = 25 nm at drain bias = 4 V. The results show that I sub increases with gate bias up to a maximum and thereafter decreases on further increase in V GS. The increase in I sub is attributed to the increase in I DS, while its decrease is due to a reduced impact ionization coefficient because of the reduced channel electric field. The modeled results can describe the experimental data of drain and electron substrate currents very well with one set of parameters. Figure 5 shows comparisons between the experimental data 13) of buried-channel pmos- FETs and the modeled results with L = 1.2µm, t ox = 30 nm and N o = cm 2, substrate doping is cm 3. The device is stressed at V DS = 15 V and V GS = 2 V for 7.5 min. A good agreement has been obtained by using only one set of parameters under fresh, forward- and reverse-mode operations. By using the same parameters extracted from Fig. 5 except for L = 1.0µm and t ox = 20 nm, it is shown in Fig. 6 that with this consistent model good agreement is achieved between measured and simulated substrate and gate currents over a large range of bias conditions. The calculated drain, substrate, and gate currents are fitted to the measurements with one set of parameters which are shown in Table I. As the drain voltage V DS increases, the magnitude of electron gate current increases due to the increase of impact-ionization generated electrons. Results of a calculation for the profile of the distribution of the trapped charge and the gate current density are shown in Fig. 7. Figure 8 shows comparisons between the experimental data 14) of buried-channel pmos- FETs and the modeled results with L = 0.6µm, t ox = 18 nm, and N o = cm 2. A good agreement has been obtained by using only one set of parameters. The model also can correctly describe the highly asymmetric behavior of the post-stress drain cur- 7

8 rent under forward- and reverse-mode operations as shown in Fig. 8. The origin of this asymmetry can be attributed to the different spatial location of trapped oxide charges. This work is very useful for modeling the asymmetrical behavior of BC pmosfet drain current due to hot-carrier stress and can be easily extended to bi-directional stress simulations. Since the model is physics-based and analytic, it uses few fitting parameters, in Table II, and simplifies the parameter extraction procedure. Thus, it can be implemented in a circuit simulator. 4. Conclusion Based on the simplified two-dimensional Poisson equation and modified lucky electron concept, analytical and complete electron substrate current, electron gate current, and degraded drain current model for short-channel BC pmosfets are derived and are verified through experimental data. The degraded drain current model model is based on the hot-carrier-induced channel shortening concept and the damaged pmosfet is treated as an undamaged MOSFET in series with effective asymmetric source and drain resistances. The increase in post-stress drain current is caused by the oxide-trapping charges in the gate oxide, which result from electron gate current passing through the gate oxide. With this model we can calculate the electron substrate current, electron gate current, and the oxide-trapping-charges, therefore the post-stress drain current can be calculated in a consistent way physically. This model is mathematically simple and inherently continuous, and potentially useful for the application to VLSI BC circuit simulation. The model has been validated by comparing with the experimental data for devices with channel lengths down to 600 nm. However, since experimental results for devices with shorter channel lengths are not available, we are not able to comment on the accuracy of the model for shorter channel devices with last technology. Perhaps the degradation mechanism and experimental data shown in this paper do not completely appealed to the applications of current technology, but it really provides the capability of calculating pr-stress drain current, non-local substrate current, gate current, and post-stress drain current at the same time for buried-channel pmosfets. 8

9 This model has the merits of including several short channel device physics: draininduced-barrier-lowering, channel-length modulation, the parasitic source and drain resistances, and hot-carrier-induced oxide-trapping-charge. All these properties make the model potentially useful for the application to VLSI circuit simulation. Acknowledgements This work was supported by the National Science Council, Taiwan (R.O.C.) under Contract NSC S The author is particularly indebted to Professor Sheng- Lyang Jang for many valuable suggestions in developing the model. 9

10 References 1) C. C. Li, K. N. Quader, E. R. Minami, C. Hu, and P. K. Ko: IEDM Tech. Dig., 1992, p ) S. L. Jang, T. Z. Tang, Y. S. Chen, and C. J. Sheu: Solid-State Electron. 39 (1996) ) P. M. Lee, T. Garfinkel, and P. K. Ko: IEEE Trans. Electron Devices 41 (1994) ) I. C. Chen and S. J.Wang: IEEE Electron Device Lett. 14 (1993) ) C. G. Chyau and S. L. Jang: IEEE Trans. Electron Devices 45 (1998) ) K. Taniguchi, M. Yamaji, K. Sonoda, T. Kunikiyo, and C. Hamaguchi: IEDM Tech. Dig., 1994, p ) J. M. Higman, I. C. Kizilyalli, and K. Hess: IEEE Electron Device Lett. (1988) ) C. J. Sheu and S. L. Jang: Solid-State Electron. 47 (2003) ) M. Brox, A. Schwerin, Q. Wang, and W. Weber: IEEE Trans. Electron Devices 41 (1994) ) G. Forsythe, M. Malcolm, and C. Moler: Computer Methods for Mathematical Computations (Prentice-Hall, Englewood Cliffs, NJ, 1977). 11) C. Moler: Numerical Computing with MATLAB (The MathWorks, Inc., Natick, MA, 2004) Electronic edition, Chap. 4, p ) M. J. Deen and J. Wang: Cryogenics 30 (1990) ) T. C. Ong, P. K. Ko, and C. Hu: IEEE Trans. Electron Devices 37 (1990) ) A. Schwerin, W. Hansch, and W. Weber: IEEE Trans. Electron Devices 34 (1987)

11 Figure captions Fig. 1. (Color online) Cross-sectional view of a BC pmosfet. The series of probabilities in the model are illustrated. Fig. 2. (Color online) Energy band diagram of a poly-gate SiO 2 silicon system near drain side of a BC pmosfet. Fig. 3. The flow chart of parameters extraction algorithm. Fig. 4. (Color online) Modeled and measured 12) drain and substrate currents of a BC pmosfet as a function of drain and gate voltage with L/W = 0.6/24µm, t ox = 25 nm at drain bias = 4 V. Fig. 5. (Color online) I DS V DS characteristics of a BC pmosfet with L = 1.2µm, t ox = 30 nm. Fig. 6. (Color online) Modeled and measured 13) substrate and gate currents of a BC pmosfet with L = 1µm, t ox = 20 nm. Fig. 7. (Color online) Results of a calculation for the profile of the distribution of the trapped charge and the gate current density with capture cross section σ = cm 2 and characteristic decay length l ox = 8 nm. Fig. 8. (Color online) Measured 14) and modeled drain current of a BC pmosfet for before and after seconds electric stress at V GS = 2 V, V DS = 8 V. 11

12 Table I. The main parameters used in Figs. 5 and 6. V FB (V) X I (µm) 0.2 µ 0 (cm 2 V 1 s 1 ) v sat (cm s 1 ) R S0 (R D0 ) (Ω) θ o (V 1 ) ξ/ξ s A TS 4.8 n m /n m1 /n x 3.28/3.41/1.45 κ 0 /κ /0.88 ζ/ζ /0.021 γ (cm 2 ) β 0 (V cm 1 ) λ 0 (cm) λ r (cm) λ e (cm) λ ox (cm)

13 Table II. The main parameters used in Fig. 8. L (µm) 0.6 V FB (V) X I (µm) 0.15 µ 0 (cm 2 V 1 s 1 ) v sat (cm s 1 ) R S0 (R D0 ) (Ω) θ o (V 1 ) ξ/ξ s 3.67/0.64 A TS 5.33 n m /n m1 /n x 25.7/2.64/1.72 κ 0 /κ /0.67 ζ/ζ /

14 Fig. 1. (Color online) Cross-sectional view of a BC pmosfet. The series of probabilities in the model are illustrated. 14

15 Fig. 2. (Color online) Energy band diagram of a poly-gate SiO 2 silicon system near the drain side of a BC pmosfet. 15

16 Fig. 3. The flow chart of parameters extraction algorithm. 16

17 Fig. 4. (Color online) Modeled and measured 12) drain and substrate currents of a BC pmosfet as a function of drain and gate voltage with L/W = 0.6/24µm, t ox = 25 nm at drain bias = 4 V. 17

18 Fig. 5. (Color online) I DS V DS characteristics of a BC pmosfet with L = 1.2µm, t ox = 30 nm. 18

19 Fig. 6. (Color online) Modeled and measured 13) substrate and gate currents of a BC pmosfet with L = 1µm, t ox = 20 nm. 19

20 Fig. 7. (Color online) Results of a calculation for the profile of the distribution of the trapped charge and the gate current density with capture cross section σ = cm 2 and characteristic decay length l ox = 8 nm. 20

21 Fig. 8. (Color online) Measured 14) and modeled drain current of a BC pmosfet for before and after seconds electric stress at V GS = 2 V, V DS = 8 V. 21