EEE598D: Analog Filter & Signal Processing Circuits
|
|
- Felicity Harrington
- 5 years ago
- Views:
Transcription
1 EEE598D: Analog Filter & Signal Processing Circuits Instructor: Dr. Hongjiang Song Department of Electrical Engineering Arizona State University
2 Thursday January 24, 2002 Today: Active RC & MOS-C Circuits Basic LSI Passive & Active Components Tuning of Integrated CT Filters CR Structures Basic Active RC and MOS-C Circuit Blocks
3 Typical Filter Design Problems Filter Realization: Schematic SFG Block diagram etc. Analysis Design Filter Specification: Responses Dynamic range etc. Math: Diff. Equations Transformations TF etc.
4 Desired Features for LSI Filters Compatible with LSI process Immunity to parasitic effects, fabrication tolerances, and environment variations Large dynamic range Good power supply rejection Low power and small chip area
5 Typical Operation Region of LSI Filters SC/SI Filters CT Active Filters Passive LC Filters Distributed Filters f (Hz)
6 LSI Active RC and MOS-C Filters Direct mapping of discrete active RC filters to LSI active RC filters with CMOS compatible R, C, and Opamp realization. For MOS-C filters, resistors are mapped to MOS CRs. Tuning is usually required due to parameter variation of the LSI components.
7 2-stage Opamp CMOS Opamp Structures - - out
8 CMOS Opamp Structures OTA - - out
9 2-stage Cascode Opamp CMOS Opamp Structures - - out
10 Folded Cascode Opamp CMOS Opamp Structures - - out
11 Telescopic Opamp CMOS Opamp Structures - - out
12 Rail-to-rail Opamp CMOS Opamp Structures - - out
13 Fully Differential Opamp CMOS Opamp Structures - o - - o- cm
14 CMOS Opamp Structures Differntial Difference Amplifer (DDA)
15 Typical Opamp Responses
16 LSI Capacitor Structures Gate capacitors high density, but Nonlinear Junction capacitors Highly nonlinear Poly(metal)-to-poly (metal) capacitors Good linearity and high Q Fractal capacitor High density and good linearity More complicated structure
17 Double-Poly Capacitor LSI Capacitor Structures n p-substrate
18 MOS Capacitor LSI Capacitor Structures n n Heavy n implant (bottom plate) p-substrate
19 LSI Capacitor Structures Metal-Polycide Capacitor
20 LSI Capacitor Structures Metal-Polycide Capacitor
21 LSI Capacitor Structures Metal-Insulator-Metal (MIM) Capacitor
22 MIM Capacitor Structure
23 Fractal capacitor LSI Capacitor Structures Enhancement (~ 2.3x) of capacitance/area with lateral coupling
24 LSI Resistor Structures Diffusion Resistors Poly Resistors Well Resistors Pinch Resistors
25 LSI Resistor Structures Diffusion Resistor P-diffusion n-well P-substrate
26 LSI Resistor Structures Poly Resistor n P-substrate
27 LSI Resistor Structures Well Resistor n n n-well P-substrate
28 LSI Resistor Structures Pinch Resistor p n n n-well P-substrate P connected to p -
29 Example of Passive Element Accuracy
30 Tuning of LSI CT Filters Tuning required for CT integrated filters to account for capacitance and resistance/transconductance variations 30% time-constant variations Must account for process, temperature, aging, etc. While absolute tolerances high, ratio of two like components can be matched to under 1% Tuning can often be the MOST difficult part of a CT integrated filter design Note that SC/SI filters do not need tuning as their transfer-function accuracy set by ratio of capacitors (or transistors) and a clock-frequency
31 Tuning of LSI CT Filters Example:
32 Dr Dr. Hongjiang Hongjiang Song, Arizona State University Song, Arizona State University LSI CR Structures Basic MOS voltage controlled resistor (CR) ) 2 ( 1 ) )( 2 ( s d T G s d s d T G R I = = β β Nonlinear term Control voltage
33 LSI CR Structures Linear MOS CR - 1st approach c 1/2 1/2 d s I Let Then G = R = d β s 2 1 ( ) C Control voltage T C
34 Dr Dr. Hongjiang Hongjiang Song, Arizona State University Song, Arizona State University LSI CR Structures Linear MOS CR - 2nd approach c c d s ) ( 2 1 ) )( ( 2 ) )( 2 ( ) )( 2 ( T G s d T c s s d s d T s c s d s d T d c R I = = = β β β β I
35 LSI CR Structures Linear MOS CR - 3rd approach I c s - I- s s - s c c [ I R = I β ( ] = β ( C 1 T C ) T )[( s ) ( s )]
36 LSI CR Structures Linear MOS CR - 4th approach c1 d d I s d- s s c2 c d- I- c1 s [ I R = I β ( ] = β ( C 2 1 C 2 C 2 ) C 2 )[( d s ) ( d s )]
37 Dr Dr. Hongjiang Hongjiang Song, Arizona State University Song, Arizona State University LSI CR Structures Grounded Linear MOS CR d I c 2 2 ) ( 2 ) 2 ( ) 2 ( ) ( 2 T d T c d d T c T d I β β β β = = ) 2 ( 1 ) ( 1 T c d d di R = = β
38 LSI Resistor Structures MOS CR Implementation
39 LSI Resistor Structures MOS CR Implementation
40 LSI Resistor Structures MOS CR Implementation
41 LSI Resistor Structures MOS CR Implementation
42 Basic Active RC Circuits Fully differential gain stage R2 i -i R1 R1 - - o -o o i = R R 2 1 R2
43 Basic MOS-C Circuits Fully differential gain stage c2 i -i β1 c1 - β2 - β2 c2 o -o o i β = β 1 2 ( ( c1 c2 T T ) )
44 Basic Active RC Circuits i2 Fully differential adder stage R1 R2 i1 -i1 -i2 R1 R1 - - o -o R2 ( ) o = i 1 i 2 R 1 R1 R2
45 Basic MOS-C Circuits Fully differential adder c2 i2 β2 i1 o - -i1 β1 - -o β2 -i2 c1 c2 β1( c 1 T ) o = ( i 1 β ( ) 2 c2 T i2 )
46 Basic Active RC Circuits Fully differential integrator C i -i R R - - o -o i ( s) = o 1 RCs C
47 Basic MOS-C Circuits Fully differential integrator i -i c β c - - C C o -o o i ( s) = 1 Cs β ( c T )
48 Basic Active RC Circuits i -i Fully differential lossy integrator R1 C R o - - R -o C o i 1 ( s) = RCs R R 1 R1
49 Basic MOS-C Circuits i -i Fully differential lossy integrator c1 β1 C c o - β - -o C c o i ( s) = Cs β ( c T ) 1 β1( β ( c1 c T T ) ) β1 c1
EE382M-14 CMOS Analog Integrated Circuit Design
EE382M-14 CMOS Analog Integrated Circuit Design Lecture 3, MOS Capacitances, Passive Components, and Layout of Analog Integrated Circuits MOS Capacitances Type of MOS transistor capacitors Depletion capacitance
More informationCircuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive
More informationCMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process
EECS240 Spring 202 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS Technology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 Today s Lecture
More informationChapter 2 Switched-Capacitor Circuits
Chapter 2 Switched-Capacitor Circuits Abstract his chapter introduces SC circuits. A brief description is given for the main building blocks of a SC filter (operational amplifiers, switches, capacitors,
More informationSwitched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationEECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology
EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor
More informationCMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices
EECS240 Spring 2008 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS echnology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 oday s Lecture
More informationLecture 040 Integrated Circuit Technology - II (5/11/03) Page ECE Frequency Synthesizers P.E. Allen
Lecture 040 Integrated Circuit Technology - II (5/11/03) Page 040-1 LECTURE 040 INTEGRATED CIRCUIT TECHNOLOGY - II (Reference [7,8]) Objective The objective of this presentation is: 1.) Illustrate and
More informationEE 434 Lecture 12. Process Flow (wrap up) Device Modeling in Semiconductor Processes
EE 434 Lecture 12 Process Flow (wrap up) Device Modeling in Semiconductor Processes Quiz 6 How have process engineers configured a process to assure that the thickness of the gate oxide for the p-channel
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft
ELEN0037 Microelectronic IC Design Prof. Dr. Michael Kraft Lecture 2: Technological Aspects Technology Passive components Active components CMOS Process Basic Layout Scaling CMOS Technology Integrated
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationLecture 210 Physical Aspects of ICs (12/15/01) Page 210-1
Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationECEN 474/704 Lab 2: Layout Design
ECEN 474/704 Lab 2: Layout esign Objectives Learn Techniques for successful integrated circuit layout design. Introduction In this lab you will learn in detail how to generate a simple transistor layout.
More informationLAYOUT TECHNIQUES. Dr. Ivan Grech
LAYOUT TECHNIQUES OUTLINE Transistor Layout Resistor Layout Capacitor Layout Floor planning Mixed A/D Layout Automatic Analog Layout Layout Techniques Main Layers in a typical Double-Poly, Double-Metal
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationCharacteristics of Passive IC Devices
008/Oct 8 esistors Characteristics of Passive IC Devices Poly esistance Diffusion esistance Well esistance Parasitic esistance Capacitors Poly Capacitors MOS Capacitors MIM Capacitors Parasitic Capacitors
More informationECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION
ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationThe Wire. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Wire July 30, 2002 1 The Wire transmitters receivers schematics physical 2 Interconnect Impact on
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationEE 434 Lecture 13. Basic Semiconductor Processes Devices in Semiconductor Processes
EE 434 Lecture 3 Basic Semiconductor Processes Devices in Semiconductor Processes Quiz 9 The top view of a device fabricated in a bulk CMOS process is shown in the figure below a) Identify the device b)
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationDiscrete Time Signals and Switched Capacitor Circuits (rest of chapter , 10.2)
Discrete Time Signals and Switched Capacitor Circuits (rest of chapter 9 + 0., 0.2) Tuesday 6th of February, 200, 9:5 :45 Snorre Aunet, sa@ifi.uio.no Nanoelectronics Group, Dept. of Informatics Office
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationElectronic Circuits Summary
Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent
More informationCapacitor Action. 3. Capacitor Action Theory Support. Electronics - AC Circuits
Capacitor Action Topics covered in this presentation: Capacitors on DC Capacitors on AC Capacitor Charging Capacitor Discharging 1 of 18 Charging a Capacitor (DC) Before looking at how capacitors charge
More informationDiscrete Time Signals and Switched Capacitor Circuits (rest of chapter , 10.2)
Discrete Time Signals and Switched Capacitor Circuits (rest of chapter 9 + 10.1, 10.2) Tuesday 16th of February, 2010, 0, 9:15 11:45 Snorre Aunet, sa@ifi.uio.no Nanoelectronics Group, Dept. of Informatics
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD
More informationECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationVLSI Design and Simulation
VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage
More informationChapter 2. Design and Fabrication of VLSI Devices
Chapter 2 Design and Fabrication of VLSI Devices Jason Cong 1 Design and Fabrication of VLSI Devices Objectives: To study the materials used in fabrication of VLSI devices. To study the structure of devices
More informationLecture 020 Review of CMOS Technology (09/01/03) Page 020-1
Lecture 020 Review of CMOS Technology (09/01/03) Page 020-1 LECTURE 020 REVIEW OF CMOS TECHNOLOGY INTRODUCTION Objective Provide sufficient background to understand the limits and capabilities of CMOS
More informationElectronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi
Electronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi Module No. #05 Lecture No. #02 FETS and MOSFETS (contd.) In the previous lecture, we studied the working
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationAE74 VLSI DESIGN JUN 2015
Q.2 a. Write down the different levels of integration of IC industry. (4) b. With neat sketch explain briefly PMOS & NMOS enhancement mode transistor. N-MOS enhancement mode transistor:- This transistor
More informationECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION
ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
More informationThe Wire EE141. Microelettronica
The Wire 1 Interconnect Impact on Chip 2 Example: a Bus Network transmitters receivers schematics physical 3 Wire Models All-inclusive model Capacitance-only 4 Impact of Interconnect Parasitics Interconnect
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 3: Sample and Hold Circuits Switched Capacitor Circuits Circuits and Systems Sampling Signal Processing Sample and Hold Analogue Circuits Switched Capacitor
More informationDigital Integrated Circuits (83-313) Lecture 5: Interconnect. Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1
Digital Integrated Circuits (83-313) Lecture 5: Interconnect Semester B, 2015-16 Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1 What will we learn today? 1 A First Glance at Interconnect 2 3
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 7 Interconnections 1: wire resistance, capacitance,
More informationAdvanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------
More informationLow Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 08 MOS Inverters - III Hello, and welcome to today
More informationVLSI VLSI CIRCUIT DESIGN PROCESSES P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI VLSI CIRCUIT DESIGN PROCESSES P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) SYLLABUS UNIT II VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 m CMOS Design
More informationHw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today
EECS141 1 Hw 8 Posted Last one to be graded Due Friday April 30 Hw 6 and 7 Graded and available Project Phase 2 Graded Project Phase 3 Launch Today EECS141 2 1 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 Frequency
More informationSupplementary Information: Noise-assisted energy transport in electrical oscillator networks with off-diagonal dynamical disorder
Supplementary Information: Noise-assisted energy transport in electrical oscillator networks with off-diagonal dynamical disorder oberto de J. León-Montiel, Mario A. Quiroz-Juárez, afael Quintero-Torres,
More informationCMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors
CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier
More informationElectronics Capacitors
Electronics Capacitors Wilfrid Laurier University October 9, 2015 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists
More informationDigital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.
Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationFrequency Response Prof. Ali M. Niknejad Prof. Rikky Muller
EECS 105 Spring 2017, Module 4 Frequency Response Prof. Ali M. Niknejad Department of EECS Announcements l HW9 due on Friday 2 Review: CD with Current Mirror 3 Review: CD with Current Mirror 4 Review:
More informationLecture 23: Negative Resistance Osc, Differential Osc, and VCOs
EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,
More informationThin Film Transistors (TFT)
Thin Film Transistors (TFT) a-si TFT - α-si:h (Hydrogenated amorphous Si) deposited with a PECVD system (low temp. process) replaces the single crystal Si substrate. - Inverted staggered structure with
More informationThe K-Input Floating-Gate MOS (FGMOS) Transistor
The K-Input Floating-Gate MOS (FGMOS) Transistor C 1 V D C 2 V D I V D I V S Q C 1 C 2 V S V K Q V K C K Layout V B V K C K Circuit Symbols V S Control Gate Floating Gate Interpoly Oxide Field Oxide Gate
More informationS No. Questions Bloom s Taxonomy Level UNIT-I
GROUP-A (SHORT ANSWER QUESTIONS) S No. Questions Bloom s UNIT-I 1 Define oxidation & Classify different types of oxidation Remember 1 2 Explain about Ion implantation Understand 1 3 Describe lithography
More informationVLSI Design I; A. Milenkovic 1
Course Administration CPE/EE 47, CPE 57 SI Design I 0: IC Manufacturing & MOS Transistor Theory Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic
More informationSwitched Capacitor Filter
Switched Capacitor Filter Design for Mixed Signal Applications by Klaus Jørgensen Napier No. 47824 Supervisor Dr. Mohammad Y Sharif Contents Aims of the Project Switch Capacitor Filter Basic Theory Low-pass
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationTaking the Laplace transform of the both sides and assuming that all initial conditions are zero,
The transfer function Let s begin with a general nth-order, linear, time-invariant differential equation, d n a n dt nc(t)... a d dt c(t) a 0c(t) d m = b m dt mr(t)... a d dt r(t) b 0r(t) () where c(t)
More informationEE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationPhysics 405/505 Digital Electronics Techniques. University of Arizona Spring 2006 Prof. Erich W. Varnes
Physics 405/505 Digital Electronics Techniques University of Arizona Spring 2006 Prof. Erich W. Varnes Administrative Matters Contacting me I will hold office hours on Tuesday from 1-3 pm Room 420K in
More informationMOS Capacitors ECE 2204
MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field
More informationLab 4 RC Circuits. Name. Partner s Name. I. Introduction/Theory
Lab 4 RC Circuits Name Partner s Name I. Introduction/Theory Consider a circuit such as that in Figure 1, in which a potential difference is applied to the series combination of a resistor and a capacitor.
More informationEE141. EE141-Spring 2006 Digital Integrated Circuits. Administrative Stuff. Class Material. Flash Memory. Read-Only Memory Cells MOS OR ROM
EE141-pring 2006 igital Integrated Circuits Lecture 29 Flash memory Administrative tuff reat job on projects and posters! Homework #10 due today Lab reports due this week Friday lab in 353 Final exam May
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More informationHigh-Order Inductorless Elliptic Filter with Reduced Number of Capacitors Using Signal- Flow Graphs
High-Order nductorless Elliptic Filter with educed Number of apacitors Using ignal- Flow Graphs Đani Glavinić * and Dražen Jurišić * * University of Zagreb/Faculty of Electrical Engineering and omputing
More informationLecture 8. Detectors for Ionizing Particles
Lecture 8 Detectors for Ionizing Particles Content Introduction Overview of detector systems Sources of radiation Radioactive decay Cosmic Radiation Accelerators Interaction of Radiation with Matter General
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationVLSI. Faculty. Srikanth
J.B. Institute of Engineering & Technology Department of CSE COURSE FILE VLSI Faculty Srikanth J.B. Institute of Engineering & Technology Department of CSE SYLLABUS Subject Name: VLSI Subject Code: VLSI
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationPARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.2-1 10.2 - PARALLEL DIGITAL-ANALOG CONVERTERS CLASSIFICATION OF DIGITAL-ANALOG CONVERTERS CMOS Analog IC Design Page 10.2-2 CURRENT SCALING DIGITAL-ANALOG CONVERTERS GENERAL
More informationJ. Lazzaro, S. Ryckebusch, M.A. Mahowald, and C. A. Mead California Institute of Technology Pasadena, CA 91125
WINNER-TAKE-ALL NETWORKS OF O(N) COMPLEXITY J. Lazzaro, S. Ryckebusch, M.A. Mahowald, and C. A. Mead California Institute of Technology Pasadena, CA 91125 ABSTRACT We have designed, fabricated, and tested
More informationGeorgia Institute of Technology School of Electrical and Computer Engineering. Midterm-1 Exam (Solution)
Georgia Institute of Technology School of Electrical and Computer Engineering Midterm-1 Exam (Solution) ECE-6414 Spring 2012 Friday, Feb. 17, 2012 Duration: 50min First name Solutions Last name Solutions
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND
More informationUnit 2: Modeling in the Frequency Domain. Unit 2, Part 4: Modeling Electrical Systems. First Example: Via DE. Resistors, Inductors, and Capacitors
Unit 2: Modeling in the Frequency Domain Part 4: Modeling Electrical Systems Engineering 582: Control Systems I Faculty of Engineering & Applied Science Memorial University of Newfoundland January 20,
More informationSemiconductor Memories
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 Chapter Overview Memory Classification Memory Architectures
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationIntroduction to CMOS RF Integrated Circuits Design
V. Voltage Controlled Oscillators Fall 2012, Prof. JianJun Zhou V-1 Outline Phase Noise and Spurs Ring VCO LC VCO Frequency Tuning (Varactor, SCA) Phase Noise Estimation Quadrature Phase Generator Fall
More informationLecture 0: Introduction
Lecture 0: Introduction Introduction q Integrated circuits: many transistors on one chip q Very Large Scale Integration (VLSI): bucketloads! q Complementary Metal Oxide Semiconductor Fast, cheap, low power
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationLecture 4, Noise. Noise and distortion
Lecture 4, Noise Noise and distortion What did we do last time? Operational amplifiers Circuit-level aspects Simulation aspects Some terminology Some practical concerns Limited current Limited bandwidth
More informationP. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationAs light level increases, resistance decreases. As temperature increases, resistance decreases. Voltage across capacitor increases with time LDR
LDR As light level increases, resistance decreases thermistor As temperature increases, resistance decreases capacitor Voltage across capacitor increases with time Potential divider basics: R 1 1. Both
More informationPURPOSE: See suggested breadboard configuration on following page!
ECE4902 Lab 1 C2011 PURPOSE: Determining Capacitance with Risetime Measurement Reverse Biased Diode Junction Capacitance MOSFET Gate Capacitance Simulation: SPICE Parameter Extraction, Transient Analysis
More informationFloating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access
More informationSwitched Capacitor Circuits I. Prof. Paul Hasler Georgia Institute of Technology
Switched Capacitor Circuits I Prof. Paul Hasler Georgia Institute of Technology Switched Capacitor Circuits Making a resistor using a capacitor and switches; therefore resistance is set by a digital clock
More informationEE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances
EE 435 Lecture 37 Parasitic Capacitances in MOS Devices String DAC Parasitic Capacitances Parasitic Capacitors in MOSFET (will initially consider two) Parasitic Capacitors in MOSFET C GCH Parasitic Capacitors
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationCapacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009
Wilfrid Laurier University June 4, 2009 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists of two conductive
More informationSemiconductor Memories
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 Chapter Overview Memory Classification Memory Architectures
More information