Chapter 5. BJT AC Analysis

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1 Chapter 5. Outline: The r e transistor model CB, CE & CC AC analysis through r e model common-emitter fixed-bias voltage-divider bias emitter-bias & emitter-follower common-base configuration

2 Transistor Modeling A model is a combination of circuit elements, properly chosen, that best approximates the actual behavior of a semiconductor device under specific operating condition. There are three models: r e model hybrid model hybrid equivalent model.

3 Before discussing model, we must make preparation to the discussion. The superposition theorem is applicable and the the investigation of the dc conditions can be totally separated from the ac response. An suitable Q-point has been chosen. Then the dc levels can be ignored in the ac analysis network.

4 The coupling capacitor C 1, C 2 and bypass capacitor C 3 are chosen to have a very small reactance. Therefore, each is replaced by a short circuit. This also results in the shorting out of dc biasing resistor R E. Those important parameters, such as Z i, Z o, V i, V o, I i and I o should be kept unchanged.

5 The input voltage V i is defined between base and ground. The input current I i is defined as the base current of the transistor. The input impedance Z i is defined from base to ground. The output voltage V o is defined between collector and ground.

6 The output current I o is defined as the current through the load resistor R C. The output impedance Z o is defined from collector to ground. By introducing a common ground, R 1 and R 2 will be in parallel. R C will appear from collector to emitter.

7 The transistor equivalent circuit also consists of resistors and independent controlled source. The circuit analysis techniques such as superposition, Thevenin theorem can be applied to determine the desired quantities. There are important quantities indicating amplification effects:

8 Voltage gain: V o / V i Current gain: I o / I i Briefly, steps to obtain ac equivalent circuit: dc sources to zero capacitors to short circuits Removing elements bypassed by short circuits and rearranging network

9 Figure: Transistor circuit for ac analysis

10 The r e Model for CB As shown in the figure, it is the commonbase BJT circuit. Now, r e model is introduced. On the input port, there is a resistor, r e. where r e = 26mV / I E (Eq. 5.1) The subscript e of r e indicates that it is the dc level of I E that determines the ac level of the resistance.

11 On the output port, there is a controlled current source, denoted by a diamond shape. The I c is controlled by the level of I e. The input impedance Z i is r e. The output impedance Z o. In general, for common-base configuration, the Z i is relatively small and Z o quite high.

12 Voltage gain: V o = - I o R L = - (- I c ) R L = I e R L V i = I i Z i = I e Z i =I e r e so that A v = V o / V i = ( I e R L )/(I e r e ) = ( R L )/ r e R L / r e Current gain: A i = I o / I i = (-I c )/(I e ) = (- I e )/(I e ) -1 For common-base configuration, the V o and V i are in phase.

13 Figure: r e model for common-base circuit

14 The r e Model for CE As shown in the figure, it is the commonemitter BJT circuit. Now, replace the transistor with r e model On the input side, there exists r e. Z i = V i / I i = V be /I b = (I e r e )/ I b = [( +1)I b r e ]/ I b =( +1)r e r e ( if is large enough) Typically, Z i is at moderate level.

15 On the output side, the controlledcurrent source is connected between collector and emitter, I source = I b. Ideally, the output impedance Z o. Or, Z o = r o, as shown in the figure. At this time, I c I b. Normally, voltage gain A v and current gain A i are high. For common-collector configuration, this model is also applicable.

16 Figure: r e model for common-emitter circuit

17 CE Fixed Bias Circuit As shown in the figure, it is the commonemitter fixed-bias configuration. The input signal V i is applied to the base and the output V o is off the collector. The input current I i is not the base current and the I o is the collector current. For small-signal analysis, V CC is replaced with ground.

18 Those dc blocking capacitors C 1 and C 2 are replaced with short circuits. So the R B is in parallel with the input port and R C output port. The parameters of Z i, Z o, I i and I o should be in the same places as original network. Finally, substitute the r e model for the transistor.

19 In practice, The is read from the datasheet or measured with testing instrument. The r e is determined from dc analysis. The r o is obtained from the datasheet. In the small-signal analysis, we assume that, r o and r e have been determined in advance.

20 Input impedance Z i : From the figure, it is obvious that Z i = R B r e For the majority of situation, R B is greater than r e by more than a factor of 10. So we get Z i r e

21 Output impedance Z o : From the definition of Z o, we get Z o = R C r o If r o 10R C, then Z o R C Voltage gain A v : From the figure, we get V o =( - I b )(R C r o )

22 And I b =V i /( r e ) So V o =( - I b )(R C r o ) =( - V i /( r e ))(R C r o ) =( -V i / r e )(R C r o ) Finally, A v =V o / V i = - (R C r o ) / r e

23 Phase relationship: The negative sign in A v,reveals that a 180 phase shift occurs between the input and output signals. This also means that a single-stage of amplifier of this type is not enough. The magnitude of output signal is larger than that of input signal. But the frequencies of them should be the same.

24 Figure: r e model for CE fixed-bias circuit

25 Figure: phase shift of input & output

26 Example 5.4 As shown in the figure, it is the commonemitter fixed-bias configuration. Determine: r e, Z i, Z o, A v with r o = 50k. Solution: From dc analysis, we get I B V CC V R B BE 12V 0.7V 470k A

27 I E = (β+1) I B = (100+1) A = 2.428mA r e = (26mV)/I E = (26mV)/ 2.428mA = Then, ac analysis r e = (100)(10.71 ) = k Z i = R B r e = (470 k ) (1.071 k ) = k

28 Z o = R C r o = (3 k ) (50 k ) = 2.83k A v =-(R C r o ) / r e =-2.83k / =-264 From the A v,we can see that the output signal has been amplified but out of phase with the input signal.

29 Figure: Example 5.4

30 Voltage Divider Bias As shown in the figure, it is the voltage divider bias configuration. Substituting r e equivalent circuit, note that: R E is absent due to the low impedance of the bypass capacitor C E. When V CC is set to zero, one end of R 1 and R C are connected to ground. R 1 and R 2 remain part of the input circuit while R C is part of output circuit.

31 Some parameter of the equivalent circuit: Input impedance Z i : Z i =R 1 R 2 r e Output impedance Z o : Z o = R C r o If r o 10R C, then Z o R C Voltage gain A v :

32 V o =( - I b )(R C r o ) =( -V i / r e )(R C r o ) =[- V i /( r e )] (R C r o ) So, A v =V o / V i = - (R C r o ) / r e If r o 10R C, then A v =V o / V i Phase relationship: -R C / r e 180 phase shift occurs between the input and output signals.

33 Figure: Voltage divider bias & its equivalent circuit

34 Example 5.5 As shown in the figure, it is the voltage divider bias configuration. Determine: r e, Z i, Z o, A v with r o = 50k. Solution: dc analysis, testing R E >10 R 2, k > k 135k > 82k (satisfied)

35 Using the approximate approach (Sec. 4.5, p155), we obtain: R 8.2k V 22V 56k 8.2k 2 B V CC R1 R2 V E = V B - V BE = 2.81V-0.7V = 2.11V I E = V E / R E = 2.11V/1.5k = 1.41mA 2.81V r e = 26mV / I E = 26mV / 1.41mA = 18.44

36 ac analysis, Z i =R 1 R 2 r e = 56k 8.2k (90)(18.44 ) = 1.347k Z o = R C r o = 6.8k 50k = 5.99k A v =-(R C r o ) / r e = k /18.44 =-324

37 Figure: Example 5.5

38 CE Emitter Bias As shown in the figure, it is the emitter bias configuration, without C E. Substituting r e equivalent circuit, note that: The resistance r o is ignored for simplicity. First, let us obtain Z b. V i =I b r e + I e R E =I b r e +( +1) I b R E So, Z b = V i / I b = r e +( +1) R E

39 At input port, Z i = R B Z b At output port, Z o = R C V o = -I o R C = - I b R C = - (V i /Z b ) R C So, A v = V o / V i = - R C /Z b Phase relationship: 180 phase shift occurs between the output and input signals.

40 Figure: Emitter bias & its equivalent circuit

41 Example 5.6 As shown in the figure, it is the emitter bias configuration. Determine: r e, Z i, Z o, A v. Solution: dc analysis, VCC VBE I B RB ( 1) RE 20V 0.7V 470k (120 1) 0.56k A

42 I E = (β+1) I B = (120+1) A =4.34mA r e = (26mV)/I E = (26mV)/ 4.34mA = 5.99 Then, ac analysis Z b = r e +( +1) R E = = k

43 Z i = R B Z b = (470 k ) (68.48k ) = k Z o = R C = 2.2 k A v = - R C /Z b = k / 68.48k = For emitter bias with C E, see Ex For emitter bias + voltage divider, see Ex. 5.8 & 5.9.

44 Figure: Example 5.6

45 Emitter-Follower As shown in the figure, it is the emitterfollower configuration. Actually, it is a common-collector network. The output is always slightly less than the input, but this is good for practical use. Also the V o is in phase with V i and this accounts for the name of emitter-follower.

46 The emitter-follower configuration has a high input impedance and a low output impedance. This is the reason why it is used for impedance matching purpose. This can give a weak load to the previous stage and a strong output ability to the next stage.

47 Substituting r e equivalent circuit, note that: The resistance r o is ignored because for most applications a good approximation for the actual results can still be obtained. First, the same as before, Z b is obtained: Then, Z b = r e +( +1) R E Z i = R B Z b

48 At output port, I e = ( +1) I b = ( +1) (V i /Z b ) So, I e r e ( 1) Vi ( 1) R If is sufficiently large, we get Vi Ie r R This means that is I e generated by V i. e E E

49 Also, V o is the potential drop across R E. So we construct a network from the viewpoint of output port. So, by setting the V i to zero, we get Z o = R E r e Furthermore, from this network it is obvious that RE Vo Vi R r E e

50 This leads to A v V V o i Since, R E is usually much greater than r e, A v 1 Phase relationship: V o and V i are in phase. R RE E r e

51 Figure: Emitter-follower & its equivalent circuit

52 Example 5.10 As shown in the figure, it is the emitterfollower configuration. Determine: r e, Z i, Z o, A v. Solution: dc analysis, VCC VBE I B RB ( 1) RE 20V 0.7V 220k (100 1) 3.3k A

53 I E = (β+1) I B = (100+1) A =2.063mA r e = (26mV)/I E = (26mV)/ 2.063mA = 12.6 Then, ac analysis Z b = r e +( +1) R E = k = k

54 Z i = R B Z b = (220 k ) (334.56k ) = k Z o = R E r e = 3.3k 12.6 = A v V V o i R RE E r e 3.3k 3.3k For some variations of emitter follower configuration, see Fig & 5.55

55 Figure: Example 5.10

56 Common-base Configuration As shown in the figure, it is the commonbase configuration. It has a relatively low Z i and high Z o and a current gain less than 1. However, the A v can be quite large. Substituting r e equivalent circuit into the network, note that:

57 The resistance r o is typically in the M and can be ignored in parallel with R C. First, Z i = R E r e Then, Z o = R C And V o = - I o R C = I c R C = I e R C With V i = I e r e, So that A v = V o / V i = R C /r e

58 At last, assuming R E >> r e, we get And I i = I e I o = - I e = - I i So that A i = I o / I i Phase relationship: = - -1 V o and V i are in phase in commonbase configuration.

59 Figure: Common-base & its equivalent circuit

60 Example 5.11 As shown in the figure, it is the commonbase configuration. Determine: r e, Z i, Z o, A v and A i. Solution: dc analysis, VEE V I E R E BE 2V 0.7V 1k 1.3mA r e = (26mV)/I E = (26mV)/ 1.3mA = 20

61 Then, ac analysis Z i = R E r e Z o = R C = 1 k 20 = = 5 k A v = R C /r e = k / 20 = 245 A i = - =

62 Figure: Example 5.11

63 Content not discussed but still important The hybrid equivalent mode (Sec. 5.5) The hybrid model (Sec. 5.6) Collector Feedback (Sec. 5.13) Cascaded Systems (Sec. 5.19) Darlington Connection (Sec. 5.20) Current Source (Sec. 5.22, 5.23)

64 Summary of Chapter 5 The r e model is applied to the analysis of transistor configurations: Common-emitter: Fixed bias; Voltage divider; Emitter bias Common-collector: emitter-follower Common-base. The calculation of those parameters, like V i, V o, I i, I o, Z i, Z o, A v and A i,in the circuits.

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