CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012

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1 1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012

2 Chapter 3: MOSFET 2 Introduction Classifications JFET D-FET (Depletion MOS) MOSFET (Enhancement E-FET) DC biasing Small signal analysis Equivalent small signal circuit

3 FET Introduction 3 High input impedance, nmω-n100mω Controlled by voltage ( BJT) Low power consumption Low noise, suitable for small signal Low impact of temperature Using as switch for low power application Small size and adapt for integrated circuit

4 Classification 4 JFET-Junction Field Effect Transistor N and P channels MOSFET-Metal Oxide Semiconductor FET Depletion MOS N and P channels Enhancement MOS N and P channels

5 Classification (cont d) 5 JFET D-FET E-FET (MOSFET)

6 JFET 6 Structure and Operation Characteristic Curve Compare with BJT Examples, datasheets

7 7 JFET Structure

8 JFET Operation 8 V GS = 0, V DS >0 increase gradually, I D increases and then saturates

9 JFET Operation 9 V GS = 0, V DS = V P, I D = I DSS V P : pinch off voltage (pinch-off) I D = I DSS (1 - V GS /V P ) 2

10 JFET Operation 10 V GS < 0, V DS > 0, Saturation current reduces when V GS V pinch-off V GS = V P, I D = 0

11 JFET Characteristic Curves 11 I D = f(v GS ) Shockley equation: I G 0A (gate current) I D = I DSS (1 - V GS /V P ) 2 I D = I S (I D drain current, I S source current)

12 JFET Characteristic Curves 12 N-channel, I DSS = 8mA, V P = - 4V P-channel, I DSS = 6mA, V P = 6V

13 13 JFET Symbol

14 JFET 14 2N5457

15 Datasheet-2N Rating Symbol Value Unit Drain-Source voltage V DS 25 Vdc Drain-Gate voltage V DG 25 Vdc Reverse G-S voltage V GSR -25 Vdc Gate current I G 10 nadc Device dissipation 25 0 C Derate above 25 0 C P D mw mw/ 0 C Junction temp range T J C Storage channel temp range T stg -60 to C

16 Datasheet-2N5457-characteristics 16 Characteristic Symbol Min Typ Max Unit V G-S breakdown V (BR)GSS -25 Vdc I gate reverse(vgs=-15, Vds=0) I GSS -1.0 nadc V G-S cutoff V GS(off) Vdc V G-S V GS Vdc I D-zero gate volage I DSS madc C in C iss pf C reverse transfer C rss pf

17 MOSFET 17 Structures Operation Characteristic Curves

18 MOSFET Structure 18 N-channel Depletion DMOS N-channel Enhancement EMOS

19 MOSFET Operation 19 N-channel DMOS V GS = 0, V DS > 0 N-channel EMOS V GS > V TH, V DS > 0

20 DMOS Transfer characteristic curves 20 Similar to JFET, transfer characteristic curve I D = f(v GS ) follows Shockley equation: I D = I DSS (1 - V GS /V P ) 2 Can work at: V GS > 0, I D > 0

21 EMOS Transfer characteristic curve 21 Transfer characteristic curve: I D = k(v GS V T ) 2 with V T > 0 (for NMOS) and Vt< 0 for PMOS) When V GS < V T, I D = 0

22 MOSFET Transfer characteristic curve 22 P-channel depletion

23 MOSFET Transfer characteristic curve 23 P-channel enhancement

24 MOSFET Symbol 24 DMOS EMOS

25 25 EMOS 2N4351

26 Datasheet-2N4351-EMOS 26 Characteristic Symbol Min Max Unit V DS breakdown V (BR)DSX 25 Vdc I D-zero gate volage, Vds=10V,Vgs=0, 25C 150C I DSS 10 nadc 10 µadc I gate reverse(vgs=+-15, Vds=0) I GSS +-10 nadc V DS on Voltage V DS(on) 1.0 V C in(vds=10v,id=2ma,f=140khz) C iss 5.0 pf C DS(Vdsub=10V,f=140KHz) C rss 5.0 pf R DS(Vgs=10V,Id=0,f=1KHz) R ds(on) 300 ohms

27 VMOS 27 VMOS Vertical MOSFET, increase channel lenght Increase drain current thanks to large space of heat release High switching speed

28 CMOS 28 CMOS=Complementary MOSFET pmos và nmos: fabricated on same wafer Reduce size and power consumption, increase switching speed Analog/Digital IC design

29 29 Resume JFET DFET MOSFET

30 Biasing types 30 Fixed bias Self-biasing Voltage divider biasing Feedback biasing

31 Some noted 31 With all kinds of FET: I G = 0A I D = I S For JFET & D-MOSFET: I D = I DSS (1 V GS /V P ) 2 For E-MOSFET (MOSFET): I D = k(v GS V T ) 2 (saturation mode) Determine Q-point (DC operating point) and DC load line

32 Fix biasing (ex: JFET) 32 I G = 0A V S = 0 V GS = V G = - V GG I D = I DSS (1-V GS /V p ) 2 V G is fixed at V GG

33 Fix biasing 33 I D = I DSS (1-V GS /V P ) 2 Build transfer characteristic curve from this table: V GS I D 0 I DSS 0.3V P I DSS /2 0.5Vp I DSS /4 V P 0mA DC load line: V GS = - V GG Intersection between DC load line and trans. Charact. Curve Q point

34 Temperature effect 34 Leakage current I GSS increases when t0 increases cannot neglect RG at mentioned previously so: Q will move from : new Q-point V GS = V GG + I GSS *R G

35 Impact of temperature 35 Question: If V GG =-1V& R G =1 MΩ. I GSS =1nA at 25 C and increase double when temperature increases 10 o C. Determine V GS at 125 o C?

36 Impact of temperature 36 Question: If V GG =-1V& R G =1 MΩ. I GSS =1nA at 25 C and increase double when temperature increases 10 o C. Determine V GS at 125 o C? Answer: At 25 o C, I GSS R G = = 1mV, can be neglected when compare with V GG = - 1V (or new V GS = -999mV). new Q-point When Temp. increases to 125 o C, current I GSS increases to 2 10 times ( 10 3 ) I GSS = nA =1µA I GSS R G =1µA* 1MOhm = 1V New Q point: V GS = 0V & I D = I DSS Q point at C is shifted to a new point and it is far from the initial Q point at room temperature

37 Self biasing 38 What is the main difference compared to fixed biasing? Role of R S? Remove R G to reduce impact of temperature?

38 Self-biasing 39 Loop at input: I G = 0 => V G = 0V V GS = - I S R S (1) I D = I DSS (1-V GS /V p ) 2 (2) To determine Q point: Sole the equation system: (1) + (2) Or by using curve method as shown in the paragraph (intersection point) Consider the impact of Temp.?

39 Voltage divider biasing (ex: JFET) 40 I G = 0, output current I D is controlled by V GS This biasing method is usually used for FET

40 Voltage divider biasing (ex: JFET) 41 V G = V DD R 2 /(R 1 +R 2 ) DC load line is: V GS = V G - I D R S (1) R S varies shift of Q point and DC load line Characteristic curve of FET I D = I DSS (1-V GS /V P ) 2, (2) To determine Q point: Sole the equation system: (1)+(2) Or by using curve method as shown in the paragraph (intersection point)

41 Voltage divider biasing (ex: DMOSFET) 42 V G = V DD * 10MΩ/(110MΩ+10MΩ) DC load line: V GS = V G I S *750Ω (1) I D current of DMOS: I D = I DSS (1-V GS /V P ) 2 (2) To determine Q point: Sole the equation system: (1) + (2) Or by using curve method as shown in the paragraph (intersection point)

42 Voltage divider biasing (ex: DMOSFET) 43 With DMOS: I D = I DSS (1-V GS /V P ) 2 V GS can be positive

43 Voltage divider biasing (E-MOSFET) 44 With EMOS: I D = k(v GS -V T ) 2 k=i Don /(V GSon -V T ) 2

44 Voltage divider biasing (ex: E-MOSFET) 45 With EMOS: I D = k(v GS -V T ) 2 where k = I D-on /(V GSon -V T ) 2 Draw transfer characteristic curve of E-MOSFET

45 Feedback biasing (ex: E-MOSFET) 46 At the node G: I G = 0 V G = V D

46 Feedback biasing (ex: E-MOSFET) 47 At the node G: I G = 0 => V G = V D DC load line V GS = V DS = V DD - R D I D (1) Transfer char. equation: I D = k(v GS - V T ) 2, (2) k = I Don /(V GSon -V T ) 2 Solve equ. Sys. (1,2) or use paragraph method

47 Example 48 Question: Determine Q (I D, V GS ) point Q of these circuits?

48 Example 49 Question: Determine Q (I D, V GS ) point Q of these circuits?

49 Example 50 Question: Determine V GS and V DS for the E-MOSFET circuit above. Given that this MOSFET has minimum values of I D(on) = 200 ma at V GS = 4V and V th = 2V. Question: Determine I D with V th = 3V.

50 51 Analyze the circuit for AC signal (small signal)

51 52 Small signal model

52 Transconductance 53 g m = I D / V GS = d(i D (V GS )) Derivation of current I D as function of V GS Slope of I D (V GS ) at Q point

53 Transconductance g m (JFET & DMOS) 54 For E-MOS; gm is defined from Shockley equation: g m 2I V DSS P 1 V V GS P When V GS = 0: g m determined at Q point: g g m m0 g 2I V m0 DSS P V 1 V GS P

54 Transconductance g m (E-MOSFET) 55 For JFET & DMOS, gm is defined from: g m determined at Q point:

55 AC equivalent circuit (EMOS) 56 Notes: V GS should be positive for NMOS and negative for PMOS g m = 2k(V GS V T )

56 3 types of MOSFET amplifier 57 CS CD - CG

57 58 EMOS CS with fixed bias voltage VDD Input at G terminal, output at D terminal Common Source RD Vout Fixed biasing (S grounded) Vin Cin RG Cout N-EMOS To draw AC equivalent circuit Short circuit all capacitors + V1 10V Short circuit power supply AC equivalent circuit

58 59 EMOS CS with fixed bias voltage Z i = R G Z o = r d //R D R D if r d > 10R D A V = - g m (r D //R D ) - g m R D if r d > 10R D Input and output voltage are out of phase

59 60 EMOS CS with voltage divider Input at G terminal, output at D terminal Common Source Voltage divider S terminal is connected to Rs and Cs in parralel Vin C1 1uF R1 G R2 D S VDD RD Vout Cout N-EMOS RS Cs AC equivalent circuit

60 61 EMOS CS with voltage divider Z i = R 1 // R 2 Z o = r d //R D R D nếu r d > 10R D A V = -g m (r D //R D ) g m R D nếu r d > 10R D Input and output voltage are out of phase

61 EMOS CS with voltage divider and wo. Cs 62 Input at G terminal, output at D terminal Common Source Voltage divider S terminal is connected to ONLY Rs and REMOVE bypass-capacitor C S Vin C1 1uF R1 G R2 D S VDD RD Cout N-EMOS RS X Vout Cs????? AC equivalent circuit

62 EMOS CS with voltage divider and wo. Cs 63 Input at G terminal, output at D terminal Common Source Voltage divider S terminal is connected to ONLY Rs and REMOVE bypass-capacitor C S Vin C1 1uF R1 G R2 D S VDD RD Vout Cout N-EMOS RS X Cs AC equivalent circuit

63 EMOS CS with voltage divider and wo. Cs 64 Z i = R G (or R1//R2) Z o = R D /[1+g m R S +(R D +R S )/r d ] A V = -g m R D /[1+g m R S +(R D +R S )/r d ] Input and output voltage are out of phase

64 EMOS CS with feedback bias 65 Input at G terminal, output at D terminal: Common Source Feedback biasing To draw AC equivalent circuit Short circuit all capacitors Short circuit power supply

65 EMOS CS with feedback bias 66 AC equivalent circuit Short circuit all capacitors Short circuit power supply

66 EMOS CS with feedback bias 67 Z i = (R F +r d //R D )/[1+g m (r d //R D )] R F /(1+g m R D ) with r d >10R D, R F >>r d //R D Z o = R F //r d //R D R D with r d >10R D, R F >>r d //R D A V = g m R F //r d //R D g m R D with r d >10R D, R F >>r d //R D Output and input voltage are out of phase

67 68 EMOS CS with feedback bias

68 69 EMOS CS with feedback bias

69 70 EMOS CS with feedback bias

70 JFET CD with fixed biasing 71 Input at G terminal, output at S terminal: Common Drain Fixed biasing

71 JFET CD with fixed biasing 72 Z i = R G Z o = r d //R S //(1/g m ) R S //(1/g m ) if r d > 10R S A V = -g m (r d //R S )/[1+g m (r d //R S )] g m R S /[1+g m R S )] if r d > 10R S 1 if g m R S >> 1

72 73 JFET CG with fixed biasing Input at S terminal, output at D terminal: Common GATE Fixed biasing

73 74 JFET CG with fixed biasing Z i = R s //[(r d +R D )/(1+g m r d )] R S //(1/g m ) nếu r d >10R D Z o = r d //R D R D nếu r d >10R D A V = [g m R D + (R D /r d )]/[1+ R D /r d ] g m R D nếu r d >10R D Input and output voltage are IN-PHASE

74 Equivalent circuit for DMOS 76 Similar to JFET and E-MOSFET For DMOS: V GS can be positive for Nchannel and negative for P channel g m can be higher than g m0

75 77 Resume

76 78 Resume

77 Exercises 79 Chapter 5: 3, 5, 6, 9, 26, 34, 37 Chapter 6: 1, 6, 12, 17, 19, 21, 23 Chapter 9: 1, 5, 12, 17, 19, 23, 27, 32, 33, 37, 38, 43, 44

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