DISCRETE SEMICONDUCTORS DATA SHEET. BLF245 VHF power MOS transistor
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1 DISCRETE SEMICONDUCTORS DATA SHEET September 1992
2 FEATURES High power gain Low noise figure Easy power control Good thermal stability Withstands full load mismatch. DESCRIPTION Silicon N-channel enhancement mode vertical D-MOS transistor designed for large signal amplifier applications in the VHF frequency range. The transistor is encapsulated in a 4-lead SOT123 flange envelope, with a ceramic cap. All leads are isolated from the flange. Matched gate-source voltage (V GS ) groups are available on request. PINNING - SOT123 PIN DESCRIPTION 1 drain 2 source 3 gate 4 source PIN CONFIGURATION fpage MSB57 Fig.1 Simplified outline and symbol. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static charge during transport and handling. WARNING Product and environmental safety - toxic materials This product contains beryllium oxide. The product is entirely safe provided that the BeO disc is not damaged. All persons who handle, use or dispose of this product should be aware of its nature and of the necessary safety precautions. After use, dispose of as chemical or special waste according to the regulations applying at the location of the user. It must never be thrown out with the general or domestic waste. g MBB72 d s QUICK REFERENCE DATA RF performance at T h = 25 C in a class-b test circuit. MODE OF OPERATION f (MHz) CW, class-b > 13 > 5 V DS (V) P L (W) G p (db) η D (%) September
3 LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DS drain-source voltage V GS = 65 V ±V GS gate-source voltage V DS = 2 V I D DC drain current 6 A P tot total power dissipation up to T mb = 25 C 68 W T stg storage temperature C T j junction temperature 2 C THERMAL RESISTANCE R th j-mb R th mb-h SYMBOL PARAMETER CONDITIONS THERMAL RESISTANCE thermal resistance from T mb =25 C; P tot = 68 W 2.6 K/W junction to mounting base thermal resistance from T mb =25 C; P tot = 68 W.3 K/W mounting base to heatsink 1 I D (A) (1) (2) MRA921 1 P tot (W) 8 MGP (2) (1) V DS (V) T h ( C) (1) Current is this area may be limited by R DS(on). (2) T mb =25 C. (1) Continuous operation. (2) Short-time operation during mismatch. Fig.2 DC SOAR. Fig.3 Power/temperature derating curves. September
4 CHARACTERISTICS T j = 25 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS drain-source breakdown voltage V GS = ; I D =1mA 65 V I DSS drain-source leakage current V GS = ; V DS = 28 V 2 ma I GSS gate-source leakage current ±V GS = 2 V; V DS = 1 µa V GS(th) gate-source threshold voltage I D = 1 ma; V DS = 1 V V V GS gate-source voltage difference of I D = 1 ma; V DS = 1 V 1 mv matched devices g fs forward transconductance I D = 1.5 A; V DS = 1 V S R DS(on) drain-source on-state resistance I D = 1.5 A; V GS = 1 V.4.75 Ω I DSX on-state drain current V GS = 1 V; V DS = 1 V 1 A C is input capacitance V GS = ; V DS = 28 V; f = 1 MHz 125 pf C os output capacitance V GS = ; V DS = 28 V; f = 1 MHz 75 pf C rs feedback capacitance V GS = ; V DS = 28 V; f = 1 MHz 7 pf F noise figure (see Fig.14) input and output power matched for: I D = 1 A; V DS =28V; P L =3W; R1 = 1 kω; T h =25 C; f = 175 MHz 2 db 6 T.C. (mv/k) 4 MGP I D (A) T j = 25 C MGP C I D (ma) V GS (V) V DS = 1 V; valid for T j = 25 to 125 C. V DS =1V. Fig.4 Temperature coefficient of gate-source voltage as a function of drain current, typical values. Fig.5 Drain current as a function of gate-source voltage, typical values. September
5 .8 R DS(on) (Ω).6 MGP17 24 C (pf) 2 MGP C is.2 8 C os T j ( C) V DS (V) V GS =1V; I D = 1.5 A. V GS = ; f = 1 MHz. Fig.6 Drain-source on-state resistance as a function of junction temperature, typical values. Fig.7 Input and output capacitance as functions of drain-source voltage, typical values. 2 MRA92 C rs (pf) V DS (V) 3 V GS = ; f = 1 MHz. Fig.8 Feedback capacitance as a function of drain-source voltage, typical values. September
6 APPLICATION INFORMATION FOR CLASS-B OPERATION T h = 25 C; R th mb-h =.3 K/W; R1 = 1 kω. RF performance in CW operation in a common source class-b test circuit. MODE OF OPERATION f (MHz) V DS (V) I DQ (ma) P L (W) G P (db) CW, class-b > 13 typ η D (%) < 5 typ. 67 Z i (Ω) (note 1) Z L (Ω) 2. j j typ. 12 typ j j1.3 Note 1. R1 included. Ruggedness in class-b operation The is capable of withstanding a load mismatch corresponding to VSWR = 5 through all phases under the following conditions: T h =25 C; R th mb-h =.3 K/W; at rated load power. 2 G p (db) G p MGP172 1 η D (%) 6 P L (W) 5 MEA736 η D P L (W) P IN (W) Class-B operation; V DS = 28 V; I DQ =5mA; f = 175 MHz; T h =25 C; R th mb-h =.3 K/W. Class-B operation; V DS = 28 V; I DQ =5mA; f = 175 MHz; T h =25 C; R th mb-h =.3 K/W. Fig.9 Power gain and efficiency as functions of load power, typical values. Fig.1 Load power as a function of input power, typical values. September
7 +V GG +V DD Philips Semiconductors 2 MGP MEA737 G p (db) η D (%) P L (W) η D G p P L (W) P IN (W) Class-B operation; V DS = 12.5 V; I DQ = 5 ma; f = 175 MHz; T h =25 C; R th mb-h =.3 K/W. Class-B operation; V DS = 12.5 V; I DQ = 5 ma; f = 175 MHz; T h =25 C; R th mb-h =.3 K/W. Fig.11 Power gain and efficiency as functions of load power, typical values. Fig.12 Load power as a function of input power, typical values. handbook, full pagewidth 5 Ω input C1 L1 Z i L2 D.U.T. L3 L6 C7 C8 C1 C9 5 Ω output C2 R2 R1 C3 C5 L4 C6 R3 C4 L5 MGP174 f = 175 MHz. Fig.13 Test circuit for class-b operation. September
8 List of components (class-b test circuit) COMPONENT DESCRIPTION VALUE DIMENSIONS CATALOGUE NO. C1 film dielectric trimmer 4 to 4 pf C2, C8 film dielectric trimmer 5 to 6 pf C3 multilayer ceramic chip capacitor 1 pf C4, C6 multilayer ceramic chip capacitor 1 nf C5 ceramic capacitor 1 pf C7 multilayer ceramic chip capacitor 18 pf (note 1) C9 multilayer ceramic chip capacitor 27 pf (note 1) C1 multilayer ceramic chip capacitor 24 pf (note 1) L1 3 turns enamelled.5 mm copper 13.5 nh length 3.5 mm wire int. dia. 2 mm leads 2 2mm L2, L3 stripline (note 2) 3 Ω 1 6mm L4 6 turns enamelled 1.5 mm copper wire 98 nh length 12.5 mm int. dia. 5 mm leads 2 2mm L5 grade 3B Ferroxcube RF choke L6 2 turns enamelled 1.5 mm copper wire 24.5 nh length 4 mm int. dia. 5 mm leads 2 2mm R1 metal film resistor 1 kω R2 metal film resistor 1 MΩ R3 metal film resistor 1 Ω Notes 1. American Technical Ceramics (ATC) capacitor, type 1B or other capacitor of the same quality. 2. The striplines are mounted on a double copper-clad PCB with epoxy fibre-glass dielectric (ε r = 4.5), thickness 1 16 inch. September
9 handbook, full pagewidth 135 copper straps rivets 72 copper strap copper straps +V GG L5 +VDD C3 C4 C5 C1 C2 R2 R1 L1 L2 L4 L3 C6 C7 L6 R3 C8 C9 C1 MGP175 The circuit and components are situated on one side of the epoxy fiber-glass board; the other side is unetched copper and serves as an earth. Earth connections are made by means of fixing screws, hollow rivets and copper straps under the sources and around the edges, to provide a direct contact between the copper on the component side and the ground plane. Dimensions in mm. Fig.14 Component layout for 175 MHz class-b test circuit. September
10 4 Z i (Ω) MGP Z L (Ω) MGP R L x i 4 X L r i f (MHz) Class-B operation; V DS = 28 V; I DQ =5mA; P L = 3 W; T h =25 C; R th mb-h =.3 K/W f (MHz) Class-B operation; V DS = 28 V; I DQ =5mA; P L = 3 W; T h =25 C; R th mb-h =.3 K/W. Fig.15 Input impedance as a function of frequency (series components), typical values. Fig.16 Load impedance as a function of frequency (series components), typical values. 4 G p (db) MGP Z i Z L MBA f (MHz) Class-B operation; V DS = 28 V; I DQ =5mA; P L = 3 W; T h =25 C; R th mb-h =.3 K/W. Fig.17 Definition of MOS impedance. Fig.18 Power gain as a function of frequency, typical values. September
11 PACKAGE OUTLINE Flanged ceramic package; 2 mounting holes; 4 leads SOT123A D A F q U 1 C B H L 4 3 w 2 M b C c α A p U 2 U 3 1 w 1 M A B H 2 Q 5 1 mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT A b c D D 1 F H L p Q q U 1 U 2 U 3 w 1 w 2 α mm inches OUTLINE VERSION REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT123A September
12 DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September
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DISCRETE SEMICONDUCTORS DT SHEET MOSFET N-channel depletion switching transistor File under Discrete Semiconductors, SC07 December 1997 DESCRIPTION Marking code: M32 Symmetrical insulated-gate silicon
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M3D88 Rev. 2 24 June 24 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. 1.2 Features TrenchMOS technology
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M3D88 Rev. 2 19 February 23 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. Product availability: in
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Rev. 1 12 May 24 Product data 1. Product profile 1.1 Description Logic level N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS technology. 1.2 Features Logic level
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Important notice Dear Customer, On 7 February 27 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and
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More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 217 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
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Important notice Dear Customer, On February the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
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Important notice Dear Customer, On 7 February 217 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic
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