Monolithic N-Channel JFET Dual
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1 N98 Monolithic N-Channel JFET Dual V GS(off) (V) V (BR)GSS Min (V) g fs Min (ms) I G Max (pa) V GS V GS Max (mv). to. Monolithic Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: pa Low Noise: 9 nv Hz High CMRR: db Tight Differential Match vs. Current Improved Op Amp Speed, Settling Time Accuracy Minimum Input Error/Trimming Requirement Insignificant Signal Loss/Error Voltage High System Sensitivity Minimum Error with Large Input Signal Wideband Differential Amps High-Speed, Temp-Compensated, Single-Ended Input Amps High Speed Comparators Impedance Converters The low cost N98 JFET dual is designed for high-performance differential amplification for a wide range of precision test instrumentation applications. This series features tightly matched specs, low gate leakage for accuracy, and wide dynamic range with I G guaranteed at V DG = V. The hermetically-sealed TO-7 package is available with full military processing (see Military Information and the N/6/7JANTX/JANTXV data sheet). For similar products see N96/97/98/99, the low-noise U/SST series, the high-gain N9/9, and the low-leakage U/ data sheets. TO-7 S G 6 D D G S Top View Gate-Drain, Gate-Source Voltage V Gate Current ma Lead Temperature ( / 6 from case for sec.) C Storage Temperature to C Operating Junction Temperature to C Document Number: 76 S- Rev. B, -Jun- Power Dissipation : Per Side a mw Total b mw Notes a. Derate mw/ C above 8 C b. Derate mw/ C above 8 C 8-
2 N98 Limits Parameter Symbol Test Conditions Min Typ a Max Unit Static Gate-Source Breakdown Voltage V (BR)GSS I G = A, V DS = V 7 V Gate-Source Cutoff Voltage V GS(off) V DS = V, = na.. Saturation Drain Current b SS V DS = V, V GS = V. ma V GS = V, V DS = V pa Gate Reverse Current I GSS T A = C na V DG = V, = A pa Gate Operating Current I G T A = C.8 na V DG = V, = A.. Gate-Source Voltage V GS = A. V Gate-Source Forward Voltage V GS(F) I G = ma, V DS = V Dynamic Common-Source Forward Transconductance g fs VDS = V, V GS = V Common-Source Output Conductance g os f = khz. ms S Common-Source Input Capacitance C iss V DS = V, V GS = V Common-Source C Reverse Transfer Capacitance rss f = MHz. pf Drain-Gate Capacitance C dg V DG = V, I S =, f = MHz. Equivalent Input Noise Voltage e n V DS = V, V GS = V, f = khz 9 Noise Figure Matching NF V DS = V, V GS = V f = Hz, R G = M nv Hz. db Differential Gate-Source Voltage V GS V GS V DG = V, = A mv Gate-Source Voltage Differential Change with Temperature V GS V GS T V DG = V, = A T A = to C V/ C Saturation Drain Current Ratio SS SS V DS = V, V GS = V.8.97 Transconductance Ratio g fs g fs Differential Output Conductance g os g os V DS = V, = A f = khz S Differential Gate Current I G I G V DG = V, = A T A = C. na Common Mode Rejection Ratio c CMRR V DG = to V, = A db Notes a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. NQP b. Pulse test: PW s duty cycle %. c. This parameter not registered with JEDEC. 8- Document Number: 76 S- Rev. B, -Jun-
3 N98 Drain Current and Transconductance vs. Gate-Source Cutoff Voltage na Gate Leakage Current SS Saturation Drain Current (ma) g fs SS V DS = V, V GS = V g V DG = V, V GS = V f = khz g fs Forward Transconductance (ms) I G Gate Leakage na na pa pa pa I = A T A = C I C A A A I C T A = C V GS(off) Gate-Source Cutoff Voltage (V). pa V DG Drain-Gate Voltage (V) V GS(off) = V V GS(off) = V V GS = V. V V GS = V. V. V.6 V.6 V.9 V. V. V. V. V.8 V.8 V. V. V. V V GS(off) = V V GS(off) = V V GS = V. V.6 V GS = V. V..6 V..8. V.6 V.8 V. V...9 V. V. V.8 V.. V.. V. V.6 V. V Document Number: 76 S- Rev. B, -Jun- 8-
4 N98 V GS(off) = V Transfer Characteristics V DS = V V DG = V T A = C Gate-Source Differential Voltage t T A = C C (mv) V GS V GS C V GS Gate-Source Voltage (V) Voltage Differential with Temperature Common Mode Rejection Ratio V DG = V V GS V GS ( V/ C ) T A = to C T A = to C CMRR (db) CMRR = log V DG = V V V DG V GS V GS Circuit Voltage Gain k On-Resistance A V Voltage Gain 8 6. V GS(off) = V A V g fs R L R L g os Assume V DD = V, V DS = V R L V V. r DS(on) Drain-Source On-Resistance ( Ω ) 8 6 V GS(off) = V V.. 8- Document Number: 76 S- Rev. B, -Jun-
5 N98 Ciss Input Capacitance (pf) 8 6 Common-Source Input Capacitance vs. Gate-Source Voltage f = MHz V DS = V V V V 8 6 V GS Gate-Source Voltage (V) Crss Reverse Feedback Capacitance (pf) Common-Source Reverse Feedback Capacitance vs. Gate-Source Voltage f = MHz V DS = V V V V 8 6 V GS Gate-Source Voltage (V) en Noise Voltage nv / Hz 6 8 Equivalent Input Noise Voltage vs. Frequency V DS = ma V GS = V g os Output Conductance (µs)..... Output Conductance V GS(off) = V C T A = C C V DS = V f = khz k k k f Frequency (Hz)... Common-Source Forward Transconductance k On-Resistance and Output Conductance vs. Gate-Source Cutoff Voltage g fs Forward Transconductance (ms).... V GS(off) = V C T A = C C V DS = V f = khz.. r DS(on) Drain-Source On-Resistance ( Ω ) 8 6 g os r DS r = A, V GS = V g V DS = V, V GS = V, f = khz 8 6 gos Output Conductance ( S) V GS(off) Gate-Source Cutoff Voltage (V) Document Number: 76 S- Rev. B, -Jun- 8-
6 Notice Legal Disclaimer Notice Vishay Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. Document Number: 9 Revision: 8-Apr-
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