AOD466 N-Channel Enhancement Mode Field Effect Transistor
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- Bruce Miller
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1 NChannel Enhancement Mode Field Effect Transistor General Description The AOD466 uses advanced trench technology and design to provide excellent R DS(ON) with low gate charge. This device is suitable for use in PWM, load switching and general purpose applications. RoHS Compliant Halogen Free* Features V DS (V) = V I D = 3A (V GS = V) R DS(ON) < 4 mω (V GS = V) R DS(ON) < 24 mω (V GS = 4.V) % UIS Tested! % Rg Tested! Top View D TO2 DPAK Bottom View D S G G S G S Absolute Maximum Ratings T A = C unless otherwise noted Parameter Symbol Maximum DrainSource Voltage GateSource Voltage V DS V GS ± Units V V Continuous Drain T C = C 3 Current G T C = C I D A Pulsed Drain Current C Avalanche Current C Repetitive avalanche energy.mh C I DM I AR E AR 7 A mj T C = C 3 Power Dissipation B P D T C = C W T A = C 2. Power Dissipation A P DSM T A =7 C.6 W Junction and Storage Temperature Range T J, T STG to 7 C Thermal Characteristics Parameter Symbol Typ Max Units Maximum JunctiontoAmbient A t s C/W R θja Maximum JunctiontoAmbient A SteadyState 4 C/W Maximum JunctiontoCase B SteadyState R θjc 3.6 C/W
2 Electrical Characteristics (T J = C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units STATIC PARAMETERS BV DSS DrainSource Breakdown Voltage I D =ua, V GS =V V I DSS Zero Gate Voltage Drain Current V DS =V, V GS =V T J = C μa I GSS GateBody leakage current V DS =V, V GS =±V na V GS(th) Gate Threshold Voltage V DS =V GS, I D =μa.8 2. V I D(ON) On state drain current V GS =V, V DS =V 7 A V GS =V, I D =3A. 4 R DS(ON) Static DrainSource OnResistance T J = C. mω V GS =4.V, I D =A 9 24 mω g FS Forward Transconductance V DS =V, I D =3A 3 S V SD Diode Forward Voltage I S =A, V GS =V.74 V I S Maximum BodyDiode Continuous Current A DYNAMIC PARAMETERS C iss Input Capacitance 83 pf C oss Output Capacitance V GS =V, V DS =2.V, f=mhz 224 pf C rss Reverse Transfer Capacitance 27 pf R g Gate resistance V GS =V, V DS =V, f=mhz.93. Ω SWITCHING PARAMETERS Q g (V) Total Gate Charge.3 9 nc Q g (4.V) Total Gate Charge nc V GS =V, V DS =2.V, I D =3A Q gs Gate Source Charge 2.7 nc Q gd Gate Drain Charge 4.3 nc t D(on) TurnOn DelayTime 8 ns t r TurnOn Rise Time V GS =V, V DS =2.V,.7 ns t D(off) TurnOff DelayTime R L =.42Ω, R GEN =3Ω 3 ns t f TurnOff Fall Time ns t rr Body Diode Reverse Recovery Time I F =3A, di/dt=a/μs ns Q rr Body Diode Reverse Recovery Charge I F =3A, di/dt=a/μs 2.8 nc A: The value of R θja is measured with the device mounted on in 2 FR4 board with 2oz. Copper, in a still air environment with T A = C. The Power dissipation P DSM is based on R θja and the maximum allowed junction temperature of C. The value in any given application depends on the user's specific board design, and the maximum temperature of 7 C may be used if the PCB allows it. B. The power dissipation P D is based on T J(MAX) =7 C, using junctiontocase thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. C: Repetitive rating, pulse width limited by junction temperature T J(MAX) =7 C. D. The R θja is the sum of the thermal impedence from junction to case R θjc and case to ambient. E. The static characteristics in Figures to 6 are obtained using <3 μs pulses, duty cycle.% max. F. These curves are based on the junctiontocase thermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of T J(MAX) =7 C. G. The maximum current rating is limited by bondwires. H. These tests are performed with the device mounted on in 2 FR4 board with 2oz. Copper, in a still air environment with T A = C. The SOA curve provides a single pulse rating. *This device is guaranteed green after data code 8X (Sep ST 8). Rev: Sep. 8 THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.
3 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 8 4 V V DS =V 6 6V 3 I D (A) 4 4.V I D (A) C C V GS =3V V DS (Volts) Fig : OnRegion Characteristics V GS (Volts) Figure 2: Transfer Characteristics.6 R DS(ON) (mω) V GS =4.V V GS =V Normalized OnResistance.4.2 V GS =V I D =3A V GS =4.V I D =A 3 4 I D (A) Figure 3: OnResistance vs. Drain Current and Gate Voltage.8 7 Temperature ( C) Figure 4: OnResistance vs. Junction Temperature 4.E2 R DS(ON) (mω) 3 I D =3A C I S (A).E.E.E.E2.E3 C C C V GS (Volts) Figure : OnResistance vs. GateSource Voltage.E4.E V SD (Volts) Figure 6: BodyDiode Characteristics
4 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS V GS (Volts) V DS =2.V I D =3A Q g (nc) Figure 7: GateCharge Characteristics Capacitance (pf) C rss C iss C oss V DS (Volts) Figure 8: Capacitance Characteristics I D (Amps) R DS(ON) limited DC μs μs ms Power (W) 6 8 T J(Max) =7 C T C = C T J(Max) =7 C, T A = C.. V DS (Volts) Figure 9: Maximum Forward Biased Safe Operating Area (Note F) Figure : Single Pulse Power Rating Junctionto Case (Note F) Z θjc Normalized Transient Thermal Resistance. D=T on /T T J,PK =T C P DM.Z θjc.r θjc R θjc = C/W In descending order D=.,.3,.,.,.2,., single pulse Single Pulse P D. T..... Figure : Normalized Maximum Transient Thermal Impedance (Note F) T on
5 TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS I D (A), Peak Avalanche Current 3 T A = C t A = L I D BV V DD Power Dissipation (W) 3... Time in avalanche, t A (s) Figure 2: Single Pulse Avalanche capability 7 7 T CASE ( C) Figure 3: Power Derating (Note B) Current rating I D (A) 3 Power (W) 4 3 T A = C 7 7 T CASE ( C) Figure 4: Current Derating (Note B).... Figure : Single Pulse Power Rating Junctionto Ambient (Note H) Z θja Normalized Transient Thermal Resistance.. Single Pulse In descending order D=.,.3,.,.,.2,., single pulse D=T on /T T J,PK =T A P DM.Z θja.r θja R θja = C/W T Figure 6: Normalized Maximum Transient Thermal Impedance (Note H) P D T on
6 Gate Charge Test Circuit & Waveform Qg V Qgs Qgd Ig Charge Resistive Switching Test Circuit & Waveforms RL Rg 9% % td(on) t r t d(off) t f t on t off Unclamped Inductive Switching (UIS) Test Circuit & Waveforms L 2 E = /2 LI AR AR BV DSS Id Rg Id I AR Diode Recovery Test Circuit & Waveforms Q = Idt rr Ig Isd L Isd I F di/dt I RM t rr
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SIPMOS PowerTransistor Features N channel Enhancement mode valanche rated dv/dt rated 75 C operating temperature Product Summary Drain source voltage V DS 55 V DrainSource onstate resistance R DS(on).5
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P-Channel MOSFET Description The enhancement mode MOS is extremely high density cell and low on-resistance. D(3) MOSFET Product Summary V DS (V) R DS(on) (Ω) I D (A) 0.11 @ V GS =-10V -60 0.13 @ V GS =-4.5V
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PHDE GENERAL DESCRIPTION QUICK REFERENCE DATA Nchannel enhancement mode SYMBOL PARAMETER MAX. UNIT fieldeffect power transistor in a plastic envelope suitable for surface V DS Drainsource voltage 6 V mounting
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IPB12CN1N G OptiMOS 2 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Product Summary V DS 1 V R DS(on),max (TO252) 12.4
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OptiMOS 2 Power-Transistor Features Ideal for high-frequency dc/dc converters Qualified according to JEDEC 1) for target application N-channel, logic level Product Summary V DS 25 V R DS(on),max (SMD version)
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IPB26CN1N G IPD25CN1N G OptiMOS 2 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Product Summary V DS 1 V R DS(on),max
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P Channel Logic Level Enhancement Mode Field Effect Transistor Product Summary: BVDSS V RDSON (MAX.) ID 5mΩ.5A Pb Free Lead Plating & Halogen Free D G S ABSOLUTE MAXIMUM RATINGS (T A = 5 C Unless Otherwise
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Preliminary Technical Information TrenchT2 TM Power MOSFET N-Channel Enhancement Mode Avalanche Rated V DSS I D25 R DS(on) TO-263 (IXTA) = V = A 7mΩ Symbol Test Conditions Maximum Ratings V DSS T J = 25
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BUK86A GENERAL DESCRIPTION QUICK REFERENCE DATA Nchannel enhancement mode SYMBOL PARAMETER MAX. UNIT logic level fieldeffect power transistor in a plastic envelope V DS Drainsource voltage 6 V suitable
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OptiMOS 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Product Summary V DS 1 V R DS(on),max 7.2 mω I D 8 A Very low on-resistance R DS(on) 175 C operating
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OptiMOS 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Product Summary V DS 8 V R DS(on),max 2.8 mω I D 1 A Very low on-resistance R DS(on) 175 C operating
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OptiMOS &!Power-Transistor Feature % N-Channel % Enhancement mode % Logic Level % High Current Rating % Excellent Gate Charge x R DS(on) product (FOM) %!Superior thermal resistance %!175 C operating temperature
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BSO15N3MD G OptiMOS 3 M-Series Power-MOSFET Features Dual N-channel Optimized for 5V driver application (Notebook, VGA, POL) Low FOM SW for High Frequency SMPS 1% Avalanche tested Product Summary V DS
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1 Description These N-Channel enhancement mode power field effect transistors are produced using planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state
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IPB2N25N3 G OptiMOS TM 3 Power-Transistor Features N-channel, normal level Excellent gate charge x R DS(on) product (FOM) Very low on-resistance R DS(on) Product Summary V DS 25 V R DS(on),max 2 mw I D
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OptiMOS PowerTransistor Feature NChannel Enhancement mode Excellent Gate Charge x R DS(on) product (FOM) Superior thermal resistance 175 C operating temperature valanche rated dv/dt rated Product Summary
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OptiMOS P Small-Signal-Transistor Features P-channel Enhancement mode Super Logic Level (.5V rated) Avalanche rated Qualified according to AEC Q % lead-free; RoHS compliant Product Summary V DS - V R DS(on),max
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BSO33N3MS G OptiMOS 3 M-Series Power-MOSFET Features Optimized for 5V driver application (Notebook, VGA, POL) Low FOM SW for High Frequency SMPS % Avalanche tested N-channel Product Summary V DS 3 V R
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N Channel Logic Level Enhancement Mode Field Effect Transistor Product Summary: BVDSS RDSON (MX.) ID D 6V 6mΩ G UIS, Rg % Tested Pb Free Lead Plating & Halogen Free S BSOLUTE MXIMUM RTINGS (T C = 5 C Unless
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