Monolithic N-Channel JFET Dual
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1 SST Monolithic N-Channel JFET Dual V GS(off) (V) V (BR)GSS Min (V) Min (ms) I G Typ (pa) V GS V GS Max (mv) to 6. Monolithic Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: pa Low Noise High CMRR: 9 db Tight Differential Match vs. Current Improved Op Amp Speed, Settling Time Accuracy High-Speed Performance Minimum Input Error/Trimming Requirement Insignificant Signal Loss/Error Voltage High System Sensitivity Minimum Error with Large Input Signal Wideband Differential Amps High-Speed, Temp-Compensated, Single-Ended Input Amps High Speed Comparators Impedance Converters The SST is a monolithic high-speed dual JFET mounted in a single SO- package. This JFET is an excellent choice for use as wideband differential amplifiers in demanding test and measurement applications. The SO- package is available with tape-and-reel options to support automated assembly (see Packaging Information). For similar products in TO-7 packaging, see the U data sheet. Narrow Body SOIC S NC D 7 G G 3 6 D NC S Top View Gate-Drain, Gate-Source Voltage V Gate Current ma Lead Temperature ( / 6 from case for sec.) C Storage Temperature to C Operating Junction Temperature to C Power Dissipation : Per Side a mw Total a mw Notes a. Derate. mw/ C above C For applications information see AN. Document Number: 7 S-3 Rev. E, -Jun- -
2 SST Static Limits Parameter Symbol Test Conditions Min Typ a Max Unit Gate-Source Breakdown Voltage V (BR)GSS I G = A, V DS = V 3 Gate-Source Cutoff Voltage V GS(off) V DS = V, I D = na 3. 6 Saturation Drain Current b I DSS V DS = V, V GS = V 6 3 ma V GS = V, V DS = V pa Gate Reverse Current I GSS T A = C. na V DG = V, I D = ma pa Gate Operating Current I G T A = C. na Gate-Source Forward Voltage V GS(F) I G = ma, V DS = V.7 V Dynamic Forward Transconductance Output Conductance Forward Transconductance Output Conductance Input Capacitance Reverse Transfer Capacitance g os g os C iss C rss V DS = V, I D = ma f = khz V DS = V, I D = ma f = MHz V DS = V, I D = ma f = MHz Equivalent Input Noise Voltage e n V DS = V, I D = ma f = khz Matching. 6 9 ms V S. ms 3 S Differential Gate-Source Voltage V GS V GS V DG = V, I D = ma 7 mv 3. pf nv Hz Gate-Source Voltage Differential Change with Temperature V GS V GS T V DG = V, I D = ma T A = to C V/ C Saturation Drain Current Ratio c I DSS I DSS V DS = V, V GS = V.9 Transconductance Ratio c V DS = V, I D = ma f = khz.9 Common Mode Rejection Ratio CMRR V DG = to V, I D = ma 9 db Notes a. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. NNZ b. Pulse test: PW 3 s duty cycle 3%. c. Assumes smaller value in the numerator. - Document Number: 7 S-3 Rev. E, -Jun-
3 SST I DSS Saturation Drain Current (ma) Drain Current and Transconductance vs. Gate-Source Cutoff Voltage I V DS = V, V GS = V DG = V, V GS = V f = khz I DSS 3 V GS(off) Gate-Source Cutoff Voltage (V) Forward Transconductance (ms) I G Gate Leakage na na na pa pa pa. pa T A = C T A = C Gate Leakage Current ma A I I D = ma A ma ma I C I C V DG Drain-Gate Voltage (V) 6 V GS(off) = V V GS = V V GS = V. V. V. V.6 V. V. V. V.6 V. V. V. V 6. V 6. V 3 V GS = V. V.6 V. V. V. V. V.6 V 6 V GS(off) = V V GS = V. V. V. V.6 V. V. V. V Document Number: 7 S-3 Rev. E, -Jun- -3
4 SST 6 Transfer Characteristics t V DS = V Gate-Source Differential Voltage V DG = V T A = C T A = C C (mv) V GS V GS C V GS Gate-Source Voltage (V) Voltage Differential with Temperature Common Mode Rejection Ratio ( V/ C ) V DG = V T A = to C T A = to C 3 CMRR = log V DG V GS V GS V GS V GS CMRR (db) 9 V DG = V V 7.. Circuit Voltage Gain On-Resistance A V Voltage Gain 6 R L A V R L g os Assume V DD = V, V DS = V R L V V I D r DS(on) Drain-Source On-Resistance ( Ω ) 6 V... - Document Number: 7 S-3 Rev. E, -Jun-
5 SST Ciss Input Capacitance (pf) 6 Input Capacitance vs. Gate-Source Voltage f = MHz V DS = V V V 6 Crss Reverse Feedback Capacitance (pf) 3 Reverse Feedback Capacitance vs. Gate-Source Voltage f = MHz V DS = V V V 6 V GS Gate-Source Voltage (V) V GS Gate-Source Voltage (V) Output Conductance Equivalent Input Noise Voltage vs. Frequency g os Output Conductance (µs) 3 C V DS = V f = khz T A = C C en Noise Voltage nv / Hz 6 V DS = V I ma V GS = V. k k k f Frequency (Hz) Forward Transconductance On-Resistance and Output Conductance vs. Gate-Source Cutoff Voltage Forward Transconductance (ms) 6 C T A = C V DS = V f = khz C. r DS(on) Drain-Source On-Resistance ( Ω ) r DS g os r I D = ma, V GS = V g V DG = V, V GS = V, f = khz 3 gos Output Conductance ( S) V GS(off) Gate-Source Cutoff Voltage (V) Document Number: 7 S-3 Rev. E, -Jun- -
6 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, Vishay ), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 9 Revision: -Jul-
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