N- and P-Channel 30 V (D-S) MOSFET

Transcription

1 N and PChannel 3 V (DS) MOSFET Si539DDL D 6 SOT363 SC7 Dual (6 leads) S 4 G 5 FEATURES TrenchFET power MOSFET % R g tested Material categorization: for definitions of compliance please see Marking code: RI S Top View G 3 D APPLICATIONS DC/DC converter Load switch D S PRODUCT SUMMARY NCHANNEL PCHANNEL V DS (V) 3 3 R DS(on) (Ω) at V GS = ± V R DS(on) (Ω) at V GS = ± 4.5 V Q g typ. (nc).55.8 I D (A) a.7.46 Configuration Dual ORDERING INFORMATION Package Lead (Pb)free and halogenfree G G S D NChannel MOSFET PChannel MOSFET SOT363 Si539DDLTGE3 ABSOLUTE MAXIMUM RATINGS (T A = 5 C, unless otherwise noted) PARAMETER SYMBOL NCHANNEL PCHANNEL UNIT Drainsource voltage V DS 3 3 V Gatesource voltage V GS ± ± T C = 5 C.7.46 T C = 7 C.6.36 Continuous drain current (T J = 5 C) I D T A = 5 C.7 b, c.4 b, c T A = 7 C.5 b, c.33 b, c A T C = 5 C.3.3 Sourcedrain current diode current I S T A = 5 C. b, c. b, c Pulsed drain current (t = μs) I DM T C = 5 C T C = 7 C.. Maximum power dissipation P D W T A = 5 C.9 b, c.9 b, c T A = 7 C.8 b, c.8 b, c Operating junction and storage temperature range T J, T stg 55 to +5 C THERMAL RESISTANCE RATINGS PARAMETER SYMBOL NCHANNEL PCHANNEL TYP. MAX. TYP. MAX. Maximum junctiontoambient b, d t s R thja Maximum junctiontofoot (drain) Steady state R thjf Notes a. Based on T C = 5 C b. Surface mounted on " x " FR4 board c. t = s d. Maximum under steady state conditions is 486 C/W (NChannel) and 486 C/W (PChannel) UNIT C/W S79Rev. B, 3Jul7 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

2 Si539DDL SPECIFICATIONS (T J = 5 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. a MAX. UNIT Static V GS = V, I D = 5 μa NCh 3 Drainsource breakdown voltage V DS V GS = V, I D = 5 μa PCh 3 I D = 5 μa NCh 3 V DS temperature coefficient ΔV DS /T J I D = 5 μa PCh 5 I D = 5 μa NCh 3.6 V GS(th) temperature coefficient ΔV GS(th) /T J I D = 5 μa PCh 3. V DS = V GS, I D = 5 μa NCh..5 Gatesource threshold voltage V GS(th) V DS = V GS, I D = 5 μa PCh.5 3 Gatebody leakage I GSS V DS = V, V GS = ± V Zero gate voltage drain current Onstate drain current b I DSS I D(on) NCh ± PCh ± V DS = 3 V, V GS = V NCh V DS = 3 V, V GS = V PCh V DS = 3 V, V GS = V, T J = 55 C NCh V DS = 3 V, V GS = V, T J = 55 C PCh V DS = 5 V, V GS = V NCh V DS = 5 V, V GS = V PCh V GS = V, I D =.6 A NCh V GS = V, I D =.4 A PCh.89.7 Drainsource onstate resistance b R DS(on) V GS = 4.5 V, I D =.A NCh V GS = 5 V, I D =. A PCh V GS = 4.35 V, I D =. A.8 V DS = 5 V, I D =.6 A NCh. Forward transconductance b g fs V DS = 5 V, I D =.4 A PCh.6 Dynamic a NCh 8 Input capacitance C iss NChannel PCh Output capacitance Reverse transfer capacitance C oss C rss V DS = 5 V, V GS = V, f = MHz V DS = 5 V, V GS = V, f = MHz NCh NCh 5 PChannel PCh PCh 6 Total gate charge Q g V DS = 5 V, V GS = V, I D =.6 A NCh.5 V DS = 5 V, V GS = V, I D =.4 A PCh.5 3 NChannel PCh.8. Gatesource charge Gatedrain charge Q gs Q gd V DS = 5 V, V GS = 4.5 V I D =.6 A V DS = 5 V, V GS = 4.5 V, I D =.4 A NCh NCh.. PChannel PCh PCh.4.35 Gate resistance R g f = MHz NCh.55. NCh PCh V mv/ C V na μa A Ω S pf nc Ω S79Rev. B, 3Jul7 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

3 Si539DDL Turnon delay time t d(on) SPECIFICATIONS (T J = 5 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. a MAX. UNIT Dynamic a NCh PCh Rise time t r NChannel V DD = 5 V, R L = 3 Ω NCh 4 I D.5 A, V GEN = V, R g = Ω PCh 8 3 Turnoff delay time t d(off) PChannel NCh V DD = 5 V, R L = 38 Ω I D.4 A, V GEN = V, R g = Ω PCh 8 6 Fall time t f PCh 8 3 NCh 6 39 Turnon delay time t d(on) PCh 33 NCh 9 8 ns Rise time t r NChannel V DD = 5 V, R L = 3 Ω NCh 5 38 I D.5 A, V GEN = 4.5 V, R g = Ω PCh 8 4 Turnoff delay time t d(off) PChannel NCh 4 V DD = 5 V, R L = 5 Ω I D.3 A, V GEN = 4.5 V, R g = Ω PCh 4 8 NCh 5 3 Fall Time t f PCh 8 3 DrainSource Body Diode Characteristics Continuous sourcedrain diode current I S T C = 5 C Pulse diode forward current (t = μs) Notes a. Guaranteed by design, not subject to production testing b. Pulse test; pulse width 3 μs, duty cycle % NCh.3 PCh.3 I SM PCh NCh I S =.5 A NCh.8. Body diode voltage V SD I S =.4 A PCh.8. Body diode reverse recovery time t rr NCh PCh 3 Body diode reverse recovery charge Q rr NChannel NCh 3 6 I F =.5 A, di/dt = A/μs, T J = 5 C PCh 8 6 Reverse recovery fall time t a PChannel NCh 6 I F =.5 A, di/dt = A/μs, T J = 5 C PCh 7 NCh 4 Reverse recovery rise time t b PCh 6 A V ns nc ns Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S79Rev. B, 3Jul7 3 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

4 Si539DDL NCHANNEL TYPICAL CHARACTERISTICS (5 C, unless otherwise noted).5 V GS = V thru 5 V.5 V GS = 4 V.4 I D Drain Current (A).5 V GS = 3 V.5.5 I D Drain Current (A).3 T C = 5 C.. T C = 5 C T C = 55 C 3 4 V DS DraintoSource Voltage (V) V GS GatetoSource Voltage (V) Output Characteristics Transfer Characteristics.8 4 R DS(on) OnResistance (Ω).6.4. V GS = 4.5 V V GS = V C Capacitance (pf) 3 C oss C iss C rss..5.5 I D Drain Current (A) OnResistance vs. Drain Current and Gate Voltage V DS DraintoSource Voltage (V) Capacitance.8 V GS GatetoSource Voltage (V) I D =.6 A V DS = 7.5 V V DS = 5 V V DS = 4 V R DS(on) OnResistance (Normalized).5..9 I D =.6 A V GS = V Q g Total Gate Charge (nc) Gate Charge V.6 GS = 4.5 V T J Junction Temperature ( C) OnResistance vs. Junction Temperature S79Rev. B, 3Jul7 4 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

5 Si539DDL NCHANNEL TYPICAL CHARACTERISTICS (5 C, unless otherwise noted).8 I D =.6 A I S Source Current (A) T J = 5 C T J = 5 C R DS(on) OnResistance (Ω).6.4. T J = 5 C T J = 5 C V SD SourcetoDrain Voltage (V) SourceDrain Diode Forward Voltage V GS GatetoSource Voltage (V) OnResistance vs. GatetoSource Voltage V GS(th) (V).6 I D = 5 μa Power (W) T J Temperature( C) Threshold Voltage... Time (s) Single Pulse Power, JunctiontoAmbient Limited by R DS(on) * Limited by I DM BVDSS Limited I D Drain Current (A). μs ms ms ms T A = 5 C Single Pulse s. s, DC. V DS DraintoSource Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Safe Operating Area, JunctiontoAmbient S79Rev. B, 3Jul7 5 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

6 Si539DDL NCHANNEL TYPICAL CHARACTERISTICS (5 C, unless otherwise noted).8.6 I D Drain Current (A) T C Case Temperature ( C) Current Derating a Power (W).7.8 Power (W) T C Case Temperature ( C) T A Ambient Temperature ( C) Power Derating, JunctiontoFoot Power Derating, JunctiontoAmbient Note a. The power dissipation P D is based on T J max. = 5 C, using junctiontocase thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit S79Rev. B, 3Jul7 6 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

7 Si539DDL NCHANNEL TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) Normalized Effective Transient Thermal Impedance. Duty Cycle = Single Pulse..... Square Wave Pulse Duration (s) Notes: Normalized Thermal Transient Impedance, JunctiontoAmbient P DM t t t. Duty Cycle, D = t. Per Unit Base =R thja = 486 C/W 3. T JM T A =P DM Z (t) thja 4. Surface Mounted Normalized Effective Transient Thermal Impedance. Duty Cycle = Single Pulse..... Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, JunctiontoFoot S79Rev. B, 3Jul7 7 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

8 Si539DDL PCHANNEL TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) V GS = V thru 7V..75 V GS = 6 V.8 I D Drain Current (A).5.5 V GS = 4 V V GS = 5 V I D Drain Current (A).6.4. T C = 5 C T C = 5 C T C = 55 C.5.5 V DS DraintoSource Voltage (V) Output Characteristics V GS GatetoSource Voltage (V) Transfer Characteristics V GS = 4.35 V 3 R DS(on) OnResistance (Ω) V GS = 4.5 V V GS = V C Capacitance (pf) C rss C iss C oss I D Drain Current (A) V DS DraintoSource Voltage (V) OnResistance vs. Drain Current and Gate Voltage Capacitance I D =.4 A V DS = 8 V.6 V GS = V,.4 A V GS GatetoSource Voltage (V) V DS = 5 V V DS = 4 V R DS(on) OnResistance (Normalized).4..8 V GS = 5 V,. A Q g Total Gate Charge (nc) Gate Charge T J Junction Temperature ( C) OnResistance vs. Junction Temperature S79Rev. B, 3Jul7 8 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

9 Si539DDL PCHANNEL TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) 4 I D =.4 A I S Source Current (A) T J = 5 C T J = 5 C R DS(on) OnResistance (Ω) 3 T J = 5 C T J = 5 C V SD SourcetoDrain Voltage (V) SourceDrain Diode Forward Voltage V GS GatetoSource Voltage (V) OnResistance vs. GatetoSource Voltage.55 I D = 5 μa V GS(th) (V).5 Power (W) T J Temperature ( C) Time (s) Threshold Voltage Single Pulse Power, JunctiontoAmbient Limited by I DM I D Drain Current (A).. Limited by R DS(on) * μs ms ms ms s DC, s T A = 5 C BVDSS Limited.. V DS DraintoSource Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Safe Operating Area, JunctiontoAmbient S79Rev. B, 3Jul7 9 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

10 Si539DDL PCHANNEL TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) I D Drain Current (A) T C Case Temperature ( C) Current Derating a Power (W).7.8 Power (W) T C Case Temperature ( C) Power Derating, JunctiontoFoot T A Ambient Temperature ( C) Power Derating, JunctiontoAmbient Note a. The power dissipation P D is based on T J max. = 5 C, using junctiontocase thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit S79Rev. B, 3Jul7 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

11 Si539DDL PCHANNEL TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) Normalized Effective Transient Thermal Impedance. Duty Cycle = Single Pulse..... Square Wave Pulse Duration (s) Notes: Normalized Thermal Transient Impedance, JunctiontoAmbient P DM t t t. Duty Cycle, D = t. Per Unit Base =R thja = 486 C/W 3. T JM T A =P DM Z (t) thja 4. Surface Mounted Normalized Effective Transient Thermal Impedance. Duty Cycle = Single Pulse..... Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, JunctiontoFoot maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see S79Rev. B, 3Jul7 Document Number: 6999 ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

12 Package Information e b e D E E B A A A c L Dim Min Nom Max Min Nom Max A A..4 A b c D E E e.65bsc.6bsc e L Nom 7 Nom A ECN: S3946 Rev. B, 9Jul DWG: 555 Document Number: 754 6Jul

13 AN84 DualChannel LITTLE FOOT SC7 6Pin MOSFET Recommended Pad Pattern and Thermal Performance INTRODUCTION This technical note discusses the pinouts, package outlines, pad patterns, evaluation board layout, and thermal performance for dualchannel LITTLE FOOT power MOSFETs in the SC7 package. These new devices are intended for smallsignal applications where a miniaturized package is needed and low levels of current (around 5 ma) need to be switched, either directly or by using a level shift configuration. Vishay provides these devices with a range of onresistance specifications in 6pin versions. The new 6pin SC7 package enables improved onresistance values and enhanced thermal performance. PINOUT Figure shows the pinout description and Pin identification for the dualchannel SC7 device in the 6pin configuration. SOT363 SC7 (6LEADS) applications for which this package is intended. For the 6pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of % when using a inch square with full copper on both sides of the printed circuit board (PCB). EVALUATION BOARDS FOR THE DUAL SC76 The 6pin SC7 evaluation board (EVB) measures.6 inches by.5 inches. The copper pad traces are the same as described in the previous section, Basic Pad Patterns. The board allows interrogation from the outer pins to 6pin DIP connections permitting test sockets to be used in evaluation testing. The thermal performance of the dual SC7 has been measured on the EVB with the results shown below. The minimum recommended footprint on the evaluation board was compared with the industry standard inch square FR4 PCB with copper on both sides of the board. S G D 3 Top View FIGURE. For package dimensions see outline drawing SC7 (6Leads) ( BASIC PAD PATTERNS See Application Note 86, Recommended Minimum Pad Patterns With Outline Drawing Access for MOSFETs, ( for the 6pin SC7. This basic pad pattern is sufficient for the lowpower D G S THERMAL PERFORMANCE JunctiontoFoot Thermal Resistance (the Package Performance) Thermal performance for the dual SC7 6pin package measured as junctiontofoot thermal resistance is 3 C/W typical, 35 C/W maximum. The foot is the drain lead of the device as it connects with the body. Note that these numbers are somewhat higher than other LITTLE FOOT devices due to the limited thermal performance of the Alloy 4 leadframe compared with a standard copper leadframe. JunctiontoAmbient Thermal Resistance (dependent on PCB size) The typical Rθ JA for the dual 6pin SC7 is 4 C/W steady state. Maximum ratings are 46 C/W for the dual. All figures based on the inch square FR4 test board. The following example shows how the thermal resistance impacts power dissipation for the dual 6pin SC7 package at two different ambient temperatures. Document Number: 737 Dec3

14 AN84 SC7 (6PIN) 5 Room Ambient 5 C Elevated Ambient 6 C Dual EVB 4 P D T J(max) T A R JA P D 5o C 5 o C 4 o C W P D 3 mw P D T J(max) T A R JA P D 5o C 6 o C 4 o C W P D 5 mw NOTE: Although they are intended for lowpower applications, devices in the 6pin SC7 will handle power dissipation in excess of. W. Thermal Resistance (C/W) 3 Square FR4 PCB Testing Time (Secs) To aid comparison further, Figure illustrates the dualchannel SC7 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state. The measured steady state values of Rθ JA for the dual 6pin SC7 are as follows: LITTLE FOOT SC7 (6PIN) ) Minimum recommended pad pattern (see Figure ) on the EVB of.5 inches x.6 inches. ) Industry standard square PCB with maximum copper both sides. 58 C/W 43 C/W FIGURE. Comparison of Dual SC76 on EVB and Square FR4 PCB. The results show that if the board area can be increased and maximum copper traces are added, the thermal resistance reduction is limited to %. This fact confirms that the power dissipation is restricted with the package size and the Alloy 4 leadframe. ASSOCIATED DOCUMENT SingleChannel LITTLE FOOT SC7 6Pin MOSFET Copper Leadframe Version, REcommended Pad Pattern and Thermal Performance, AN85, ( Document Number: 737 Dec3

15 Application Note 86 RECOMMENDED MINIMUM PADS FOR SC7: 6Lead.67 (.7) APPLICATION NOTE.96 (.438).45 (.43).6 (.648).6 (.46).6 (.648). (.4) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index Document Number: 76 8 Revision: Jan8

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