|
|
|
- Curtis Neal
- 5 years ago
- Views:
Transcription
1 Distributed by: The content and copyrights of the attached material are the property of its owner.
2 September 2001 S7C256 5V/3.3V 32K X 8 CMOS SRM (Common I/O) Features S7C256 (5V version) (3.3V version) Industrial and commercial temperature Organization: 32,768 words 8 bits High speed - 12/15/20 ns address access time - 6, 7, 8 ns output enable access time Very low power consumption: CTIVE - 660mW (S7C256) / 12 ns - 216mW () / 12 ns Very low power consumption: STNDBY - 22 mw (S7C256) / max CMOS I/O mw () / max CMOS I/O Easy memory expansion with CE and OE inputs TTL-compatible, three-state I/O 28-pin JEDEC standard packages -300 mil PDIP -300 mil SOJ mm TSOP 1 ESD protection 2000 volts Latch-up current 200 m Logic block diagram Pin arrangement V CC 28-pin TSOP 1 ( mm) 28-pin DIP, SOJ (300 mil) Row decoder 7 8 Input buffer 256 X 128 X 8 rray (262,144) Column decoder Sense amp Control circuit I/O7 I/O0 WE OE CE OE WE V CC (22) (23) (24) (25) (26) (27) (28) (1) (2) (3) (4) (5) (6) (7) S7C256 (21) 28 (20) 27 (19) 26 (18) 25 (17) 24 (16) 23 (15) 22 (14) 21 (13) 20 (12) 19 (11) 18 (10) 17 (9) 16 (8) CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O Note: This part is compatible with both pin numbering conventions used by various manufacturers I/O S7C V CC WE OE 10 CE I/O7 I/O5 I/O4 Selection guide Unit Maximum address access time ns Maximum output enable access time ns Maximum operating current S7C m m Maximum CMOS standby current S7C m m 9/18/01; v.1.6 lliance Semiconductor P. 1 of 9 Copyright lliance Semiconductor. ll rights reserved.
3 S7C256 Functional description The S7C(3)256 is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-ccess Memory (SRM) device organized as 32,768 words 8 bits. It is designed for memory applications requiring fast data access at low voltage, including Pentium TM, PowerPC TM, and portable computing. lliance s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins. The device enters standby mode when CE is high. CMOS standby mode consumes 3.6 mw. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Equal address access and cycle times (t, t RC, t WC ) of 12/15/20 ns with output enable access times (t OE ) of 6, 7, 8 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations. write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. ll chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3±0.3V supply. The S7C(3)256 is packaged in high volume industry standard packages. bsolute maximum ratings Parameter Device Symbol Min Max Unit Voltage on V CC relative to S7C256 V t V V t V Voltage on any pin relative to V t2 0.5 V CC V Power dissipation P D 1.0 W Storage temperature (plastic) T stg o C mbient temperature with V CC applied T bias o C DC current into outputs (low) I OUT 20 m Stresses greater than those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE WE OE Data Mode H X X High Z Standby (I SB, I SB1 ) L H H High Z Output disable (I CC ) L H L D OUT Read (I CC ) L L X D IN Write (I CC ) Key: X = Don t care, L = Low, H = High 9/18/01; v.1.6 lliance Semiconductor P. 2 of 9
4 S7C256 Recommended operating conditions Parameter Device Symbol Min Typical Max Unit Supply voltage Input voltage mbient operating temperature * VIL min = 2.0V for pulse width less than t RC /2. DC operating characteristics (over the operating range) Parameter Sym Test conditions Device Input leakage current Output leakage current Operating power supply current Standby power supply current I LI I LO I CC I SB I SB1 S7C256 V CC V V CC V S7C256 V IH 2.2 V CC +0.5 V V IH 2.0 V CC +0.5 V V * IL -0.5 * 0.8 V commercial T 0 70 o C industrial T o C Min Max Min Max Min Max V CC = Max, V in = to V CC Both µ V CC = Max, V OUT = to V CC Both µ V CC = Max, CE V IL f = f Max, I OUT = 0m V CC = Max, CE V IL f = f Max, I OUT = 0m V CC = Max, CE > V CC 0.2V V IN < + 0.2V or V IN > V CC 0.2V, f = 0 S7C S7C S7C Output voltage V OL I OL = 8 m, V CC = Min Both V V OH I OH = 4 m, V CC = Min Both V Unit m m m Capacitance (f = 1MHz, T a = room temperature, V CC = NOMINL) Parameter Symbol Signals Test conditions Max Unit Input capacitance C IN, CE, WE, OE V in = 0V 5 pf I/O capacitance C I/O I/O V in = V out = 0V 7 pf 9/18/01; v.1.6 lliance Semiconductor P. 3 of 9
5 S7C256 Read cycle (over the operating range) Parameter Symbol Min Max Min Max Min Max Unit Notes Read cycle time t RC ns ddress access time t ns 3 Chip enable (CE) access time t CE ns 3 Output enable (OE) access time t OE ns Output hold from address change t OH ns 5 CE LOW to output in low Z t CLZ ns 4, 5 CE HIGH to output in high Z t CHZ ns 4, 5 OE LOW to output in low Z t OLZ ns 4, 5 OE HIGH to output in high Z t OHZ ns 4, 5 Power up time t PU ns 4, 5 Power down time t PD ns 4, 5 Key to switching waveforms Read waveform 1 (address controlled) ddress D Data valid Read waveform 2 (CE controlled) D Data valid Supply current I 50% 50% I 9/18/01; v.1.6 lliance Semiconductor P. 4 of 9
6 S7C256 Write cycle (over the operating range) Parameter Symbol Write waveform 1 (WE controlled) Min Max Min Max Min Max Unit Notes Write cycle time t WC ns Chip enable to write end t CW ns ddress setup to write end t W ns ddress setup time t S ns Write pulse width t WP ns Write recovery time t WR ns ddress hold from end of write t H ns Data valid to write end t DW ns Data hold time t DH ns 4, 5 Write enable to output in high Z t WZ ns 4, 5 Output active from write end t OW ns 4, 5 ddress D Data valid D Write waveform 2 (CE controlled) ddress D D Data valid 9/18/01; v.1.6 lliance Semiconductor P. 5 of 9
7 S7C256 C test conditions - Output load: see Figure B or Figure C. - Input pulse level: to 3.0V. See Figure. - Input rise and fall times: 2 ns. See Figure. - Input and output timing reference levels: 1.5V. +5V Thevenin equivalent D 168Ω +1.72V (5V and 3.3V) +3.3V +3.0V 90% 90% 10% 2 ns 10% Figure : Input pulse 480Ω D 255Ω C(14) Figure B: Output lo 320Ω D 350Ω C(14) Figure C: Output load Notes 1 During V CC power-up, a pull-up resistor to V CC on CE is required to meet I SB specification. 2 This parameter is sampled, but not 100% tested. 3 For test conditions, see C Test Conditions, Figures, B, C. 4 These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured ±500mV from steady-state voltage. 5 This parameter is guaranteed, but not tested. 6 WE is High for read cycle. 7 CE and OE are Low for read cycle. 8 ddress valid prior to or coincident with CE transition Low. 9 ll read cycle timings are referenced from the last valid address to the first transitioning address. 10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle. 11 ll write cycle timings are referenced from the last valid address to the first transitioning address. 12 CE1 and CE2 have identical timing. 13 C=30pF, except on High Z and Low Z parameters, where C=5pF. 9/18/01; v.1.6 lliance Semiconductor P. 6 of 9
8 S7C256 Typical DC and C characteristics Normalized supply current I CC, I SB vs. supply voltage V CC Normalized supply current I CC, I SB vs. ambient temperature T a Normalized supply current ISB1 vs. ambient temperature T a Normalized I CC, I SB MIN I CC I SB NOMINL Supply voltage (V) MX Normalized I CC, I SB I CC I SB mbient temperature ( C) Normalized I SB1 (log scale) V CC = V CC (NOMINL) mbient temperature ( C) 1.5 Normalized access time t vs. supply voltage V CC 1.5 Normalized access time t vs. ambient temperature T a 1.4 Normalized supply current I CC vs. cycle frequency 1/t RC, 1/t WC Normalized access time T a = 25 C Normalized access time V CC = V CC (NOMINL) Normalized I CC V CC = V CC (NOMINL) T a = 25 C 0.8 MIN NOMINL Supply voltage (V) MX mbient temperature ( C) Cycle frequency (MHz) 140 Output source current I OH vs. output voltage V OH 140 Output sink current I OL vs. output voltage V OL 35 Typical access time change t vs. output capacitive loading Output source current (m) V CC = V CC (NOMINL)PL T a = 25 C Output sink current (m) V CC = V CC (NOMINL) T a = 25 C Change in t (ns) V CC = V CC(NOMINL) V CC 0 V CC Output voltage (V) Output voltage (V) Capacitance (pf) 9/18/01; v.1.6 lliance Semiconductor P. 7 of 9
9 S7C256 Package diagrams Pin 1 D E1 E L S e B b 1 Seating Plane α e c 28-pin PDIP Min Max in mils B b c D E E e BSC e L a 0 15 S Seating Plane 28-pin SOJ Min Max in mils B TYP b TYP c TYP b e c L 2 1 D E E E e BSC E D Hd pin 1(22) 28-pin pin 8(21) pin 1(7) pin 5(8) Note: This part is compatible with both pin numbering conventions used by various manufacturers. α 28-pin mm Min Max b c D e 0.55 nominal E 8.0 nominal Hd L α 0 5 9/18/01; v.1.6 lliance Semiconductor P. 8 of 9
10 S7C256 Ordering information Package / ccess time Volt/Temp 12 ns 15 ns 20 ns Plastic DIP, 300 mil Plastic SOJ, 300 mil TSOP 8x13.4mm Part numbering system 5V commercial S7C256-12PC S7C256-15PC S7C256-20PC 3.3V commercial -12PC -15PC -20PC 5V commercial S7C256-12JC S7C256-15JC S7C256-20JC 3.3V commercial -12JC -15JC -20JC 5V industrial S7C256-12JI S7C256-15JI S7C256-20JI 3.3V industrial -12JI -15JI -20JI 5V commercial S7C256-12TC S7C256-15TC S7C256-20TC 3.3V commercial -12TC -15TC -20TC 5V industrial S7C256-12TI S7C256-15TI S7C256-20TI 3.3V industrial -12TI -15TI -20TI S7C XX X C or I SRM prefix Voltage: 3 = 3.3V supply 5 = 5V supply Device number ccess time Packages: P = PDIP 300 mil J = SOJ 300 mil T = TSOP 8x13.4mm Temperature range: C = 0 o C to 70 0 C I = -40C to 85C 9/18/01; v.1.6 lliance Semiconductor P. 9 of 9
April 2004 AS7C3256A
pril 2004 S7C3256 3.3V 32K X 8 CMOS SRM (Common I/O) Features Pin compatible with S7C3256 Industrial and commercial temperature options Organization: 32,768 words 8 bits High speed - 10/12/15/20 ns address
3.3 V 256 K 16 CMOS SRAM
August 2004 AS7C34098A 3.3 V 256 K 16 CMOS SRAM Features Pin compatible with AS7C34098 Industrial and commercial temperature Organization: 262,144 words 16 bits Center power and ground pins High speed
5.0 V 256 K 16 CMOS SRAM
February 2006 5.0 V 256 K 16 CMOS SRAM Features Pin compatible with AS7C4098 Industrial and commercial temperature Organization: 262,144 words 16 bits Center power and ground pins High speed - 10/12/15/20
5 V 64K X 16 CMOS SRAM
September 2006 A 5 V 64K X 16 CMOS SRAM AS7C1026C Features Industrial (-40 o to 85 o C) temperature Organization: 65,536 words 16 bits Center power and ground pins for low noise High speed - 15 ns address
3.3 V 64K X 16 CMOS SRAM
September 2006 Advance Information AS7C31026C 3.3 V 64K X 16 CMOS SRAM Features Industrial (-40 o to 85 o C) temperature Organization: 65,536 words 16 bits Center power and ground pins for low noise High
P4C164 ULTRA HIGH SPEED 8K X 8 STATIC CMOS RAMS FEATURES DESCRIPTION. Full CMOS, 6T Cell. Common Data I/O
FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 8/10/12/15/20/25/35/70/100 ns (Commercial) 10/12/15/20/25/35/70/100 ns(industrial) 12/15/20/25/35/45/70/100 ns (Military) Low Power
HM6264A Series. Features. Ordering Information word 8-bit High Speed CMOS Static RAM
8192-word 8-bit High Speed CMOS Static RAM Features Low-power standby 0.1 mw (typ) 10 µw (typ) L-/LL-version Low power operation 15 mw/mhz (typ) Fast access time l00/120/ (max) Single +5 V supply Completely
High Speed Super Low Power SRAM
Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Feb.15, 2005 2.1 2.2 Add 48CSP-6x8mm package outline Revise 48CSP-8x10mm pkg code from W to K Mar. 08, 2005 Oct.25, 2005
5V 1M 16 CMOS DRAM (fast-page mode) DQ16 DQ15 DQ14 DQ13 RAS DQ12 DQ11 DQ10 DQ9 OE WE UCAS LCAS LCAS UCAS OE A9 A8 A7 A6 A5 A4
August 2001 AS4C1M16F5 5V 1M 16 CMOS DRAM (fast-page mode) Features Organization: 1,048,576 words 16 bits High speed - 45/50/60 ns access time - 20/20/25 ns fast page cycle time - 10/12/15 ns CAS access
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM MAY 1999 FEATURES High-speed access time: 10, 12, 15, 20, 25 ns Low active power: 400 mw (typical) Low standby power 250 µw (typical) CMOS standby 55 mw (typical) TTL
DS K x 8 Static RAM FEATURES PIN ASSIGNMENT PIN DESCRIPTION
8K x 8 Static RAM FEATURES Low power CMOS design Standby current 50 na max at t A = 25 C V CC = 3.0V 100 na max at t A = 25 C V CC = 5.5V 1 µa max at t A = 60 C V CC = 5.5V Full operation for V CC = 4.5V
256K X 16 BIT LOW POWER CMOS SRAM
Revision History 256K x16 bit Low Power CMOS Static RAM Revision No History Date Remark 1.0 Initial Issue January 2011 Preliminary 2.0 updated DC operating character table May 2016 Alliance Memory Inc.
SRAM AS5LC512K8. 512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT. PIN ASSIGNMENT (Top View)
512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT AVAILABLE AS MILITARY SPECIFICATIONS MIL-STD-883 for Ceramic Extended Temperature Plastic (COTS) FEATURES Ultra High Speed Asynchronous Operation
I/O 8 I/O 15 A13 A 14 BHE WE CE OE BLE
256K x 16 Static RAM Features High speed t AA = 12 ns Low active power 1540 mw (max.) Low CMOS standby power (L version) 2.75 mw (max.) 2.0V Data Retention (400 µw at 2.0V retention) Automatic power-down
DS1225Y. 64K Nonvolatile SRAM FEATURES PIN ASSIGNMENT
DS1225Y 64K Nonvolatile SRAM FEATURES years minimum data retention in the absence of external power PIN ASSIGNMENT NC 1 28 VCC Data is automatically protected during power loss Directly replaces 8K x 8
LH5P8128. CMOS 1M (128K 8) Pseudo-Static RAM PIN CONNECTIONS
LH5P8128 FEATURES 131,072 8 bit organization Access times (MAX.): 60/80/100 ns Cycle times (MIN.): 100/130/160 ns Single +5 V power supply Power consumption: Operating: 572/385/275 mw (MAX.) Standby (CMOS
256K x 16 Static RAM CY7C1041BN. Features. Functional Description
256K x 16 Static RAM Features Temperature Ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C High speed t AA = 15 ns Low active power 1540 mw (max.) Low CMOS standby power
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP
HN58C256 Series word 8-bit Electrically Erasable and Programmable CMOS ROM
32768-word 8-bit Electrically Erasable and Programmable CMOS ROM ADE-203-092G (Z) Rev. 7.0 Nov. 29, 1994 Description The Hitachi HN58C256 is a electrically erasable and programmable ROM organized as 32768-word
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
2-Mbit (128K x 16)Static RAM
2-Mbit (128K x 16)Static RAM Features Functional Description Pin-and function-compatible with CY7C1011CV33 High speed t AA = 10 ns Low active power I CC = 90 ma @ 10 ns (Industrial) Low CMOS standby power
SRAM AS5C512K8. 512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS FEATURES
512K x 8 SRAM HIGH SPEED SRAM with REVOLUTIONARY PINOUT AVAILABLE AS MILITARY SPECIFICATIONS SMD 5962-95600 SMD 5962-95613 MIL-STD-883 FEATURES Ultra High Speed Asynchronous Operation Fully Static, No
SRM2264L10/12 CMOS 64K-BIT STATIC RAM. Low Supply Current Access Time 100ns/120ns 8,192 Words 8 Bits, Asynchronous DESCRIPTION
DESCRIPTION SRM2264L10/12 CMOS 64K-BIT STATIC RAM Low Supply Current Access Time 100ns/120ns 8,192 Words 8 Bits, Asynchronous The SRM2264L10/12 is an 8,192-word 8-bit asynchronous, static, random access
512K x 32 Static RAM CY7C1062AV33. Features. Functional Description. Logic Block Diagram. Selection Guide
512K x 32 Static RAM Features High speed t AA = 8 ns Low active power 1080 mw (max.) Operating voltages of 3.3 ± 0.3V 2.0V data retention Automatic power-down when deselected TTL-compatible inputs and
HN58C66 Series word 8-bit CMOS Electrically Erasable and Programmable CMOS ROM. ADE F (Z) Rev. 6.0 Apr. 12, Description.
8192-word 8-bit CMOS Electrically Erasable and Programmable CMOS ROM ADE-203-375F (Z) Rev. 6.0 Apr. 12, 1995 Description The Hitachi HN58C66 is a electrically erasable and programmable ROM organized as
16-Mbit (1M x 16) Static RAM
16-Mbit (1M x 16) Static RAM Features Very high speed: 55 ns Wide voltage range: 1.65V 1.95V Ultra low active power Typical active current: 1.5 ma @ f = 1 MHz Typical active current: 15 ma @ f = f max
IS61C K x 16 HIGH-SPEED CMOS STATIC RAM
ISC K x HIGH-SPEED CMOS STATIC RAM FEATURES High-speed access time: 0,,, and 0 ns CMOS low power operation 0 mw (typical) operating 0 µw (typical) standby TTL compatible interface levels Single V ± 0%
LH5P832. CMOS 256K (32K 8) Pseudo-Static RAM
LH5P832 CMOS 256K (32K 8) Pseudo-Static RAM FEATURES 32,768 8 bit organization Access time: 100/120 ns (MAX.) Cycle time: 160/190 ns (MIN.) Power consumption: Operating: 357.5/303 mw Standby: 16.5 mw TTL
1-Mbit (128K x 8) Static RAM
1-Mbit (128K x 8) Static RAM Features Very high speed: 45 ns Temperature ranges Industrial: 40 C to +85 C Automotive-A: 40 C to +85 C Automotive-E: 40 C to +125 C Voltage range: 4.5V 5.5V Pin compatible
IS61LV K x 16 LOW VOLTAGE CMOS STATIC RAM
ISLV K x LOW VOLTAGE CMOS STATIC RAM FEATURES High-speed access time: 0,,, and 0 ns CMOS low power operation 0 mw (typical) operating 0 µw (typical) standby TTL compatible interface levels Single.V ± 0%
HN58C65 Series word 8-bit Electrically Erasable and Programmable CMOS ROM
8192-word 8-bit Electrically Erasable and Programmable CMOS ROM ADE-203-374A (Z) Rev. 1.0 Apr. 12, 1995 Description The Hitachi HN58C65 is a electrically erasable and programmable ROM organized as 8192-word
DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
512K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY SEPTEMBER 2005 FEATURES High-speed access time: 8, 10, and 12 ns CMOS low power operation Low stand-by power: Less than 5 ma (typ.) CMOS
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS The IN74AC138 is identical in pinout to the LS/ALS138, HC/HCT138. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS The IN74ACT138 is identical in pinout to the LS/ALS138, HC/HCT138. The IN74ACT138 may be used as a level converter for interfacing TTL or NMOS
INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28
INTEGRATED CIRCUITS -to-8 line decoder/demultiplexer; inverting 998 Apr 8 FEATURES Wide supply voltage range of. to. V In accordance with JEDEC standard no. 8-A Inputs accept voltages up to. V CMOS lower
NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register
NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package
74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting
3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible
PYA28C16 2K X 8 EEPROM FEATURES PIN CONFIGURATIONS DESCRIPTION FUNCTIONAL BLOCK DIAGRAM. Access Times of 150, 200, 250 and 350ns
PYA28C16 2K X 8 EEPROM FEATURES Access Times of 150, 200, 250 and 350ns Single 5V±10% Power Supply Fast Byte Write (200µs or 1 ms) Low Power CMOS: - 60 ma Active Current - 150 µa Standby Current Endurance:
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer General Description The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines
74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting. Product data sheet
3-to-8 line decoder, demultiplexer with address latches; inverting Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky
HN27C1024HG/HCC Series
65536-word 16-bit CMOS UV Erasable and Programmable ROM Description The Hitachi HN27C1024H series is a 1-Mbit (64-kword 16-bit) ultraviolet erasable and electrically programmable ROM. Fabricated on new
16-Mbit (1M x 16) Pseudo Static RAM
16-Mbit (1M x 16) Pseudo Static RAM Features Advanced low-power architecture High speed: 55 ns, 70 ns Wide voltage range: 2.7V to 3.3V Typical active current: 3 ma @ f = 1 MHz Typical active current: 13
UNISONIC TECHNOLOGIES CO., LTD L16B45 Preliminary CMOS IC
UNISONIC TECHNOLOGIES CO., LTD L16B45 Preliminary CMOS IC 16-BIT CONSTANT CURRENT LED SINK DRIVER DESCRIPTION The UTC L16B45 is designed for LED displays. UTC L16B45 contains a serial buffer and data latches
The 74HC21 provide the 4-input AND function.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
32K x 8 EEPROM - 5 Volt, Byte Alterable
32K x 8 EEPROM - 5 Volt, Byte Alterable Description The is a high performance CMOS 32K x 8 E 2 PROM. It is fabricated with a textured poly floating gate technology, providing a highly reliable 5 Volt only
74HC238; 74HCT to-8 line decoder/demultiplexer
Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders
8-Mbit (512K x 16) Pseudo Static RAM
8-Mbit (512K x 16) Pseudo Static RAM Features Advanced low-power architecture High speed: 55 ns, 70 ns Wide voltage range: 2.7V to 3.3V Typical active current: 2 ma @ f = 1 MHz Typical active current:
4-Mbit (256K x 16) Static RAM
4-Mbit (256K x 16) Static RAM Features Temperature Ranges Industrial: 40 C to +85 C Automotive-A: 40 C to +85 C Automotive-E: 40 C to +125 C Very high speed: 45 ns Wide voltage range: 2.20V 3.60V Pin-compatible
Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
TECHNICAL DATA IN74ACT74 Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT74 is identical in pinout to the LS/ALS74, HC/HCT74. The IN74ACT74 may be used as a level converter
BCD-TO-DECIMAL DECODER HIGH-VOLTAGE SILICON-GATE CMOS IW4028B TECHNICAL DATA
TECHNICAL DATA BCD-TO-DECIMAL DECODER HIGH-OLTAGE SILICON-GATE CMOS IW4028B The IW4028B types are BCD-to-decimal or binary-tooctal decoders consisting of buffering on all 4 inputs, decoding-logic gates,
The 74LVC1G11 provides a single 3-input AND gate.
Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input
MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity
64K x 18 Synchronous Burst RAM Pipelined Output
298A Features Fast access times: 5, 6, 7, and 8 ns Fast clock speed: 100, 83, 66, and 50 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 5 and 6 ns Optimal for performance (two cycle
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS
HN27C4096G/CC Series. Ordering Information. Features word 16-bit CMOS UV Erasable and Programmable ROM
262144-word 16-bit CMOS UV Erasable and Programmable ROM The Hitachi HN27C4096G/CC is a 4-Mbit ultraviolet erasable and electrically programmable ROM, featuring high speed and low power dissipation. Fabricated
74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:
Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
2M x 32 Bit 5V FPM SIMM. Fast Page Mode (FPM) DRAM SIMM S51T04JD Pin 2Mx32 FPM SIMM Unbuffered, 1k Refresh, 5V. General Description.
Fast Page Mode (FPM) DRAM SIMM 322006-S51T04JD Pin 2Mx32 Unbuffered, 1k Refresh, 5V General Description The module is a 2Mx32 bit, 4 chip, 5V, 72 Pin SIMM module consisting of (4) 1Mx16 (SOJ) DRAM. The
MM74HC573 3-STATE Octal D-Type Latch
MM74HC573 3-STATE Octal D-Type Latch General Description The MM74HC573 high speed octal D-type latches utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low
74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.
16-bit dual supply translating transciever; 3-state Rev. 02 1 June 2004 Product data sheet 1. General description 2. Features The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 1999 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
NTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder
NTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder Description: The NTE4514B (output active high option) and NTE4515B (output active low option) are two output options of a 4
MM74HC373 3-STATE Octal D-Type Latch
3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
MM74C912 6-Digit BCD Display Controller/Driver
6-Digit BCD Display Controller/Driver General Description The display controllers are interface elements, with memory, that drive a 6-digit, 8-segment LED display. The display controllers receive data
MM74HC373 3-STATE Octal D-Type Latch
MM74HC373 3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power
Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance
INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook
INTEGRATED CIRCUITS Octal D-type flip-flop with reset; positive-edge trigger 1997 Apr 07 IC24 Data Handbook FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V
74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:
Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
MM74HC374 3-STATE Octal D-Type Flip-Flop
3-STATE Octal D-Type Flip-Flop General Description The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
74HC1G125; 74HCT1G125
Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state
Hex inverting Schmitt trigger with 5 V tolerant input
Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 2005 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
INTEGRATED CIRCUITS. 74LV259 8-bit addressable latch. Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 May 20 FEATURES Optimized for low voltage applicatio: 1.0 to 3.6 V Accepts TTL input levels between = 2.7 V and = 3.6 V Typical
8-bit binary counter with output register; 3-state
Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It
White Electronic Designs
查询 WS1M32-25HSCA 供应商 White Electronic Designs 捷多邦, 专业 PCB 打样工厂,24 小时加急 出货 1Mx32 SRAM MODULE FEATURES Access Times of 17, 20, 25ns Packaging 4 lead, 2mm CQFP, (Package 511) 66 pin PGA Type, 1 35" sq, Hermetic
Octal buffer/line driver (3-State)
FEATURES Octal bus interface Functio similar to the ABT4 Provides ideal interface and increases fan-out of MOS Microprocessors Efficient pinout to facilitate PC board layout 3-State buffer outputs sink
R1RW0416D Series. 4M High Speed SRAM (256-kword 16-bit) Description. Features. REJ03C Z Rev Mar
4M High Speed SRAM (256-kword 16-bit) REJ03C0107-0100Z Rev. 1.00 Mar.12.2004 Description The R1RW0416D is a 4-Mbit high speed static RAM organized 256-kword 16-bit. It has realized high speed access time
1-Mbit (64K x 16) Static RAM
1-Mbit (64K x 16) Static RAM Features Very high speed 55 ns Temperature Ranges Industrial: 40 C to 85 C Automotive: 40 C to 125 C Wide voltage range 2.2V - 3.6V Pin compatible with CY62126BV Ultra-low
TC74LCX244F,TC74LCX244FW,TC74LCX244FT,TC74LCX244FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LCX244F/FW/FT/FK TC74LCX244F,TC74LCX244FW,TC74LCX244FT,TC74LCX244FK Low-Voltage Octal Bus Buffer with 5-V Tolerant Inputs and Outputs The
MM74HC151 8-Channel Digital Multiplexer
8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation
74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.
Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
74HC86. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS
Quad 2 Input Exclusive OR Gate MARKING DIAGRAMS High Performance Silicon Gate CMOS The is identical in pinout to the LS86. The device inputs are compatible with standard CMOS outputs; with pullup resistors,
NL27WZ126. Dual Buffer with 3 State Outputs. The NL27WZ126 is a high performance dual noninverting buffer operating from a 1.65 V to 5.5 V supply.
Dual Buffer with 3 State Outputs The NL27WZ126 is a high performance dual noninverting buffer operating from a 1.65 to 5.5 supply. Features Extremely igh Speed: t PD 2.6 ns (typical) at = 5.0 Designed
The 74LV08 provides a quad 2-input AND function.
Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0
74HC257; 74HCT257. Quad 2-input multiplexer; 3-state
Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has four identical 2-input multiplexers with
74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
INTEGRATED CIRCUITS inputs/outputs; positive edge-trigger (3-State) 1998 Jul 29 FEATURES 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic Supply voltage range of 2.7 to 3.6 Complies with
M74HCT138TTR 3 TO 8 LINE DECODER (INVERTING)
3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: t PD = 16ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) SYMMETRICAL
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general
The 74LV32 provides a quad 2-input OR function.
Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.
NTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register
NTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register Description: The NTE4035B is a 4 bit shift register in a 16 Lead DIP type package constructed with MOS P Channel an N Channel
INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels
MM74HC154 4-to-16 Line Decoder
4-to-16 Line Decoder General Description The MM74HC154 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses high
The 74LVC1G02 provides the single 2-input NOR function.
Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
ALLIANCE SEMICONDUCTOR
High Performance 32K 8 CMOS SRM S7C26 32K 8 CMOS SRM (Common I/O) FETURES Organization: 32,768 words 8 bits High speed 0/2///2/3 ns address access time 3/3/4//6/8 ns output enable access time Low power
INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook
INTEGRATED CIRCUITS 1998 Jun 23 IC24 Data Handbook FEATURES Optimized for Low Voltage applications: 1.0 to 5.5V Accepts TTL input levels between V CC = 2.7V and V CC = 3.6V Typical V OLP (output ground
2 Input NAND Gate L74VHC1G00
Input NAND Gate The is an advanced high speed CMOS input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining