Rules of Constant Field Scaling

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1 MOSFET Scaling Device scaling: Simplified design goals/guidelines for shrinking device dimensions to achieve density and performance gains, and power reduction in VLSI. Issues: Short-channel effect, Power density, Switching delay, Reliability. The principle of constant-field scaling lies in scaling the device voltages and the device dimensions (both horizontal and vertical) by the same factor, κ (> 1), such that the electric field remains unchanged. /19/003 1

2 Rules of Constant Field Scaling Scaling assumptions Derived scaling behavior of device parameters MOSFET Device and Circuit Parameters Device dimensions (t ox, L, W, x j ) Doping concentration (N a, N d ) Voltage (V) Electric field (E) Carrier velocity (v) Depletion layer width (W d ) Capacitance (C = εa/t) Inversion layer charge density (Q i ) Current, drift (I) Channel resistance (R ch ) Multiplicative Factor (κ > 1) 1/κ κ 1/κ 1 1 1/κ 1/κ 1 1/κ 1 Derived scaling behavior of circuit parameters Circuit delay time (τ CV/I) Power dissipation per circuit (P VI) Power-delay product per circuit (P τ) Circuit density ( 1/A) Power density (P/A) /19/003 1/κ 1/κ 1/κ 3 κ 1

3 Scaling of Depletion Width Maximum drain depletion width: W D = εsi( ψbi + Vdd ) qn a For N a κn a and V dd V dd /κ, W D W D /κ if V dd >> ψ bi. However, the source depletion width, W S si = εψ qn is indep. of V dd and only scales as W S W S / κ. a bi Furthermore, the maximum gate depletion width, W 0 dm scales even less than 1/. = 4ε sikt ln( Na / ni ) qn κ /19/003 3 a

4 Generalized Scaling Allows electric field to scale up by α (E αe) while the device dimensions scale down by κ, i.e., voltage scales by α/κ (V (α/κ)v). More flexible than constant-field scaling, but has reliability and power concerns. To keep Poisson s equation invariant under the transformation, (x,y) (x,y)/κ and ψ ψ/(κ/α) within the depletion region: ( αψ / κ ) ( αψ / κ ) qn + = a ( x/ κ) ( y/ κ) ε N a should be scaled to (ακ)n a. si /19/003 4

5 Constant Voltage Scaling Special case of α=κ in generalized scaling: The only mathematically correct scaling as far as D Poisson eq. and boundary conditions are concerned. N a κ N a, therefore, the maximum depletion width, scales down by κ. W 0 dm = 4ε sikt ln( Na / ni ) qn a Both the short-channel V t roll-off, and the threshold voltage, remain unchanged for constant-voltage scaling. However, it is physically incorrect since E κe (reliability) and P/A κ -3 P/A (power). V /19/003 5 V = V + ψ + t fb B t 4t ox = ψbi ( ψbi + Vds ) e W dm εsiqna( ψb + Vbs ) C ox πl/ W + 3t dm ox

6 Scaling in Practice CMOS VLSI technology generations Feature Size Power Supply Gate Oxide Oxide Field µm 5 V 350 Å 1.4 MV/cm 1. µm 5 V 50 Å.0 MV/cm 0.8 µm 5 V 180 Å.8 MV/cm 0.5 µm 3.3 V 10 Å.8 MV/cm 0.35 µm 3.3 V 100 Å 3.3 MV/cm 0.5 µm.5 V 70 Å 3.6 MV/cm CMOS technology has gone through mixed steps of constant voltage and constant field scaling. As a result, field and power density have gone up, but performance gains have been maintained and power per circuit has come down. Fortunately, by physics or by learning, we managed to cope with reliability requirements at higher fields. /19/003 6

7 Non-Scaling Factors Primary nonscaling factors: Built-in potential ψ bi (Si bandgap) Subthreshold current (thermal energy kt/q) Secondary nonscaling factors (due to higher E): Velocity saturation Decreased mobility at higher fields (cm /V-s) µ eff E eff Electron -0.3 E eff Hole t ox=35 Å t =70 Å ox - E eff Oxide reliability (t ox scales less, W dm more) E eff 1 µm CMOS 0.1 µm CMOS E eff (MV/cm) /19/003 7

8 Other Non-Scaling Factors Source and drain series resistance Doping level limited by solid solubility and is not scalable. Doping gradient or junction abruptness limited by annealing process. Polysilicon gate depletion Inversion layer depth/thickness Various process tolerances Gate length. Gate oxide thickness. Dopant number fluctuations. /19/003 8

9 MOSFET Threshold Voltage MOSFET current in linear and log scales: Subthreshold: V = V + ψ + V = V + ψ + t fb B ox fb B Source-Drain Current (A/µm) 1E-3 1E-4 1E-5 1E-6 1E-7 Log scale Slope ~q/kt /19/003 9 V t Q C 1E Gate Voltage (V) I C W L m kt ds = eff ox e µ ( 1) 1 q d ox Linear scale ( e ) qv ( V)/ mkt qv / kt g t ds Source-Drain Current (ma/µm)

10 CMOS Circuit Delay Node voltage (V) V 1 V V 3 V C L C L C L C L V 1 V V 3 V 4 τ n τ τ p Normalized CMOS Delay ~ V t /V dd Time (ps) V t /V dd Delay ~ CV/I Desirable to keep V t /V dd < 0.3. /19/003 10

11 Choice of Gate Work Function V = V + ψ + V = V + ψ + t fb B ox fb B Q C d ox ψ B ~ 1 V, need V fb ~ -1 V to obtain low V t ; i.e., n + poly gate on nmosfet and vice versa. V g = 0 V g = V =φ fb ms φ ms = E = 0.56 g q kt q ψ B ln N n i a E f n+ poly ψ B E c E i E v p-type silicon E f E f n+ poly qφ ms p-type silicon E c E i E v E f oxide oxide /19/003 11

12 Threshold Voltage Adjustment In a uniformly doped MOSFET, the maximum gate depletion width (long-channel), V 4εsiqNaψ B tox = V + ψ + = V fb + ( 1+ 6 ) ψ B C W t fb B W 0 4 dm = and the threshold voltage, ox εψ si B qn are coupled through the parameter N a, and therefore cannot be varied independently (for given V fb, t ox ). a dm To adjust threshold voltage, it is necessary to employ nonuniform channel doping. /19/003 1

13 Nonuniform Channel Doping d ψ de ρ( x) 1-D Poisson s eq.: = = dx dx ε si For a nonuniform p-type doping profile N(x), the electric field is obtained by integrating Poisson s equation once (neglecting mobile carriers): q W d E( x ) = N( x) dx where W ε x d is the depletion layer width. si q Wd Wd Integrating again, ψ s = N x dxdx ε ( ) 0 x si q Wd Integration by parts, ψ s = xn x dx ε ( ) 0 Note that the maximum depletion layer width W dm0 is determined by the condition ψ s = ψ B when W d = W dm0. The threshold voltage of a nonuniformly doped MOSFET is then determined by both the integral (depletion charge density) and the first moment of N(x) within (0, W dm0 ). /19/ si

14 High-Low Doping Profile N(x) Doping concentration N s N a x s W d 0 x Depth The maximum depletion width at threshold is: W 0 dm ε si qn ( N) x = ψ B qna ε si The body-effect factor takes the same form as before: ε si / Wdm Cdm 3t m = 1+ = 1+ = 1+ C C W ox 0 ox s a s ox 0 dm The threshold voltage is, again, V fb +ψ Β +V ox (=Q d /C ox ), i.e., V 1 = V + ψ + ε siqn a ψb C t fb B ox q( Ns Na) x s q( N N ) x + ε C si s a s ox /19/003 14

15 Implanted Gaussian Profile Let (N s N a )x s = D I and x s / = x c, Then and /19/ V qnawdm qd = V + ψ + + C C t fb B For shallow surface implants, x c = 0, there is no change in the depletion width. The V t shift is simply given by qd I /C ox like a sheet of charge at the silicon-oxide interface. W ε si qdix = B qn ψ a ε si 0 dm ox 0 c ox I

16 Low-High Doping Profile Channel Doping Take N s = 0, then N s N a W 4εψ si B = + x qn 0 dm s a x s 0 0 x W dm V qn a 4ε siψb = V + ψ + + xs C qn t fb B ox a qn x C a ox s In contrary to high-low doping, low-high (retrograde) doping results in a lower V t than uniform doping for a given W dm. /19/003 16

17 Extreme Retrograde Profile For x s >> (4ε si ψ B /qn a ) 1/, E f i.e., V V ε si / xs = V + ψ + ψ B C t fb B t ox t ox = Vfb ψ B Wdm n + Poly i- Layer p + Region x = W x j Q M Q i s dm Q d p- Substrate The depletion depth is the same as the undoped layer thickness. All the depletion charge is located at the far edge of the depletion region. Magnitude of the depletion charge is one half of the uniformly doped value. /19/003 17

18 Channel Profile Evolution > 1 µm CMOS: HIGH-LOW Doping Depth 1E16 cm µm CMOS: UNIFORM 0. µm CMOS: RETROGRADE Doping Doping Depth Depth 5E16 cm -3 3E17 cm µm CMOS: HALO 1E18 cm µm CMOS: SUPER-HALO 5E18 cm -3 /19/003 18

19 Channel Profile Trends For uniform channel doping, V 4εsiqNaψ B tox = V + ψ + = V fb + ( 1+ 6 ) ψ B C W t fb B ox V t is increasing slightly toward shorter channel lengths and higher N a. -D quantum effect further raises V t as the surface field increases and the electrons experience more confinement. dm On the other hand, device design calls for lower V dd and V t as the CMOS dimensions are scaled down. 1-D vertically nonuniform doping only addresses V t of long channel devices. Laterally nonuniform doping helps control V t of short channel devices. /19/003 19

20 Laterally Nonuniform Doping (Halo) Gate Source Hi Lo Hi Drain Depletion boundary Halo implants are made after gate patterning, therefore self-aligned to the gate like source-drain. Halo doped regions are farther apart for longer gates, and closer together for shorter gates. As a result, the effective doping becomes higher toward shorter devices, thus counteracting short channel effects. /19/003 0

21 CMOS Inverter V dd V dd V dd In I P I Out V dd C + C In Out p + p + n-well n + p-substrate I N n + Since only one of the transistors is on in the steady state, there is no static current or static power dissipation in a CMOS inverter. /19/003 1

22 CMOS Inverter Transfer Curve V out V in0 I P I N V in4 V dd A C V in1 V in3 V in V in V in3 B 0 D C V in1 V dd A V out 0 D B V dd V in Qualitatively, the sharpness of the high-to-low transition of the V out -V in curve is a measure of how well the circuit performs digital operations. /19/003

23 Switching Waveform for a Step Input V out V in (a) Pull down V dd V dd / Slope = I / C Nsat (b) Pull up V dd V dd / Slope = I / C Psat V in τ n t V out τ p t For nmosfet pull down transition, ( C C ) dv C dv out out + + = = IN( Vin = Vdd) dt dt The pull down delay is CVdd CVdd τ n = = I WI Nsat n nsat Similarly, the pmosfet pull up delay is CVdd CVdd τ p = = I WI Psat p psat For symmetric transfer curve and best noise margin, the width ratio should be W p /W n = I nsat /I psat. /19/003 3

24 Active Power Dissipation Consider a capacitor C between the output node and the ground. Initially, the output node is at the ground potential and there is no charge on C. During a pull up transition, current flows from the power supply through the turned-on pmosfet and raises the output node to V dd. The capacitor is now charged to Q = CV dd. The energy flow out of the power supply is QV dd = CV dd, in which half or CV dd / is energy stored in C; the other half is dissipated irreversibly as Joule heat. Now the node is pulled down and the capacitor discharged by current through the turned-on nmosfet to ground. The stored CV dd / energy is now dissipated in the circuit. A total energy of CV dd is dissipated irreversibly in an up-down switching cycle. If the clock frequency is f, and on the average a total capacitance C undergoes an up-down cycle in a clock period T, then the CMOS power dissipation is P CV dd = = CVdd f T (Note that the cross-over current is neglected.) /19/003 4

25 CMOS NAND and NOR Gates NAND: Output is high unless all inputs are high. V dd NOR: Output is low unless all inputs are low. V dd V out V in1 V in V in V in1 V out Like the inverter, there is no static power dissipation. /19/003 5

26 MOSFET Layout Polysilicon gate Contact hole Active region W b c a L d d = a + b + c are layout groundrules dictated by lithography capability. Field oxide n+ or p+ Silicon substrate Field oxide L is limited by either lithography or device design. /19/003 6

27 CMOS Inverter Layout Output n+ N-well/p+ p+ (a) Gr. V dd Input (b) Gr. Gr. Output n+ N-well/p+ p+ Input Active region V dd V dd Folded (or interdigitated) layout in (b) reduces the junction capacitance contribution by a factor of. Polysilicon gate Contact hole Metal /19/003 7

28 Two-way NAND Layout Output V dd N-well/p+ p+ n+ V dd P1 P V x V out V in1 N1 Gr. V dd V in N V x Input-1 Input- Active region Polysilicon gate Contact hole Metal /19/003 8

29 Source-Drain Series Resistance R ac is the accumulation-layer resistance which is modulated by gate voltage and should be a part of the channel length. R sp is the spreading resistance associated with current injection from the surface channel into the bulk. Rsh = ρshs / W R co is the contact resistance associated with current flowing from Si into metal. /19/003 9

30 Self-Aligned Silicide Technology Sheet resistance: Metal (1 µm) 0.05 Ω/sq N+, p+ diffusion (0.1 µm) Ω/sq Silicide (0.03 µm) 5-10 Ω/sq R sh becomes negligible. R co between silicide and metal is negligible. Long contact regime between silicide and Si. /19/003 30

31 MOSFET Capacitances Gate C ov C g C ov Source C d Drain C J C J Intrinsic capacitance: C g = WLCox Cg = WLC 3 ox Parasitic capacitances: Depletion capacitance Overlap capacitance Junction capacitance C = ε WL / W si a j si dj ( ψ bi + V j /19/ C d s = ε Wd / W dm = Wd ε qn )

32 Overlap Capacitance l ov C of t gate Gate C of C do t ox C do x j Source C if C if Drain C Direct overlap Outer fringe Inner fringe oxwlov = Wl C = ε ε W t ox gate ε W x si Cof = ln 1+ Cif = ln 1+ t π t ox ox π t do ov ox For typical values of t gate /t ox 40 and x j /t ox 0, C of /W.3ε ox 0.08 ff/µm, C if /W 1.5ε si 0.16 ff/µm (off state) C V C C C W l ov ov( g = 0) = do + of + if εox + 7 t ox For reliability, l ov (-3)t ox, C ov /W 10ε ox 0.3 ff/µm /19/003 3 j ox

33 Gate Resistance Gate V(x) I(x) Rdx Cdx L x=0 x=w The resistance per unit length is R = ρ / g L where ρ g is the silicide sheet resistivity (Ω/ ). The capacitance per unit length is approximately C = CoxL= ε V t Diffusion eq.: = RC V x t ρ The effective RC delay is RCW gcoxw /4 or τ g = 4 For ρ g = 10 Ω/, t ox = 50 Å; τ g < 1 ps if W < 7.6 µm. Multiple-finger gate layouts with interdigitated source and drain regions should be used. /19/ ox ox L

34 Interconnect Scaling L w Interconnect parameters Scaling factor (κ > 1) t ins A Ground plane Scaling assumptio ns Interconnect dimensions (t w, L w, W w, t ins, W sp ) Resistivity of conductor (ρ w ) 1/κ 1 Insulator permittivity (ε ins ) 1 Derived wire Wire capacitance per unit length (C w ) 1 L w /κ scaling behavior Wire resistance per unit length (R w ) κ t ins /κ A/κ Wire RC-delay (τ w ) 1 Wire current density (I/W w t w ) κ /19/003 34

35 Interconnect Resistance Interconnect RC delay is described by the same distributed RC-ckt & diffusion eq. as gate resistance. τ w = 1 w w w RCL where R w = ρ w /W w t w and C w πε ins ( pf/cm). Lw τw πεinsρw Wt w w For aluminum and oxide technology, Lw τ w ( s) Wt Local wire RC delay < 1 ps as long as L w /W w t w < and can be scaled down without problem. For global wires, however, L w does not scale down, e.g., L w /W w t w , and τ w 1 ns. Therefore, W w t w cannot scale down Use large wires for global wiring. /19/ w w

36 Global Interconnects Chip Interconnect delay (s) 1E-8 1E-9 1E-10 1E-11 1E-1 Wire size: 0.1 µm 0.3 µm 1.0 µm Limited by speed of EM-wave Must also scale up insulator spacing otherwise C w RC Delay ~ l /A Time of Flight ~ l /c 1E Wire length (cm) Ultimately, signal propagation is limited by the speed of electromagnetic wave, c/(ε ins /ε 0 ) 1/, (70 ps/cm for oxide), instead of by RC delay. /19/003 36

37 Propagation Delay For a chain of CMOS inverters or NAND/NOR gates, V 1 V V 3 V C L C L C L C L Node voltage (V) V 1 V V 3 V 4 τ n τ p τ CMOS propagation delay equals τ = (τ n + τ p )/, where τ n is the pulldown delay and τ p is the pull-up delay Time (ps) /19/003 37

38 Bias Point Trajectories Pull down Pull up 4 V in = I P 4 V in = I P Transistor current (ma) V in = Transistor current (ma) V in = I N.5-4 I N Output node voltage (V) Output node voltage (V) Equal time interval (10 ps) between dots. /19/003 38

39 Delay Equation Inverter delay (ps) W n =10 µm W p =5 µm τ int =R sw (C in +C out ) Fan-out = 3 Slope=R sw Load capacitance (pf) 1 Delay equation: τ = R ( C + FO C + C ) sw out in L R sw : Switching Resistance ( dτ/dc L ) C in : Input Capacitance (to next stage) C out : Output Capacitance FO: Number of Fan-Out s The delay equation not only allows the delay to be calculated for any fan-out and loading conditions, but also decouples the two important factors that govern CMOS performance: current and capacitance. /19/003 39

40 Input and Output Capacitance V dd V dd V dd In I P I Out V dd C + C In Out p + p + n-well n + p-substrate I N n + C in : For switching n/p gates of the receiving stage. C out : For switching n/p drains of the sending stage. Gate C ov C g C ov Source C d Drain C J /19/ C J

41 Switching Resistance Switching resistance R sw is a direct indicator of the current drive capability of the logic gate. If we define R swn dτ n /dc L and R swp dτ p /dc L, then R sw = (R swn + R swp )/ and we can write R k V dd swn = R n swp = k WI n n Vdd WI where I n, I p are maximum on currents at V ds = V g = V dd, and k n, k p are numerical fitting parameters. For step inputs with zero rise time, k n = k p = 0.5. For propagation delays, k n, k p ~ p p p /19/003 41

42 Delay Sensitivity to n/p Width Ratio Intrinsic delay (ps) τ p τ τ n Table 5. value Note that for equal pull-up and pull-down delays (τ n = τ p ) and therefore symmetric transfer curve and best noise margin, W p /W n =.5. Minimum CMOS delay, (τ n + τ p )/, however, occurs at W p /W n = Device width ratio, W p /W n /19/003 4

43 Buffer Stage for Heavy Loads For a given W p /W n ratio, if both widths are increased by a factor of k, then R sw R sw /k, C in kc in, C out kc out. No change in intrinsic delay, τ int = Rsw ( Cin + Cout ) But driving capability is improved. Consider a CMOS inverter driving a large capacitive load: τ = R ( C + C ) sw out L If C L >> C in, C out, the delay can be improved by inserting a buffer stage k (> 1) times wider than the original inverter. The twostage delay is Rsw CL τ b = R sw ( C out + kc in ) + ( kcout + CL ) = Rsw( Cout + kcin + ) k k which has a minimum τ b min = R sw ( C out + C in C L ) when k = (C L /C in ) 1/. Multiple-stage buffers can be used for very heavy loads (Problem ). /19/003 43

44 Delay Sensitivity to Channel Length Switching resistance ( Ω-µm ) 0,000 15,000 10,000 9,000 8,000 7,000 6,000 5,000 4,000 3, W p R swp W n R swn Channel length (µm) 0.5 Intrinsic delay (ps) Input, output capacitance (ff/µm) C out /(W n +W p ) C in /(W n +W p ) Channel length (µm) Channel length (µm) /19/003 44

45 Delay Sensitivity to Oxide Thickness 15,000 3 W p R swp Switching resistance ( Ω-µm ) 10,000 9,000 8,000 7,000 6,000 5,000 4,000 C in /(W n +W p ) C out /(W n +W p ) W n R swn 1 Input, output capacitance (ff/µm) Inverter delay (ps) C L =0.1 pf C L =0 W n =10 µm W p =5 µm Gate oxide thickness (nm) 3, Gate oxide thickness (nm) /19/003 45

46 Delay Sensitivity to V dd and V t Normalized CMOS Delay ~ V t /V dd V t /V dd Delay sensitivity to V dd and V t is mainly in the R sw factor. Note that the dependence is stronger than I on 1 V t /V dd, due to the finite input rise time. Desirable to keep V t /V dd < 0.3. /19/003 46

47 CMOS Performance and Power Power supply voltage Higher standby power ~exp( qv /mkt) t Higher active power ~CV dd f Increasing performance ~0.7 V t /V dd Threshold voltage /19/003 47

48 CMOS Power vs. Delay Trade-off Power/stage (uw) V dd =.0 V 0.1 µm CMOS 1.5 V 101-stage inverter P ~ f 3 W n= 3 µm W = 4 µm p 1.0 V 0.7 V 0.5 V P ~ f 0.4 V Delay/stage (ps) Significant power savings by trading off performance and operating at low V dd (same V t ). /19/003 48

49 Overlap Capacitance and Miller Effect Consider driving 3 capacitors with respect to different voltages: V dd C 1 V 1 i V C V C 3 V 3 i C d ( V V C d V V C d V V 1) ( ) ( 3) = dt dt dt i C dv C dv C dv C dv = dt dt dt dt If dv /dt = dv/dt, then i= ( C C C dv ) dt C appears doubled to the driving source. /19/003 49

50 Components of C in and C out Gate C ov C g C ov Source C d Drain C J C J Intrinsic gate oxide capacitance (n & p) Overlap capacitance Junction capacitance (nonfolded) Input capacitance 57% 43% --- Output capacitance 14% 35% 51% /19/003 50

51 Two Input (Two-way) NAND V dd P1 P V out Top (N1) switching: Effective gate drive is V in1 V x, threshold is V t + (m 1)V x due to body effect. V in1 V in N1 N V x Bottom (N) switching: Has more capacitance (of N1) to pull down..5 -way NAND (Top Switching) V out.5 -way NAND (Bottom Switching) V out Node voltage (V) 1.5 V x Node voltage (V) 1.5 V x 0 V in 0 V in Time (ps) Time (ps) /19/003 51

52 Two Input (Two-way) NAND V dd 00 Top switching -way NAND{ Bottom switching V in1 V in P1 N1 N V x P V out Propagation delay (ps) Inverter Fan-out=1 W n =10 µm W p =0 µm Load capacitance (pf) Delay is about 30% worse than inverter. (Fan-in > 3 rarely used.) R sw k n V dd + (FI 1) V W I n n dsat + k p V W p dd I p /19/003 5

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