Chapter 10 Instructor Notes

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Chapter 10 Instructor Notes"

Transcription

1 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 hapter 10 nstructor Notes hapter 10 introduces bipolar junction transistors. The material on transistors has been reorganized in this 4 th dition, and is now divided into two independent chapters, one on bipolar devices, and one on field-effect devices. The two chapters are functionally independent, except for the fact that Section 10.1, introducing the concept of transistors as amplifiers and switches, can be covered prior to starting hapter 11 if the instructor decides to only teach field-effect devices. Section 10.2 introduces the fundamental ideas behind the operation of bipolar transistors, and illustrates the calculation of the state and operating point of basic transistor circuits. The discussion of the properties of the JT in Section 10.2 is centered around a description of the base and collector characteristics, and purposely avoids a detailed description of the physics of the device, with the intent of providing an intuitive understanding of the transistor as an amplifier and electronic switch. xample 10.5 introduces the use of lectronics Workbench (W) as a tool for analyzing electronics circuits; the D- OM contains an introduction to the software package and a number of solved problems. Section 10.3 introduces large-signal models of the JT, and also includes the box Focus on Methodology: Using device data sheets (pp ). xample 10.7 (LD Driver) and the box Focus on Measurements: Large Signal Amplifier for Diode Thermometer (pp ) provide two application examples that include W solutions. Section 8.4 introduces the analysis of JT switches and presents TTL gates. The end-of-chapter problems are straightforward applications of the concepts illustrated in the chapter. Learning Objectives 1. Understand the basic principles of amplification and switching. Section Understand the physical operation of bipolar transistors; determine and select the operating point of a bipolar transistor circuit; understand the principle of small signal amplifiers. Section Understand the large-signal model of the bipolar transistor, and apply it to simple amplifier circuits. Section Understand the operation of bipolar transistor as a switch and analyze basic analog and digital gate circuits. Section

2 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Section 10.2: Operation of the ipolar Junction Transistor Problem 10.1 Transistor diagrams, as shown in Figure P10.1: (a) pnp, 0.6 and 4.0 (b) npn, 0.7 and 0.2 (c) npn, 0.7 and 0.3 (d) pnp, 0.6 and 5.4 For each transistor shown in Figure P10.1, determine whether the and junctions are forward or reverse biased, and determine the operating region. (a) for a pnp transistor implies that the junction is forward-biased The junction is reverse-biased. Therefore, the transistor is in the active region. (b) for a npn transistor implies that the junction is reverse-biased The junction is reverse-biased. Therefore, the transistor is in the cutoff region. (c) 0.7 for a npn transistor implies that the junction is forward-biased The junction is forward-biased. Therefore, the transistor is in the saturation region. (d) 0.6 for a pnp transistor implies that the junction is reverse-biased The junction is forward-biased. Therefore, the transistor is in the active region. Problem 10.2 Transistor type and operating characteristics: a) npn, 0.8 and 0.4 b) npn, 1.4 and 2.1 c) pnp, 0.9 and 0.4 d) npn, and 0.6 The region of operation for each transistor. a) Since 0.8, the junction is forward-biased Thus, the junction is forward-biased. Therefore, the transistor is in the saturation region. 10.2

3 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 b) The junction is forward-biased The junction is reverse-biased. Therefore, the transistor is in the active region. c) 0.9 for a pnp transistor implies that the junction is forward-biased The junction is forward-biased. Therefore, the transistor is in the saturation region. d) With - 1.2, the junction is reverse-biased The junction is reverse-biased. Therefore, the transistor is in the cutoff region. Problem 10.3 The circuit of Figure P10.3. β 100. The operating point and the state of the transistor. 0.6 and the junction is forward biased. 1 β 1.39mA µA 820 Writing KL around the right-hand side of the circuit: ( + ) 12 (1.39)(2.2) ( )(0.910) > The transistor is in the active region. 10.3

4 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem 10.4 The magnitude of a pnp transistor's emitter and base current, and the magnitudes of the voltages across the emitter-base and collector-base junctions: 6 ma, 0.1 ma and 0.65, 7.3. a). b). c) The total power dissipated in the transistor, defined as P +. a) b) ma. c) The total power dissipated in the transistor can be found to be: P mw. Problem 10.5 The circuit of Figure P10.5, assuming the JT has The emitter current and the collector-base voltage. Applying KL to the right-hand side of the circuit, Then, on the left-hand side, assuming β >> 1: ( 520) (15) ( ) ) µA Problem 10.6 The circuit of Figure P10.6, assuming the JT has 0.6 and β 150. The operating point and the region in which the transistor operates. 10.4

5 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Define 3.3kΩ, 1.2kΩ, 1 62kΩ, 2 15kΩ, 18 y applying Thevenin s theorem from base and mass, we have 1 1 β kω ma µa + (1 + β ) From the value of it is clear that the JT is in the active region. Problem 10.7 The circuit of Figure P10.7, assuming the JT has The emitter current and the collector-base voltage. Applying KL to the right-hand side of the circuit, µA Since β >> 1, 497.4µA Applying KL to the left-hand side: + DD DD Problem 10.8 The circuit of Figure P10.7, assuming the emitter resistor is changed to 22 kω and the JT has 0.6. The operating point of the transistor µ A , 881.8µA 10.5

6 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 DD Problem 10.9 The collector characteristics for a certain transistor, as shown in Figure P10.9. a) The ratio / for 10 and 100 µa, 200 µa, and 600 µa b), assuming the maximum allowable collector power dissipation is 0.5 W for 500 µa. a) For 100 µa and 10, from the characteristics, we have 17 ma. The ratio / is 170. For 200 µa and 10, from the characteristics, we have 33 ma. The ratio / is 165. For 600 µa and 10, from the characteristics, we have 86 ma. The ratio / is 143. b) For 500 µa, and if we consider an average β from a., we have P +, therefore: ma. The power dissipated by the transistor is P Problem Figure P10.10, assuming both transistors are silicon-based with β 100. a) 1, 1, 1. b) 2, 2, µA β 3.907mA a) From KL: b) Again, from KL: mA β ma β and

7 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Also, ( ) (1.07) ( ) (1.07) (20) Finally, 2 Problem ollector characteristics of the 2N3904 npn transistor, see data sheet pg The operating point of the transistor in Figure P10.11, and the value of β at this point. onstruct a load line. Writing KL, we have: Then, if 0, 50 ; and if 0, 10mA. The load line is shown superimposed on the collector characteristic below: load line The operating point is at the intersection of the load line and the 20µA line of the characteristic. Therefore, Q 5 ma and Q 20. Under these conditions, an 5 µa increase in yields an increase in of approximately 6 5 1mA. Therefore, β The same result can be obtained by checking the h F gain from the data-sheets corresponding to 5 ma. 10.7

8 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem The circuit shown in Figure P With reference to Figure 10.20, assume 0.6, 0.2 The operating point of the transistor, by computing the ratio of collector current to base current sat 0.2, therefore 9.8mA , therefore 102µA sat << β Problem For the circuit shown in Figure P10.13, a) b) c) 1 and 0.6. d) e) β f) α. a)

9 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter b) 20µA c) 800µA 5000 d) µA 780 e) β f) α. Problem For the circuit shown in Figure P10.14: 20 β MΩ 2 300kΩ 3kΩ 1kΩ 1kΩ 0.6kΩ cos[ t]m L S v 3 S. The Thèvenin equivalent of the part of the circuit containing 1, 2, and with respect to the terminals of 2. edraw the schematic using the Thèvenin equivalent. xtracting the part of the circuit specified, the Thèvenin equivalent voltage is the open circuit voltage. The equivalent resistance is obtained by suppressing the ideal independent voltage source: Note that must remain in the circuit because it supplies current to other parts of the circuit: 10.9

10 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem For the circuit shown in Figure P10.14: 15 β kΩ kΩ 200Ω 200Ω 1.5kΩ 0.9kΩ cos[ t]m L S Q and the region of operation. v 3 S. Simplify the circuit by obtaining the Thèvenin equivalent of the biasing network in the base circuit: D : Suppress : TH eq kω edraw the circuit using the Thèvenin equivalent. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region; then, the base-emitter junction is forward biased. Q 700 m [Si] Q β Q Q ( β + 1) Q Then: 10.10

11 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 KL: - Q + Q Q +[ β + 1 ] Q Q ( )( 200) Q µa Q +[ β + 1 ] Q 0 KL : - Q Q Q Q β ( β + 1) ( ) - Q Q - Q - Q Q - + Q ma ma The collector-emitter voltage is greater than its saturation value (0.3 for Silicon). Therefore the initial assumption (operation in the active region) was correct and the solution is valid. Notes: 1. f the collector-emitter voltage were less than its saturation value, the transistor would be operating in its "saturation" or "ohmic" region. n this case, the collector-emitter voltage is equal to its saturation value (0.3 for Silicon). The solution for the base current remains valid. However, the parameter β and the solution for the collector and emitter curents become invalid. n the saturation region, the base-emitter junction is still forward biased and its voltage remains the same. A solution for the collector and emitter currents is possible using the collector-emitter saturation voltage (0.3 for Silicon) in a KL. 2. n the saturation region, the base current has no control over the collector or emitter currents (since β is invalid). Therefore, amplification is impossible. Problem For the circuit shown in Figure P10.14: 15 β kΩ kΩ 4kΩ 200Ω 1.5kΩ 0.9kΩ cos[ t]m L S Q and the region of operation. v 3 S

12 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Simplify the circuit by obtaining the Thèvenin equivalent of the biasing network in the base circuit: edraw the circuit using the Thèvenin equivalent. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region. Then, the base-emitter junction is forward biased. Q Q Q Q ( β ) Q 700 m [Si] β + 1 KL : - + Q + Q + Q Q + Q + [ β + 1 ] Q 0 Q - Q + [ β + 1 ] ( )( 200) µa KL : - Q Q Q Q β ( β + 1) ( ) - Q Q - Q - Q Q - + Q ma ma The collector-emitter voltage is less (more negative) than its saturation value (+ 0.3 for Silicon). Therefore the initial assumption (operation in the active region) was incorrect and the solution is not valid. The device is operating in the saturation region with a saturation collector-emitter voltage equal to 0.3. The solutions for the collector and emitter currents are invalid. TH ALD SOLUTON: KL : - - v Q -SAT Q Q Q Q - [ Q + Q ] - v -SAT - Q + 0 Q - Q - v + -SAT mA The solution for the base current is valid. The value of beta given is not valid

13 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem For the circuit shown in Figure P10.17: 12 β kΩ 2 22kΩ 0.5kΩ L 16Ω Q at the D operating point.. Simplify the circuit by obtaining the Thèvenin equivalent of the biasing network ( 1,, 2, ) in the base circuit: D : Suppress : eq 17.35kΩ edraw the circuit using the Thèvenin equivalent. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region. Then, the base-emitter junction is forward biased. Q TH 700 m O [Si] Q [ β + 1 ] Q KL : - + Q + Q + Q Q + Q + [ β + 1 ] Q 0 Q Q - Q + ( β + 1) ( ) 6 ( β + 1 ) ( ) Q µA ma KL : Q - Q - - Q Q The collector-emitter voltage is greater than its saturation value (0.3 for Silicon). Therefore the initial assumption (operation in the active region) was correct and the solution is valid. Problem For the circuit shown in Figure P10.18: 10.13

14 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter β kΩ 3kΩ 3kΩ v cos S t. 6kΩ 0.6kΩ [ ]m L s Q and the region of operation. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region; then, the base-emitter junction is forward biased and: Q 700 m [Si] Q β Q Q ( β + 1) Q KL : KL : - Q + Q [ β + β Q Q + Q ] ( )( 3000) 6 ( 100) ma Q Q 6 ( β + 1) ( ) ma Q Q + - Q - Q - Q + Q + - Q - Q µ A The collector-emitter voltage is greater (more positive) than its saturation value (+ 0.3 for Silicon). Therefore the initial assumption (operation in the active region) was correct and the solution is valid. Notes: 1. D power may be supplied to an npn JT circuit by connecting the positive terminal of a D source to the collector circuit, or, by connecting the negative terminal of a D source to the emitter circuit, or, as was done here, both. 2. n a pnp JT circuit the polarities of the sources must be reversed. Negative to collector and positive to emitter. Problem For the circuit shown in Figure P10.19: 12 β kΩ 1.9kΩ 2.3kΩ 10.14

15 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 10kΩ 0.5kΩ cos[ t]m L s Q and the region of operation. v 3 S. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region; then, the base-emitter junction is forward biased. The base and collector currents both flow through the collector resistor in this circuit. Q 700 m [Si] Q β Q Q [ β + 1 ] Q KL : Q + Q - 0 Q + Q β Q + Q [ β + 1 ] Q KL : - Q - Q - Q [ β + 1 ] Q [ + ] - Q - Q + 0 Q Q - Q µA 3 + [ β + 1 ] [ + 10 [ β + 1 ] Q ] [ ( ) ( ) ] 6 ( ) mA KL : - Q Q - Q Q The collector-emitter voltage is greater than its saturation value (0.3 for Silicon). Therefore the initial assumption (operation in the active region) was correct and the solution is valid. Problem For the circuit shown in Figure P10.19: µF β kΩ 3.3kΩ 3.3kΩ v cos S t. 1.7kΩ 70Ω [ ]m L s 10.15

16 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Q and the region of operation. When β is very high (say, greater than 50) the "high beta approximation" can be used, i.e.: β Using this approximation in this problem: Q 12.5µA Q Q ma Q The collector-emitter voltage is greater than the saturation value (but not by much) so the original assumption (operation in the active region) and the solution are valid. However, when a signal is introduced into the circuit, the collector-emitter voltage will vary about its Q point value. Since the Q point is close to saturation, saturation and severe distortion due to clipping is likely. Problem For the circuit shown in Figure P10.14: µ F 1 220kΩ 2 55kΩ 3kΩ 710Ω 3kΩ 0.6kΩ v 0 sin( ωt ) 0 10m. L D operating point: Q 19.9µ A s 7.61 S i i Q Transfer characteristic and β of the npn silicon transistor: v Q + vbe s e s e β 100 T T Device i-v characteristic plotted in Figure P9.21. a) The no-load large signal gain [v 0 /v i ]. b) Sketch the waveform of the output voltage as a function of time. c) How the output voltage is distorted compared with the input waveform. a) Simplify the circuit by determining the Thèvenin equivalent of the biasing network in the base circuit. D : Suppress : TH kω eq 1 2 First, determine the collector and emitter Q point:

17 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 KL : - Q - Q - Q + 0 Q Q β Q ma 6 Q [ β + 1 ] Q Now, determine the D load line (circuit characteristic). KL : i - i - v - i - v - v β β 0 f : v ma f : mA 0 v 15 i β + 1 i β 0 [ntercept 1] [ntercept 2] Plot the D load line on the same plot as the transistor i-v characteristic. Note that the collector current is a linear function of the collector-emitter voltage. Only two points (the two intercepts shown as Points 1 and 2 on the plot) are required to plot a linear function. The D load line should pass through the Q point. The A load line can now be plotted. t will pass through the Q point as does the D load line; however, its intercepts cannot be directly determined. nstead, its slope will be determined. The slope and the Q point can then be used to plot the A load line. Slope A ma mA - 6 i v For A the capacitors act as short circuits. The bypass capacitor in parallel with the emitter resistor shorts out any A voltage across it. The collector coupling capacitor acts as a short and connects the load resistor to the circuit. However, no-load conditions are specified, i.e., the load current is zero or the load resistor is replaced by an open circuit. With no signal, the circuit operates at its Q point. When a signal is introduced, the operating point changes along the A load line as a function of the signal voltage. Unfortunately, the device i-v characteristic is plotted as a function of input (base) current instead of voltage. ut, there is the static characteristic that relates collector current to base-emitter voltage: i s e v T s e Q T + v be [ s e Q T ] e v be T Q e v be T i i β Q β e v be T Q e v be T The base-emitter signal voltage is related to the input signal voltage. At sufficiently high frequencies (the "mid"-frequency range) the capacitors can be modeled as short circuits for A. This means that there is no A voltage across either the A coupling (D blocking) capacitor or the capacitor bypassing the emitter resistor. Using superposition to sum only A voltages around the loop: 10.17

18 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 KL :- v + v + v + v 0 v v i c be e c e be i vbe vi i Q e [ 19.9µA ] T e26 m This transfer function can now be used to give the base current as a function of the input voltage. The intersection of the base current curves with the A load line give the corresponding values of the collector current and collector-emitter voltage (points 3, Q and 4 on the plot): ωt [rad] v i [m] i [µa] i [ma] v [] v o [] 0,π,2π π/ π/ The capacitor connecting the load to the circuit is a D blocking [and A coupling] capacitor. emember that for no load conditions, the load resistor is assumed to be open. Again using superposition to sum only A voltages around the loop and modeling the capacitors as shorts: - ve + vce + vc + vo 0 ve vc 0 vo vce v - Q The no-load voltage gain can be determined using the maximum excursion in the input and output voltages: A vo v v o ( 1.54) ( ) 3 3 ( ) ( ) i When the input voltage becomes more positive, the output voltage becomes more negative and vice versa. This is called "phase inversion" and is why the gain is negative. n normal amplification this is not important. f the loading effect of the load resistance is included, the A load line will be steeper and the gain will be reduced. b) A plot is a large number of calculated points plotted and connected by a smooth curve. n a sketch, only the most significant points [maxima, minima, intercepts, etc] are calculated, plotted, and connected by a carefully drawn smooth curve. c) The output waveform is very distorted, i.e., it is not a true linearly amplified copy of the input waveform. This is most obvious when the positive and negative peaks of the two curves are compared: nput voltage +10 m -10 m Output voltage The two peaks of the input voltage are equal; however, the positive peak is amplified less than the negative peak. The nonlinear (exponential) behavior of the transistor causes the amplification to be nonlinear and the output waveform to be very distorted. This is characteristic of large signal amplifiers. ven more serious distortion could occur if the input voltage (also called the "excitation" or "drive") were increased so that saturation or cutoff occurs. This causes "clipping" and a severely distorted output. v v 10.18

19 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Section 10.3: JT Large-Signal Model Problem For the circuit shown in Figure 10.24: off LD 0, on 1.4, ange of. 5, LD 5 ma, 10 ma, P max 1kΩ, 100 mw LD sat Ω 0.01 LD From the maximum power LD max > P max LD LD LD max ma 1.4 sat 47 Ω 5, 0.7, sat 0.2, β 95, Therefore, [47, 340] Ω Problem For the circuit shown in Figure 10.26:.1, 33kΩ, 12, 0.75, 6, β 188.5, 500 Ω D 1 Q S The resistance. The current through the resistance is given by D Q The current through S is S Q S D µa ma 500 t follows that the current through the resistance is Q β + S Finally, 11.8 ma Q Ω Q 10.19

20 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem For the circuit shown in Figure 10.24: off LD 0, on 1.4, 5, LD ange of. f the JT is in saturation LD max 10 ma, P sat 5 ma, max 10 ma 340 Ω, 100 mw n order to guarantee that the JT is in saturation on on / β max kω Ω 5, 0.7, sat 0.2, β 95, Problem For the circuit shown in Figure 10.24: off LD 0, on 1.4, 5, LD max 10mA, P 5mA, max 10kΩ, 100mW 340Ω, 5, 0.7, sat 0.2, Minimum value of β that will ensure the correct operation of the LD. on ma LD min 0.01 β min Problem For the circuit shown in Figure 10.24: off LD 0, on 1.4, 3.3, LD max 10mA, P 5mA, max 100mW 10kΩ, 340Ω, 5, 0.7, sat 0.2, 10.20

21 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Minimum value of β that will ensure the correct operation of the LD. on ma LD min 0.01 β min Problem For the circuit shown in Figure 10.24: off 0, on 5, max 1mA, 1kΩ, 12 Ω, 13, 1A Minimum value of β that will ensure the correct operation of the fuel injector. 0.7, sat 1, sat A 12 1 β min max Problem For the circuit shown in Figure 10.24: off 0, on 5, max 1A 1mA, β 2000, 12 Ω, The range of that will ensure the correct operation of the fuel injector. 13, 0.7, sat 1, 10.21

22 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 f the JT is in saturation sat 1A ecause this is the minimum value allowed for the current to drive the fuel injector, it is necessary to guarantee that the JT is in saturation. n order to guarantee that the JT is in saturation on on / β max kω kΩ Problem For the circuit shown in Figure 10.24: off 0, 3.3, max 1A on 1mA, β 2000, 12 Ω, The range of that will ensure the correct operation of the fuel injector. f the JT is in saturation sat 1A 13, 0.7, ecause this is the minimum value allowed for the current to drive the fuel injector, it is necessary to guarantee that the JT is in saturation. n order to guarantee that the JT is in saturation on on / β max kω kω sat 1, 10.22

23 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Section 10.4: JT Switches and Gates Problem The circuit given in Figure P Show that the given circuit functions as an O gate if the output is taken at v 01. onstruct a state table. This table clearly describes an AND gate when the output is taken at v o1. v 1 v 2 Q 1 Q 2 Q 3 v o1 v o2 0 0 off off on off on off on off off on on off 5 0 Problem The circuit given in Figure P Show that the given circuit functions as a NO gate if the output is taken at v 02. See the state table constructed for Problem This table clearly describes a NO gate when the output is taken at v o2. Problem The circuit given in Figure P Show that the given circuit functions as an AND gate if the output is taken at v 01. onstruct a state table. This table clearly describes an AND gate when the output is taken at v o

24 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 v 1 v 2 Q 1 Q 2 Q 3 v o1 v o2 0 0 off off on off on on on off on on on off 5 0 Problem The circuit given in Figure P Show that the given circuit functions as a NAND gate if the output is taken at v 02. See the state table constructed for Problem This table clearly describes a NAND gate when the output is taken at v o2. Problem n the circuit given in Figure P10.34 the minimum value of v in for a high input is 2.0. Assume that the transistor Q 1 has a β of at least 10. The range for resistor that can guarantee that the transistor is on i c 2.4mA, therefore, i 2000 i /β 0.24 ma. (v in )min 2.0 and (v in )max 5.0, therefore, applying KL: -vin + i vin 0.6 or. Substituting for (v i in )min and (v in )max, we find the following range for : 5.833kΩ k Ω Problem For the circuit given in Figure P10.35: a) v, v out, and the state of the transistor Q 1 when v in is low. b) v, v out, and the state of the transistor Q 1 when v in is high kΩ, kω

25 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 a) v in is low Q 1 is cutoff v 5 Q 2 is in saturation v out low 0.2. b) v in is high Q 1 is in saturation v 0.2 Q 2 is cutoff v out high 5. Problem For the inverter given in Figure P10.36: 2kΩ, 5kΩ. 1 2 The minimum values of β 1 and β 2 to ensure that Q 1 and Q 2 saturate when v in is high i c 2.4mA, therefore, i c ma 2000 β. Applying KL: 5 + i Therefore, i ma. i β 1 i1 + i or 0.64 β β hoose β 2 10 β Problem For the inverter given in Figure P10.36: 1 2.5kΩ, 2 2kΩ, β1 β2 4. Show that Q 1 saturates when v in is high. Find a condition for i 1 0.8mA i1 3.2mA Applying KL: i 3.2 i2 2mA ; i 2 β i 500 Applying KL: Ω to ensure that Q 2 also saturates. 8mA Problem The basic circuit of a TTL gate, shown in Figure P The logic function performed by this circuit. The circuit performs the function of a 2-input NAND gate. The analysis is similar to xample

26 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem The circuit diagram of a three-input TTL NAND gate, given in Figure P v 1, v 2, v 3, v 2, and v out, assuming that all the input voltages are high. Q 2 and Q 3 conduct, while Q 4 is cutoff. v 1 1.8, v 2 1.2, v 3 0.6, and v 2 v out 0.2. Problem Figure P Show that when two or more emitter-follower outputs are connected to a common load, as shown in Figure P10.54, the O operation results; that is, v 0 v 1 O v 2. v 2 v 1 Q 1 Q 2 v 0 L L L L L L H H L H H L L H H H H H H H L : Low; H : High

Chapter 9 Bipolar Junction Transistor

Chapter 9 Bipolar Junction Transistor hapter 9 ipolar Junction Transistor hapter 9 - JT ipolar Junction Transistor JT haracteristics NPN, PNP JT D iasing ollector haracteristic and Load Line ipolar Junction Transistor (JT) JT is a three-terminal

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

Biasing BJTs CHAPTER OBJECTIVES 4.1 INTRODUCTION

Biasing BJTs CHAPTER OBJECTIVES 4.1 INTRODUCTION 4 DC Biasing BJTs CHAPTER OBJECTIVES Be able to determine the dc levels for the variety of important BJT configurations. Understand how to measure the important voltage levels of a BJT transistor configuration

More information

assess the biasing requirements for transistor amplifiers

assess the biasing requirements for transistor amplifiers 1 INTODUTION In this lesson we examine the properties of the bipolar junction transistor (JT) amd its typical practical characteristics. We then go on to devise circuits in which we can take best advantage

More information

Chapter 2 - DC Biasing - BJTs

Chapter 2 - DC Biasing - BJTs Objectives Chapter 2 - DC Biasing - BJTs To Understand: Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

DC Biasing. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE230 Electronics I 15-Mar / 59

DC Biasing. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE230 Electronics I 15-Mar / 59 Contents Three States of Operation BJT DC Analysis Fixed-Bias Circuit Emitter-Stabilized Bias Circuit Voltage Divider Bias Circuit DC Bias with Voltage Feedback Various Dierent Bias Circuits pnp Transistors

More information

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00

More information

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

More information

At point G V = = = = = = RB B B. IN RB f

At point G V = = = = = = RB B B. IN RB f Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F

More information

Chapter 2. - DC Biasing - BJTs

Chapter 2. - DC Biasing - BJTs Chapter 2. - DC Biasing - BJTs Objectives To Understand : Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

Transistors. Lesson #9 Chapter 4. BME 372 Electronics I J.Schesser

Transistors. Lesson #9 Chapter 4. BME 372 Electronics I J.Schesser Transistors Lesson #9 hapter 4 252 JT egions of Operation 7.03 6.03 5.03 4.03 3.03 2.03 1.03 0.00 Saturation Active i amps i =50 ma 40 ma 30 ma 20 ma 10 ma 0 ma 0 1 2 3 4 5 6 7 8 9 10 v volts utoff There

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

Electronic Circuits. Transistor Bias Circuits. Manar Mohaisen Office: F208 Department of EECE

Electronic Circuits. Transistor Bias Circuits. Manar Mohaisen Office: F208   Department of EECE lectronic ircuits Transistor Bias ircuits Manar Mohaisen Office: F208 mail: manar.subhi@kut.ac.kr Department of Review of the Precedent Lecture Bipolar Junction Transistor (BJT) BJT haracteristics and

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Chapter 3 Output stages

Chapter 3 Output stages Chapter 3 utput stages 3.. Goals and properties 3.. Goals and properties deliver power into the load with good efficacy and small power dissipate on the final transistors small output impedance maximum

More information

ESE319 Introduction to Microelectronics. Output Stages

ESE319 Introduction to Microelectronics. Output Stages Output Stages Power amplifier classification Class A amplifier circuits Class A Power conversion efficiency Class B amplifier circuits Class B Power conversion efficiency Class AB amplifier circuits Class

More information

KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II )

KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II ) KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II ) Most of the content is from the textbook: Electronic devices and circuit theory,

More information

VI. Transistor amplifiers: Biasing and Small Signal Model

VI. Transistor amplifiers: Biasing and Small Signal Model VI. Transistor amplifiers: iasing and Small Signal Model 6.1 Introduction Transistor amplifiers utilizing JT or FET are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly.

More information

CHAPTER 13. Solutions for Exercises

CHAPTER 13. Solutions for Exercises HPT 3 Solutions for xercises 3. The emitter current is gien by the Shockley equation: i S exp VT For operation with i, we hae exp >> S >>, and we can write VT i S exp VT Soling for, we hae 3.2 i 2 0 26ln

More information

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

More information

CHAPTER.4: Transistor at low frequencies

CHAPTER.4: Transistor at low frequencies CHAPTER.4: Transistor at low frequencies Introduction Amplification in the AC domain BJT transistor modeling The re Transistor Model The Hybrid equivalent Model Introduction There are three models commonly

More information

ESE319 Introduction to Microelectronics. BJT Biasing Cont.

ESE319 Introduction to Microelectronics. BJT Biasing Cont. BJT Biasing Cont. Biasing for DC Operating Point Stability BJT Bias Using Emitter Negative Feedback Single Supply BJT Bias Scheme Constant Current BJT Bias Scheme Rule of Thumb BJT Bias Design 1 Simple

More information

SOME USEFUL NETWORK THEOREMS

SOME USEFUL NETWORK THEOREMS APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem

More information

Transistor amplifiers: Biasing and Small Signal Model

Transistor amplifiers: Biasing and Small Signal Model Transistor amplifiers: iasing and Small Signal Model Transistor amplifiers utilizing JT or FT are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly. Then, similar FT

More information

Chapter 13 Bipolar Junction Transistors

Chapter 13 Bipolar Junction Transistors Chapter 3 ipolar Junction Transistors Goal. ipolar Junction Transistor Operation in amplifier circuits. 2. Load-line Analysis & Nonlinear Distortion. 3. Large-signal equialent circuits to analyze JT circuits.

More information

EE 330 Lecture 20. Bipolar Device Modeling

EE 330 Lecture 20. Bipolar Device Modeling 330 Lecture 20 ipolar Device Modeling xam 2 Friday March 9 xam 3 Friday April 13 Review from Last Lecture ipolar Transistors npn stack pnp stack ipolar Devices Show asic Symmetry lectrical Properties not

More information

Figure 1 Basic epitaxial planar structure of NPN. Figure 2 The 3 regions of NPN (left) and PNP (right) type of transistors

Figure 1 Basic epitaxial planar structure of NPN. Figure 2 The 3 regions of NPN (left) and PNP (right) type of transistors Figure 1 Basic epitaxial planar structure of NPN Figure 2 The 3 regions of NPN (left) and PNP (right) type of transistors Lecture Notes: 2304154 Physics and Electronics Lecture 6 (2 nd Half), Year: 2007

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

Section 5.4 BJT Circuits at DC

Section 5.4 BJT Circuits at DC 12/3/2004 section 5_4 JT Circuits at DC 1/1 Section 5.4 JT Circuits at DC Reading Assignment: pp. 421-436 To analyze a JT circuit, we follow the same boring procedure as always: ASSUME, ENFORCE, ANALYZE

More information

Mod. Sim. Dyn. Sys. Amplifiers page 1

Mod. Sim. Dyn. Sys. Amplifiers page 1 AMPLIFIERS A circuit containing only capacitors, amplifiers (transistors) and resistors may resonate. A circuit containing only capacitors and resistors may not. Why does amplification permit resonance

More information

(e V BC/V T. α F I SE = α R I SC = I S (3)

(e V BC/V T. α F I SE = α R I SC = I S (3) Experiment #8 BJT witching Characteristics Introduction pring 2015 Be sure to print a copy of Experiment #8 and bring it with you to lab. There will not be any experiment copies available in the lab. Also

More information

Electronic Circuits. Bipolar Junction Transistors. Manar Mohaisen Office: F208 Department of EECE

Electronic Circuits. Bipolar Junction Transistors. Manar Mohaisen Office: F208   Department of EECE Electronic Circuits Bipolar Junction Transistors Manar Mohaisen Office: F208 Email: manar.subhi@kut.ac.kr Department of EECE Review of Precedent Class Explain the Operation of the Zener Diode Explain Applications

More information

Mod. Sim. Dyn. Sys. Amplifiers page 1

Mod. Sim. Dyn. Sys. Amplifiers page 1 AMPLIFIERS A circuit containing only capacitors, amplifiers (transistors) and resistors may resonate. A circuit containing only capacitors and resistors may not. Why does amplification permit resonance

More information

Biasing the CE Amplifier

Biasing the CE Amplifier Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th

More information

DEPARTMENT OF ECE UNIT VII BIASING & STABILIZATION AMPLIFIER:

DEPARTMENT OF ECE UNIT VII BIASING & STABILIZATION AMPLIFIER: UNIT VII IASING & STAILIZATION AMPLIFIE: - A circuit that increases the amplitude of given signal is an amplifier - Small ac signal applied to an amplifier is obtained as large a.c. signal of same frequency

More information

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

More information

University of Pittsburgh

University of Pittsburgh University of Pittsburgh Experiment #8 Lab Report The Bipolar Junction Transistor: Characteristics and Models Submission Date: 11/6/2017 Instructors: Dr. Minhee Yun John Erickson Yanhao Du Submitted By:

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

More information

figure shows a pnp transistor biased to operate in the active mode

figure shows a pnp transistor biased to operate in the active mode Lecture 10b EE-215 Electronic Devices and Circuits Asst Prof Muhammad Anis Chaudhary BJT: Device Structure and Physical Operation The pnp Transistor figure shows a pnp transistor biased to operate in the

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EECS 40 Spring 2000 Introduction to Microelectronic Devices Prof. King MIDTERM EXAMINATION

More information

Chapter 5. BJT AC Analysis

Chapter 5. BJT AC Analysis Chapter 5. Outline: The r e transistor model CB, CE & CC AC analysis through r e model common-emitter fixed-bias voltage-divider bias emitter-bias & emitter-follower common-base configuration Transistor

More information

Capacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009

Capacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009 Wilfrid Laurier University June 4, 2009 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists of two conductive

More information

Switching circuits: basics and switching speed

Switching circuits: basics and switching speed ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V

More information

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130 ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED

More information

EE105 Fall 2014 Microelectronic Devices and Circuits

EE105 Fall 2014 Microelectronic Devices and Circuits EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati

Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati Basic Electronics Prof. Dr. Chitralekha Mahanta Department of Electronics and Communication Engineering Indian Institute of Technology, Guwahati Module: 2 Bipolar Junction Transistors Lecture-4 Biasing

More information

Figure Circuit for Question 1. Figure Circuit for Question 2

Figure Circuit for Question 1. Figure Circuit for Question 2 Exercises 10.7 Exercises Multiple Choice 1. For the circuit of Figure 10.44 the time constant is A. 0.5 ms 71.43 µs 2, 000 s D. 0.2 ms 4 Ω 2 Ω 12 Ω 1 mh 12u 0 () t V Figure 10.44. Circuit for Question

More information

CE/CS Amplifier Response at High Frequencies

CE/CS Amplifier Response at High Frequencies .. CE/CS Amplifier Response at High Frequencies INEL 4202 - Manuel Toledo August 20, 2012 INEL 4202 - Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

ELECTRONICS IA 2017 SCHEME

ELECTRONICS IA 2017 SCHEME ELECTRONICS IA 2017 SCHEME CONTENTS 1 [ 5 marks ]...4 2...5 a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ]...5 3...6 a. [ 3 marks ]...6 b. [ 3 marks ]...6 4 [ 7 marks ]...7 5...8

More information

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:

Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web:     Ph: Serial : ND_EE_NW_Analog Electronics_05088 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 0-4546 CLASS TEST 08-9 ELECTCAL ENGNEENG Subject

More information

BJT - Mode of Operations

BJT - Mode of Operations JT - Mode of Operations JTs can be modeled by two back-to-back diodes. N+ P N- N+ JTs are operated in four modes. HO #6: LN 251 - JT M Models Page 1 1) Forward active / normal junction forward biased junction

More information

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen

Lecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output

More information

Department of Electrical Engineering and Computer Sciences University of California, Berkeley. Final Exam Solutions

Department of Electrical Engineering and Computer Sciences University of California, Berkeley. Final Exam Solutions Electrical Engineering 42/00 Summer 202 Instructor: Tony Dear Department of Electrical Engineering and omputer Sciences University of alifornia, Berkeley Final Exam Solutions. Diodes Have apacitance?!?!

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of

More information

Chapter 5 Objectives

Chapter 5 Objectives Chapter 5 Engr228 Circuit Analysis Dr Curtis Nelson Chapter 5 Objectives State and apply the property of linearity State and apply the property of superposition Investigate source transformations Define

More information

FYSE400 ANALOG ELECTRONICS

FYSE400 ANALOG ELECTRONICS YSE400 ANALOG ELECTONCS LECTUE 3 Bipolar Sub Circuits 1 BPOLA SUB CCUTS Bipolar Current Sinks and -Sources Transistor operates in forwardactive region. < < sat CE CN max CE < < + BN CN BN max CE N N N

More information

Notes for course EE1.1 Circuit Analysis TOPIC 10 2-PORT CIRCUITS

Notes for course EE1.1 Circuit Analysis TOPIC 10 2-PORT CIRCUITS Objectives: Introduction Notes for course EE1.1 Circuit Analysis 4-5 Re-examination of 1-port sub-circuits Admittance parameters for -port circuits TOPIC 1 -PORT CIRCUITS Gain and port impedance from -port

More information

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Final Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013. Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at

More information

Forward-Active Terminal Currents

Forward-Active Terminal Currents Forward-Active Terminal Currents Collector current: (electron diffusion current density) x (emitter area) diff J n AE qd n n po A E V E V th ------------------------------ e W (why minus sign? is by def.

More information

1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)

1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn

More information

Digital Electronics Part II - Circuits

Digital Electronics Part II - Circuits Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The

More information

mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 3 Dominique Thiébaut

mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 3 Dominique Thiébaut mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 3 Dominique Thiébaut dthiebaut@smith.edu Crash Course in Electricity and Electronics Zero Physics background expected!

More information

Whereas the diode was a 1-junction device, the transistor contains two junctions. This leads to two possibilities:

Whereas the diode was a 1-junction device, the transistor contains two junctions. This leads to two possibilities: Part Recall: two types of charge carriers in semiconductors: electrons & holes two types of doped semiconductors: n-type (favor e-), p-type (favor holes) for conduction Whereas the diode was a -junction

More information

CHAPTER 7 - CD COMPANION

CHAPTER 7 - CD COMPANION Chapter 7 - CD companion 1 CHAPTER 7 - CD COMPANION CD-7.2 Biasing of Single-Stage Amplifiers This companion section to the text contains detailed treatments of biasing circuits for both bipolar and field-effect

More information

Refinements to Incremental Transistor Model

Refinements to Incremental Transistor Model Refinements to Incremental Transistor Model This section presents modifications to the incremental models that account for non-ideal transistor behavior Incremental output port resistance Incremental changes

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time

More information

Introduction to Transistors. Semiconductors Diodes Transistors

Introduction to Transistors. Semiconductors Diodes Transistors Introduction to Transistors Semiconductors Diodes Transistors 1 Semiconductors Typical semiconductors, like silicon and germanium, have four valence electrons which form atomic bonds with neighboring atoms

More information

ECE 2201 PRELAB 5B BIPOLAR JUNCTION TRANSISTOR (BJT) FUNDAMENTALS

ECE 2201 PRELAB 5B BIPOLAR JUNCTION TRANSISTOR (BJT) FUNDAMENTALS EE 2201 PRELAB 5B BIPOLAR JUNTION TRANSISTOR (BJT) FUNDAMENTALS P1. β Meter The circuit of Figure P51 can be used to measure the current gain β of the BJT. Determine values for resistors R1 and R2 to meet

More information

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14

Microelectronic Circuit Design 4th Edition Errata - Updated 4/4/14 Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

MP6901 MP6901. High Power Switching Applications. Hammer Drive, Pulse Motor Drive and Inductive Load Switching. Maximum Ratings (Ta = 25 C)

MP6901 MP6901. High Power Switching Applications. Hammer Drive, Pulse Motor Drive and Inductive Load Switching. Maximum Ratings (Ta = 25 C) TOSHIBA Power Transistor Module Silicon Epitaxial Type (Darlington power transistor in ) High Power Switching Applications. Hammer Drive, Pulse Motor Drive and Inductive Load Switching. Industrial Applications

More information

Lecture 7: Transistors and Amplifiers

Lecture 7: Transistors and Amplifiers Lecture 7: Transistors and Amplifiers Hybrid Transistor Model for small AC : The previous model for a transistor used one parameter (β, the current gain) to describe the transistor. doesn't explain many

More information

A.M. WEDNESDAY, 13 May minutes

A.M. WEDNESDAY, 13 May minutes Candidate Name Centre Number Candidate Number 0 GCSE 293/02 ELECTRONICS MODULE TEST E1 HIGHER TIER AM WEDNESDAY, 13 May 2009 45 minutes For Examiner s use Total Mark ADDITIONAL MATERIALS In addition to

More information

KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D)

KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D) KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D) Most of the content is from the textbook: Electronic devices and circuit theory, Robert

More information

Section 1: Common Emitter CE Amplifier Design

Section 1: Common Emitter CE Amplifier Design ECE 3274 BJT amplifier design CE, CE with Ref, and CC. Richard Cooper Section 1: CE amp Re completely bypassed (open Loop) Section 2: CE amp Re partially bypassed (gain controlled). Section 3: CC amp (open

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Designing Information Devices and Systems I Fall 2018 Lecture Notes Note Introduction: Op-amps in Negative Feedback

Designing Information Devices and Systems I Fall 2018 Lecture Notes Note Introduction: Op-amps in Negative Feedback EECS 16A Designing Information Devices and Systems I Fall 2018 Lecture Notes Note 18 18.1 Introduction: Op-amps in Negative Feedback In the last note, we saw that can use an op-amp as a comparator. However,

More information

MICROELECTRONIC CIRCUIT DESIGN Second Edition

MICROELECTRONIC CIRCUIT DESIGN Second Edition MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113

More information

SAMPLE EXAMINATION PAPER

SAMPLE EXAMINATION PAPER IMPERIAL COLLEGE LONDON Design Engineering MEng EXAMINATIONS 2016 For Internal Students of the Imperial College of Science, Technology and Medicine This paper is also taken for the relevant examination

More information

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed)

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed) ECE-342 Test 2 Solutions, Nov 4, 2008 6:00-8:00pm, Closed Book (one page of notes allowed) Please use the following physical constants in your calculations: Boltzmann s Constant: Electron Charge: Free

More information

55:041 Electronic Circuits The University of Iowa Fall Final Exam

55:041 Electronic Circuits The University of Iowa Fall Final Exam Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered

More information

LB1846M, 1848M. Low-Voltage/Low Saturation Voltage Type Bidirectional Motor Driver

LB1846M, 1848M. Low-Voltage/Low Saturation Voltage Type Bidirectional Motor Driver Ordering number : ENN5339A Monolithic Digital IC LB1846M, 1848M Low-Voltage/Low Saturation Voltage Type Bidirectional Motor Driver Overview The LB1846M and LB1848M are 2-channel low-voltage, low saturation

More information

As light level increases, resistance decreases. As temperature increases, resistance decreases. Voltage across capacitor increases with time LDR

As light level increases, resistance decreases. As temperature increases, resistance decreases. Voltage across capacitor increases with time LDR LDR As light level increases, resistance decreases thermistor As temperature increases, resistance decreases capacitor Voltage across capacitor increases with time Potential divider basics: R 1 1. Both

More information

POLYTECHNIC UNIVERSITY Electrical Engineering Department. EE SOPHOMORE LABORATORY Experiment 2 DC circuits and network theorems

POLYTECHNIC UNIVERSITY Electrical Engineering Department. EE SOPHOMORE LABORATORY Experiment 2 DC circuits and network theorems POLYTECHNIC UNIVERSITY Electrical Engineering Department EE SOPHOMORE LABORATORY Experiment 2 DC circuits and network theorems Modified for Physics 18, Brooklyn College I. Overview of Experiment In this

More information

Transistor Characteristics and A simple BJT Current Mirror

Transistor Characteristics and A simple BJT Current Mirror Transistor Characteristics and A simple BJT Current Mirror Current-oltage (I-) Characteristics Device Under Test DUT i v T T 1 R X R X T for test Independent variable on horizontal axis Could force current

More information

EE 434 Lecture 33. Logic Design

EE 434 Lecture 33. Logic Design EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X

More information

Vidyalankar S.E. Sem. III [EXTC] Analog Electronics - I Prelim Question Paper Solution

Vidyalankar S.E. Sem. III [EXTC] Analog Electronics - I Prelim Question Paper Solution . (a) S.E. Sem. [EXTC] Analog Electronics - Prelim Question Paper Solution Comparison between BJT and JFET BJT JFET ) BJT is a bipolar device, both majority JFET is an unipolar device, electron and minority

More information

The equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A =

The equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A = The equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A = 10 10 4. Section Break Difficulty: Easy Learning Objective: Understand how real operational

More information

Solved Problems. Electric Circuits & Components. 1-1 Write the KVL equation for the circuit shown.

Solved Problems. Electric Circuits & Components. 1-1 Write the KVL equation for the circuit shown. Solved Problems Electric Circuits & Components 1-1 Write the KVL equation for the circuit shown. 1-2 Write the KCL equation for the principal node shown. 1-2A In the DC circuit given in Fig. 1, find (i)

More information

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

More information

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating ELEC 3908, Physical Electronics, Lecture 18 The Early Effect, Breakdown and Self-Heating Lecture Outline Previous 2 lectures analyzed fundamental static (dc) carrier transport in the bipolar transistor

More information

1200 V 600 A IGBT Module

1200 V 600 A IGBT Module 1200 V 600 A IGBT RoHS Features Trench-gate field stop IGBT technology Low saturation voltage and positive temperature coefficient Fast switching and short tail current Free wheeling diodes with fast and

More information

Junction Bipolar Transistor. Characteristics Models Datasheet

Junction Bipolar Transistor. Characteristics Models Datasheet Junction Bipolar Transistor Characteristics Models Datasheet Characteristics (1) The BJT is a threeterminal device, terminals are named emitter, base and collector. Small signals, applied to the base,

More information

Summary Notes ALTERNATING CURRENT AND VOLTAGE

Summary Notes ALTERNATING CURRENT AND VOLTAGE HIGHER CIRCUIT THEORY Wheatstone Bridge Circuit Any method of measuring resistance using an ammeter or voltmeter necessarily involves some error unless the resistances of the meters themselves are taken

More information