Chapter 10 Instructor Notes

Transcription

1 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 hapter 10 nstructor Notes hapter 10 introduces bipolar junction transistors. The material on transistors has been reorganized in this 4 th dition, and is now divided into two independent chapters, one on bipolar devices, and one on field-effect devices. The two chapters are functionally independent, except for the fact that Section 10.1, introducing the concept of transistors as amplifiers and switches, can be covered prior to starting hapter 11 if the instructor decides to only teach field-effect devices. Section 10.2 introduces the fundamental ideas behind the operation of bipolar transistors, and illustrates the calculation of the state and operating point of basic transistor circuits. The discussion of the properties of the JT in Section 10.2 is centered around a description of the base and collector characteristics, and purposely avoids a detailed description of the physics of the device, with the intent of providing an intuitive understanding of the transistor as an amplifier and electronic switch. xample 10.5 introduces the use of lectronics Workbench (W) as a tool for analyzing electronics circuits; the D- OM contains an introduction to the software package and a number of solved problems. Section 10.3 introduces large-signal models of the JT, and also includes the box Focus on Methodology: Using device data sheets (pp ). xample 10.7 (LD Driver) and the box Focus on Measurements: Large Signal Amplifier for Diode Thermometer (pp ) provide two application examples that include W solutions. Section 8.4 introduces the analysis of JT switches and presents TTL gates. The end-of-chapter problems are straightforward applications of the concepts illustrated in the chapter. Learning Objectives 1. Understand the basic principles of amplification and switching. Section Understand the physical operation of bipolar transistors; determine and select the operating point of a bipolar transistor circuit; understand the principle of small signal amplifiers. Section Understand the large-signal model of the bipolar transistor, and apply it to simple amplifier circuits. Section Understand the operation of bipolar transistor as a switch and analyze basic analog and digital gate circuits. Section

2 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Section 10.2: Operation of the ipolar Junction Transistor Problem 10.1 Transistor diagrams, as shown in Figure P10.1: (a) pnp, 0.6 and 4.0 (b) npn, 0.7 and 0.2 (c) npn, 0.7 and 0.3 (d) pnp, 0.6 and 5.4 For each transistor shown in Figure P10.1, determine whether the and junctions are forward or reverse biased, and determine the operating region. (a) for a pnp transistor implies that the junction is forward-biased The junction is reverse-biased. Therefore, the transistor is in the active region. (b) for a npn transistor implies that the junction is reverse-biased The junction is reverse-biased. Therefore, the transistor is in the cutoff region. (c) 0.7 for a npn transistor implies that the junction is forward-biased The junction is forward-biased. Therefore, the transistor is in the saturation region. (d) 0.6 for a pnp transistor implies that the junction is reverse-biased The junction is forward-biased. Therefore, the transistor is in the active region. Problem 10.2 Transistor type and operating characteristics: a) npn, 0.8 and 0.4 b) npn, 1.4 and 2.1 c) pnp, 0.9 and 0.4 d) npn, and 0.6 The region of operation for each transistor. a) Since 0.8, the junction is forward-biased Thus, the junction is forward-biased. Therefore, the transistor is in the saturation region. 10.2

3 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 b) The junction is forward-biased The junction is reverse-biased. Therefore, the transistor is in the active region. c) 0.9 for a pnp transistor implies that the junction is forward-biased The junction is forward-biased. Therefore, the transistor is in the saturation region. d) With - 1.2, the junction is reverse-biased The junction is reverse-biased. Therefore, the transistor is in the cutoff region. Problem 10.3 The circuit of Figure P10.3. β 100. The operating point and the state of the transistor. 0.6 and the junction is forward biased. 1 β 1.39mA µA 820 Writing KL around the right-hand side of the circuit: ( + ) 12 (1.39)(2.2) ( )(0.910) > The transistor is in the active region. 10.3

4 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem 10.4 The magnitude of a pnp transistor's emitter and base current, and the magnitudes of the voltages across the emitter-base and collector-base junctions: 6 ma, 0.1 ma and 0.65, 7.3. a). b). c) The total power dissipated in the transistor, defined as P +. a) b) ma. c) The total power dissipated in the transistor can be found to be: P mw. Problem 10.5 The circuit of Figure P10.5, assuming the JT has The emitter current and the collector-base voltage. Applying KL to the right-hand side of the circuit, Then, on the left-hand side, assuming β >> 1: ( 520) (15) ( ) ) µA Problem 10.6 The circuit of Figure P10.6, assuming the JT has 0.6 and β 150. The operating point and the region in which the transistor operates. 10.4

5 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Define 3.3kΩ, 1.2kΩ, 1 62kΩ, 2 15kΩ, 18 y applying Thevenin s theorem from base and mass, we have 1 1 β kω ma µa + (1 + β ) From the value of it is clear that the JT is in the active region. Problem 10.7 The circuit of Figure P10.7, assuming the JT has The emitter current and the collector-base voltage. Applying KL to the right-hand side of the circuit, µA Since β >> 1, 497.4µA Applying KL to the left-hand side: + DD DD Problem 10.8 The circuit of Figure P10.7, assuming the emitter resistor is changed to 22 kω and the JT has 0.6. The operating point of the transistor µ A , 881.8µA 10.5

6 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 DD Problem 10.9 The collector characteristics for a certain transistor, as shown in Figure P10.9. a) The ratio / for 10 and 100 µa, 200 µa, and 600 µa b), assuming the maximum allowable collector power dissipation is 0.5 W for 500 µa. a) For 100 µa and 10, from the characteristics, we have 17 ma. The ratio / is 170. For 200 µa and 10, from the characteristics, we have 33 ma. The ratio / is 165. For 600 µa and 10, from the characteristics, we have 86 ma. The ratio / is 143. b) For 500 µa, and if we consider an average β from a., we have P +, therefore: ma. The power dissipated by the transistor is P Problem Figure P10.10, assuming both transistors are silicon-based with β 100. a) 1, 1, 1. b) 2, 2, µA β 3.907mA a) From KL: b) Again, from KL: mA β ma β and

7 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Also, ( ) (1.07) ( ) (1.07) (20) Finally, 2 Problem ollector characteristics of the 2N3904 npn transistor, see data sheet pg The operating point of the transistor in Figure P10.11, and the value of β at this point. onstruct a load line. Writing KL, we have: Then, if 0, 50 ; and if 0, 10mA. The load line is shown superimposed on the collector characteristic below: load line The operating point is at the intersection of the load line and the 20µA line of the characteristic. Therefore, Q 5 ma and Q 20. Under these conditions, an 5 µa increase in yields an increase in of approximately 6 5 1mA. Therefore, β The same result can be obtained by checking the h F gain from the data-sheets corresponding to 5 ma. 10.7

8 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem The circuit shown in Figure P With reference to Figure 10.20, assume 0.6, 0.2 The operating point of the transistor, by computing the ratio of collector current to base current sat 0.2, therefore 9.8mA , therefore 102µA sat << β Problem For the circuit shown in Figure P10.13, a) b) c) 1 and 0.6. d) e) β f) α. a)

9 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter b) 20µA c) 800µA 5000 d) µA 780 e) β f) α. Problem For the circuit shown in Figure P10.14: 20 β MΩ 2 300kΩ 3kΩ 1kΩ 1kΩ 0.6kΩ cos[ t]m L S v 3 S. The Thèvenin equivalent of the part of the circuit containing 1, 2, and with respect to the terminals of 2. edraw the schematic using the Thèvenin equivalent. xtracting the part of the circuit specified, the Thèvenin equivalent voltage is the open circuit voltage. The equivalent resistance is obtained by suppressing the ideal independent voltage source: Note that must remain in the circuit because it supplies current to other parts of the circuit: 10.9

10 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem For the circuit shown in Figure P10.14: 15 β kΩ kΩ 200Ω 200Ω 1.5kΩ 0.9kΩ cos[ t]m L S Q and the region of operation. v 3 S. Simplify the circuit by obtaining the Thèvenin equivalent of the biasing network in the base circuit: D : Suppress : TH eq kω edraw the circuit using the Thèvenin equivalent. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region; then, the base-emitter junction is forward biased. Q 700 m [Si] Q β Q Q ( β + 1) Q Then: 10.10

11 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 KL: - Q + Q Q +[ β + 1 ] Q Q ( )( 200) Q µa Q +[ β + 1 ] Q 0 KL : - Q Q Q Q β ( β + 1) ( ) - Q Q - Q - Q Q - + Q ma ma The collector-emitter voltage is greater than its saturation value (0.3 for Silicon). Therefore the initial assumption (operation in the active region) was correct and the solution is valid. Notes: 1. f the collector-emitter voltage were less than its saturation value, the transistor would be operating in its "saturation" or "ohmic" region. n this case, the collector-emitter voltage is equal to its saturation value (0.3 for Silicon). The solution for the base current remains valid. However, the parameter β and the solution for the collector and emitter curents become invalid. n the saturation region, the base-emitter junction is still forward biased and its voltage remains the same. A solution for the collector and emitter currents is possible using the collector-emitter saturation voltage (0.3 for Silicon) in a KL. 2. n the saturation region, the base current has no control over the collector or emitter currents (since β is invalid). Therefore, amplification is impossible. Problem For the circuit shown in Figure P10.14: 15 β kΩ kΩ 4kΩ 200Ω 1.5kΩ 0.9kΩ cos[ t]m L S Q and the region of operation. v 3 S

12 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Simplify the circuit by obtaining the Thèvenin equivalent of the biasing network in the base circuit: edraw the circuit using the Thèvenin equivalent. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region. Then, the base-emitter junction is forward biased. Q Q Q Q ( β ) Q 700 m [Si] β + 1 KL : - + Q + Q + Q Q + Q + [ β + 1 ] Q 0 Q - Q + [ β + 1 ] ( )( 200) µa KL : - Q Q Q Q β ( β + 1) ( ) - Q Q - Q - Q Q - + Q ma ma The collector-emitter voltage is less (more negative) than its saturation value (+ 0.3 for Silicon). Therefore the initial assumption (operation in the active region) was incorrect and the solution is not valid. The device is operating in the saturation region with a saturation collector-emitter voltage equal to 0.3. The solutions for the collector and emitter currents are invalid. TH ALD SOLUTON: KL : - - v Q -SAT Q Q Q Q - [ Q + Q ] - v -SAT - Q + 0 Q - Q - v + -SAT mA The solution for the base current is valid. The value of beta given is not valid

13 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem For the circuit shown in Figure P10.17: 12 β kΩ 2 22kΩ 0.5kΩ L 16Ω Q at the D operating point.. Simplify the circuit by obtaining the Thèvenin equivalent of the biasing network ( 1,, 2, ) in the base circuit: D : Suppress : eq 17.35kΩ edraw the circuit using the Thèvenin equivalent. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region. Then, the base-emitter junction is forward biased. Q TH 700 m O [Si] Q [ β + 1 ] Q KL : - + Q + Q + Q Q + Q + [ β + 1 ] Q 0 Q Q - Q + ( β + 1) ( ) 6 ( β + 1 ) ( ) Q µA ma KL : Q - Q - - Q Q The collector-emitter voltage is greater than its saturation value (0.3 for Silicon). Therefore the initial assumption (operation in the active region) was correct and the solution is valid. Problem For the circuit shown in Figure P10.18: 10.13

14 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter β kΩ 3kΩ 3kΩ v cos S t. 6kΩ 0.6kΩ [ ]m L s Q and the region of operation. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region; then, the base-emitter junction is forward biased and: Q 700 m [Si] Q β Q Q ( β + 1) Q KL : KL : - Q + Q [ β + β Q Q + Q ] ( )( 3000) 6 ( 100) ma Q Q 6 ( β + 1) ( ) ma Q Q + - Q - Q - Q + Q + - Q - Q µ A The collector-emitter voltage is greater (more positive) than its saturation value (+ 0.3 for Silicon). Therefore the initial assumption (operation in the active region) was correct and the solution is valid. Notes: 1. D power may be supplied to an npn JT circuit by connecting the positive terminal of a D source to the collector circuit, or, by connecting the negative terminal of a D source to the emitter circuit, or, as was done here, both. 2. n a pnp JT circuit the polarities of the sources must be reversed. Negative to collector and positive to emitter. Problem For the circuit shown in Figure P10.19: 12 β kΩ 1.9kΩ 2.3kΩ 10.14

15 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 10kΩ 0.5kΩ cos[ t]m L s Q and the region of operation. v 3 S. The "D blocking" or "A coupling" capacitors act as open circuits for D; therefore, the signal source and load can be neglected since this is a D problem. Specify directions of current and polarities of voltages. Assume the transistor is operating in its active region; then, the base-emitter junction is forward biased. The base and collector currents both flow through the collector resistor in this circuit. Q 700 m [Si] Q β Q Q [ β + 1 ] Q KL : Q + Q - 0 Q + Q β Q + Q [ β + 1 ] Q KL : - Q - Q - Q [ β + 1 ] Q [ + ] - Q - Q + 0 Q Q - Q µA 3 + [ β + 1 ] [ + 10 [ β + 1 ] Q ] [ ( ) ( ) ] 6 ( ) mA KL : - Q Q - Q Q The collector-emitter voltage is greater than its saturation value (0.3 for Silicon). Therefore the initial assumption (operation in the active region) was correct and the solution is valid. Problem For the circuit shown in Figure P10.19: µF β kΩ 3.3kΩ 3.3kΩ v cos S t. 1.7kΩ 70Ω [ ]m L s 10.15

16 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Q and the region of operation. When β is very high (say, greater than 50) the "high beta approximation" can be used, i.e.: β Using this approximation in this problem: Q 12.5µA Q Q ma Q The collector-emitter voltage is greater than the saturation value (but not by much) so the original assumption (operation in the active region) and the solution are valid. However, when a signal is introduced into the circuit, the collector-emitter voltage will vary about its Q point value. Since the Q point is close to saturation, saturation and severe distortion due to clipping is likely. Problem For the circuit shown in Figure P10.14: µ F 1 220kΩ 2 55kΩ 3kΩ 710Ω 3kΩ 0.6kΩ v 0 sin( ωt ) 0 10m. L D operating point: Q 19.9µ A s 7.61 S i i Q Transfer characteristic and β of the npn silicon transistor: v Q + vbe s e s e β 100 T T Device i-v characteristic plotted in Figure P9.21. a) The no-load large signal gain [v 0 /v i ]. b) Sketch the waveform of the output voltage as a function of time. c) How the output voltage is distorted compared with the input waveform. a) Simplify the circuit by determining the Thèvenin equivalent of the biasing network in the base circuit. D : Suppress : TH kω eq 1 2 First, determine the collector and emitter Q point:

17 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 KL : - Q - Q - Q + 0 Q Q β Q ma 6 Q [ β + 1 ] Q Now, determine the D load line (circuit characteristic). KL : i - i - v - i - v - v β β 0 f : v ma f : mA 0 v 15 i β + 1 i β 0 [ntercept 1] [ntercept 2] Plot the D load line on the same plot as the transistor i-v characteristic. Note that the collector current is a linear function of the collector-emitter voltage. Only two points (the two intercepts shown as Points 1 and 2 on the plot) are required to plot a linear function. The D load line should pass through the Q point. The A load line can now be plotted. t will pass through the Q point as does the D load line; however, its intercepts cannot be directly determined. nstead, its slope will be determined. The slope and the Q point can then be used to plot the A load line. Slope A ma mA - 6 i v For A the capacitors act as short circuits. The bypass capacitor in parallel with the emitter resistor shorts out any A voltage across it. The collector coupling capacitor acts as a short and connects the load resistor to the circuit. However, no-load conditions are specified, i.e., the load current is zero or the load resistor is replaced by an open circuit. With no signal, the circuit operates at its Q point. When a signal is introduced, the operating point changes along the A load line as a function of the signal voltage. Unfortunately, the device i-v characteristic is plotted as a function of input (base) current instead of voltage. ut, there is the static characteristic that relates collector current to base-emitter voltage: i s e v T s e Q T + v be [ s e Q T ] e v be T Q e v be T i i β Q β e v be T Q e v be T The base-emitter signal voltage is related to the input signal voltage. At sufficiently high frequencies (the "mid"-frequency range) the capacitors can be modeled as short circuits for A. This means that there is no A voltage across either the A coupling (D blocking) capacitor or the capacitor bypassing the emitter resistor. Using superposition to sum only A voltages around the loop: 10.17

18 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 KL :- v + v + v + v 0 v v i c be e c e be i vbe vi i Q e [ 19.9µA ] T e26 m This transfer function can now be used to give the base current as a function of the input voltage. The intersection of the base current curves with the A load line give the corresponding values of the collector current and collector-emitter voltage (points 3, Q and 4 on the plot): ωt [rad] v i [m] i [µa] i [ma] v [] v o [] 0,π,2π π/ π/ The capacitor connecting the load to the circuit is a D blocking [and A coupling] capacitor. emember that for no load conditions, the load resistor is assumed to be open. Again using superposition to sum only A voltages around the loop and modeling the capacitors as shorts: - ve + vce + vc + vo 0 ve vc 0 vo vce v - Q The no-load voltage gain can be determined using the maximum excursion in the input and output voltages: A vo v v o ( 1.54) ( ) 3 3 ( ) ( ) i When the input voltage becomes more positive, the output voltage becomes more negative and vice versa. This is called "phase inversion" and is why the gain is negative. n normal amplification this is not important. f the loading effect of the load resistance is included, the A load line will be steeper and the gain will be reduced. b) A plot is a large number of calculated points plotted and connected by a smooth curve. n a sketch, only the most significant points [maxima, minima, intercepts, etc] are calculated, plotted, and connected by a carefully drawn smooth curve. c) The output waveform is very distorted, i.e., it is not a true linearly amplified copy of the input waveform. This is most obvious when the positive and negative peaks of the two curves are compared: nput voltage +10 m -10 m Output voltage The two peaks of the input voltage are equal; however, the positive peak is amplified less than the negative peak. The nonlinear (exponential) behavior of the transistor causes the amplification to be nonlinear and the output waveform to be very distorted. This is characteristic of large signal amplifiers. ven more serious distortion could occur if the input voltage (also called the "excitation" or "drive") were increased so that saturation or cutoff occurs. This causes "clipping" and a severely distorted output. v v 10.18

19 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Section 10.3: JT Large-Signal Model Problem For the circuit shown in Figure 10.24: off LD 0, on 1.4, ange of. 5, LD 5 ma, 10 ma, P max 1kΩ, 100 mw LD sat Ω 0.01 LD From the maximum power LD max > P max LD LD LD max ma 1.4 sat 47 Ω 5, 0.7, sat 0.2, β 95, Therefore, [47, 340] Ω Problem For the circuit shown in Figure 10.26:.1, 33kΩ, 12, 0.75, 6, β 188.5, 500 Ω D 1 Q S The resistance. The current through the resistance is given by D Q The current through S is S Q S D µa ma 500 t follows that the current through the resistance is Q β + S Finally, 11.8 ma Q Ω Q 10.19

20 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem For the circuit shown in Figure 10.24: off LD 0, on 1.4, 5, LD ange of. f the JT is in saturation LD max 10 ma, P sat 5 ma, max 10 ma 340 Ω, 100 mw n order to guarantee that the JT is in saturation on on / β max kω Ω 5, 0.7, sat 0.2, β 95, Problem For the circuit shown in Figure 10.24: off LD 0, on 1.4, 5, LD max 10mA, P 5mA, max 10kΩ, 100mW 340Ω, 5, 0.7, sat 0.2, Minimum value of β that will ensure the correct operation of the LD. on ma LD min 0.01 β min Problem For the circuit shown in Figure 10.24: off LD 0, on 1.4, 3.3, LD max 10mA, P 5mA, max 100mW 10kΩ, 340Ω, 5, 0.7, sat 0.2, 10.20

21 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Minimum value of β that will ensure the correct operation of the LD. on ma LD min 0.01 β min Problem For the circuit shown in Figure 10.24: off 0, on 5, max 1mA, 1kΩ, 12 Ω, 13, 1A Minimum value of β that will ensure the correct operation of the fuel injector. 0.7, sat 1, sat A 12 1 β min max Problem For the circuit shown in Figure 10.24: off 0, on 5, max 1A 1mA, β 2000, 12 Ω, The range of that will ensure the correct operation of the fuel injector. 13, 0.7, sat 1, 10.21

22 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 f the JT is in saturation sat 1A ecause this is the minimum value allowed for the current to drive the fuel injector, it is necessary to guarantee that the JT is in saturation. n order to guarantee that the JT is in saturation on on / β max kω kΩ Problem For the circuit shown in Figure 10.24: off 0, 3.3, max 1A on 1mA, β 2000, 12 Ω, The range of that will ensure the correct operation of the fuel injector. f the JT is in saturation sat 1A 13, 0.7, ecause this is the minimum value allowed for the current to drive the fuel injector, it is necessary to guarantee that the JT is in saturation. n order to guarantee that the JT is in saturation on on / β max kω kω sat 1, 10.22

23 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Section 10.4: JT Switches and Gates Problem The circuit given in Figure P Show that the given circuit functions as an O gate if the output is taken at v 01. onstruct a state table. This table clearly describes an AND gate when the output is taken at v o1. v 1 v 2 Q 1 Q 2 Q 3 v o1 v o2 0 0 off off on off on off on off off on on off 5 0 Problem The circuit given in Figure P Show that the given circuit functions as a NO gate if the output is taken at v 02. See the state table constructed for Problem This table clearly describes a NO gate when the output is taken at v o2. Problem The circuit given in Figure P Show that the given circuit functions as an AND gate if the output is taken at v 01. onstruct a state table. This table clearly describes an AND gate when the output is taken at v o

24 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 v 1 v 2 Q 1 Q 2 Q 3 v o1 v o2 0 0 off off on off on on on off on on on off 5 0 Problem The circuit given in Figure P Show that the given circuit functions as a NAND gate if the output is taken at v 02. See the state table constructed for Problem This table clearly describes a NAND gate when the output is taken at v o2. Problem n the circuit given in Figure P10.34 the minimum value of v in for a high input is 2.0. Assume that the transistor Q 1 has a β of at least 10. The range for resistor that can guarantee that the transistor is on i c 2.4mA, therefore, i 2000 i /β 0.24 ma. (v in )min 2.0 and (v in )max 5.0, therefore, applying KL: -vin + i vin 0.6 or. Substituting for (v i in )min and (v in )max, we find the following range for : 5.833kΩ k Ω Problem For the circuit given in Figure P10.35: a) v, v out, and the state of the transistor Q 1 when v in is low. b) v, v out, and the state of the transistor Q 1 when v in is high kΩ, kω

25 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 a) v in is low Q 1 is cutoff v 5 Q 2 is in saturation v out low 0.2. b) v in is high Q 1 is in saturation v 0.2 Q 2 is cutoff v out high 5. Problem For the inverter given in Figure P10.36: 2kΩ, 5kΩ. 1 2 The minimum values of β 1 and β 2 to ensure that Q 1 and Q 2 saturate when v in is high i c 2.4mA, therefore, i c ma 2000 β. Applying KL: 5 + i Therefore, i ma. i β 1 i1 + i or 0.64 β β hoose β 2 10 β Problem For the inverter given in Figure P10.36: 1 2.5kΩ, 2 2kΩ, β1 β2 4. Show that Q 1 saturates when v in is high. Find a condition for i 1 0.8mA i1 3.2mA Applying KL: i 3.2 i2 2mA ; i 2 β i 500 Applying KL: Ω to ensure that Q 2 also saturates. 8mA Problem The basic circuit of a TTL gate, shown in Figure P The logic function performed by this circuit. The circuit performs the function of a 2-input NAND gate. The analysis is similar to xample

26 G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 Problem The circuit diagram of a three-input TTL NAND gate, given in Figure P v 1, v 2, v 3, v 2, and v out, assuming that all the input voltages are high. Q 2 and Q 3 conduct, while Q 4 is cutoff. v 1 1.8, v 2 1.2, v 3 0.6, and v 2 v out 0.2. Problem Figure P Show that when two or more emitter-follower outputs are connected to a common load, as shown in Figure P10.54, the O operation results; that is, v 0 v 1 O v 2. v 2 v 1 Q 1 Q 2 v 0 L L L L L L H H L H H L L H H H H H H H L : Low; H : High