Course Administration. CPE/EE 427, CPE 527 VLSI Design I L04: MOS Transistors. Review: CMOS Process at a Glance


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1 Course Administration CPE/EE 7, CPE 7 VLI esign I L: MO Transistors epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( ) Instructor: TA: Labs: URL: Text: Aleksandar Milenkovic E 7L Office Hrs: MW 9:: Fathima Tareen Accounts on olaris machines, Lab# is on Analysis and esign of igital ICs, rd Edition Hodges et. al., Previous: IC Fabrication (slides, Chapter ) Today: MO Transistors (slides, Chapter ) 9// VLI esign I; A. Milenkovic Review: CMO Process at a lance Review: implified CMO Inverter Process efine active areas Etch and fill trenches Implant well regions eposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows eposit and pattern metal layers One full photolithography sequence per layer (mask) uilt (roughly) from the bottom up metal metal polysilicon exception! source and drain diffusions tubs (aka wells, active areas) cut line p well 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic Review: IntraLayer esign Rules Review: InterLayer esign Rule Origins Well Active elect ame Potential or 6 ifferent Potential 9 Contact or Via Hole Polysilicon Metal Metal. Transistor rules transistor formed by overlap of active and poly layers Transistors Unrelated Poly & iffusion Catastrophic error Thinner diffusion, but still working 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic 6
2 Review: Vias and Contacts esign Abstraction Levels YTEM Via Metal to Active Contact Metal to Poly Contact + MOULE ATE CIRCUIT V in V out EVICE 9// VLI esign I; A. Milenkovic 7 9// VLI esign I; A. Milenkovic 8 oal of this lecture (Chapter ) Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for PICE simulation Analysis of secondary and deepsubmicron effects Future trends A p n The iode Al A io p n Cross section of pnjunction in an IC process Al A Onedimensional representation diode symbol Mostly occurring as parasitic element in igital ICs 9// VLI esign I; A. Milenkovic 9 9// VLI esign I; A. Milenkovic epletion Region iode Current hole diffusion electron diffusion p n (a) Current flow. Charge ensity hole drift electron drift  ρ + x istance (b) Charge density. Electrical Field ξ x (c) Electric field. Potential V ψ W W x (d) Electrostatic potential. 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic
3 I (ma) Ideal iode Equation The MO Transistor The ideal diode equation (for both forward and reversebias conditions) is I = I (e V / φ T ) + V Polysilicon Aluminum where V is the voltage applied to the junction a forward bias lowers the potential barrier allowing carriers to flow across the diode junction a reverse bias raises the potential barrier and the diode becomes nonconducting φ T = kt/q = 6mV at K I is the saturation current of the diode V (V) 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic The NMO Transistor Cross ection n areas have been doped with donor ions (arsenic) of concentration N  electrons are the majority carriers V witch Model of NMO Transistor ate ource W Polysilicon ate L p substrate ate oxide rain FieldOxide (io ) p+ stopper ource (of carriers) rain (of carriers) Open (off) (ate = ) Closed (on) ( ate = ) Connected to N for NMO R on ulk (ody) p areas have been doped with acceptor ions (boron) of concentration N A  holes are the majority carriers 9// VLI esign I; A. Milenkovic V < V T V > V T 9// VLI esign I; A. Milenkovic 6 witch Model of PMO Transistor Threshold Voltage Concept V ource (of carriers) ate rain (of carriers) Open (off) (ate = ) Closed (on) ( ate = ) R on Connected to V for PMO V +  n channel p substrate depletion region V > V V T V < V V T 9// VLI esign I; A. Milenkovic 7 The value of V where strong inversion occurs is called the threshold voltage, V T 9// VLI esign I; A. Milenkovic 8
4 V T (V) The Threshold Voltage The ody Effect where V T = V T + γ( φ F + V  φ F ) V T is the threshold voltage at V = and is mostly a function of the manufacturing process ifference in workfunction between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc. V is the sourcebulk voltage φ F = φ T ln(n A /n i ) is the Fermi potential (φ T = kt/q = 6mV at K is the thermal voltage; N A is the acceptor ion concentration; n i.x cm  at K is the intrinsic carrier concentration in pure silicon) γ = (qε si N A )/C ox is the bodyeffect coefficient (impact of changes in V ) (ε si =.x  F/m is the permittivity of silicon; C ox = ε ox /t ox is the gate oxide capacitance with ε ox =.x  F/m) V (V) V is the substrate bias voltage (normally positive for nchannel devices with the body tied to ground) A negative bias causes V T to increase from.v to.8v 9// VLI esign I; A. Milenkovic 9 9// VLI esign I; A. Milenkovic Transistor in Linear Mode Current flowing in the transistor Assuming V > V T V  V(x) + x V I Current flowing in the transistor: I dsn = Q/t f Q charge, t f time for flight t f = L/v x Velocity of electrons: v =  µ n * E µ n electron mobility (cm /Vs); µ p hole mobility (cm /Vs); E electric field (vector) E x horizontal component of E, E x =  V ds /L v x horizontal component of v, v x =  µ n * E x t f = L/v x = L /µ n *V ds The current is a linear function of both V and V 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic Current flowing in the transistor (cont d) Q = C(V gc V tn ) V gc voltage between the gate and the channel charge only appears on the lower plate when V gc exceeds V tn V gc is not constant; V gc = V gs at the source, V gc = V gs V ds at the drain => sum (integrate) the charge all the way across the channel from x = (at the source) to x = L (at the drain) Assume: V gc (x) is linear function of distance => V gc = [V gs + (V gs V ds )]/ = V gs V ds / C the gate capacitance (parallelplate capacitor with length L, width W, a plate separation equal to the gateoxide thickness T ox, ε ox the gate oxide permittivity; ε ox =.x  F/m, T ox = Å) C = ε ox *W*L/T ox = C ox *W*L; C ox gate capacitance per unit area Q = C ox *W*L*[(V gs V tn ) V ds /] Current flowing in the transistor (cont d) t f = L/v x = L /µ n *Vds Q = C ox *W*L*[(V V TN ) V /] I N = (W/L)*µ n *C ox *[(V V TN ) V /]*V k n = µ n *C ox process transconductance parameter β n = (W/L)*k n transistor gain factor Linear (triode) region: V ds < = V gs V tn I dsn = β n *[(V gs V tn ) V ds /]*V ds 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic
5 VoltageCurrent Relation: Linear Mode For longchannel devices (L >. micron) When V V V T I = k n W/L [(V V T )V V /] where k n = µ n C ox = µ n ε ox /t ox = is the process transconductance parameter (µ n is the carrier mobility (m /Vsec)) k n = k n W/L is the gain factor of the device For small V, there is a linear dependence between V and I, hence the name resistive or linear region Transistor in aturation Mode Assuming V > V T V V  V  V + T I Pinchoff V > V  V T The current remains constant (saturates). 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic 6 VoltageCurrent Relation: aturation Mode For long channel devices When V V V T I = k n / W/L [(V V T ) ] since the voltage difference over the induced channel (from the pinchoff point to the source) remains fixed at V V T However, the effective length of the conductive channel is modulated by the applied V, so I = I ( + λv ) where λ is the channellength modulation (varies with the inverse of the channel length) Current eterminates For a fixed V and V (> V T ), I is a function of the distance between the source and drain L the channel width W the threshold voltage V T the thickness of the io t ox the dielectric of the gate insulator (io ) ε ox the carrier mobility for nfets: µ n = cm /Vsec for pfets: µ p = 8 cm /Vsec 9// VLI esign I; A. Milenkovic 7 9// VLI esign I; A. Milenkovic 8 cutoff I Long Channel IV Plot (NMO) X  6 V = V  V T V =.V V =.V Linear aturation V =.V V =.V... V (V) NMO transistor,.um, L d = um, W/L =., V =.V, V T =.V 9// VLI esign I; A. Milenkovic 9 Quadratic dependence υ n (m/s) hort Channel Effects ehavior of short channel device mainly due to Constant mobility (slope = µ) υ sat = Constant velocity ξ c =. ξ(v/µm) Velocity saturation the velocity of the carriers saturates due to scattering (collisions suffered by the carriers) For an NMO device with L of.µm, only a couple of volts difference between and are needed to reach velocity saturation 9// VLI esign I; A. Milenkovic
6 VoltageCurrent Relation: Velocity aturation Velocity aturation Effects For short channel devices Linear: When V V V T I = κ(v ) k n W/L [(V V T )V V /] where κ(v) = /( + (V/ξ c L)) is a measure of the degree of velocity saturation Long V = V V AT V V T channel devices hort channel devices For short channel devices and large enough V V T V AT < V V T so the device enters saturation before V reaches V V T and operates more often in saturation aturation: When V = V AT V V T I at = κ(v AT ) k n W/L [(V V T )V AT V AT /] I AT has a linear dependence wrt V so a reduced amount of current is delivered for a given control voltage 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic hort Channel IV Plot (NMO) MO I V Characteristics I... X  Linear Early Velocity aturation aturation V =.V V =.V V =.V V =.V... V (V) NMO transistor,.um, L d =.um, W/L =., V =.V, V T =.V Linear dependence I 6 X  longchannel quadratic shortchannel linear... V (V) (for V =.V, W/L =.) Linear (shortchannel) versus quadratic (longchannel) dependence of I on V in saturation Velocitysaturation causes the shortchannel device to saturate at substantially smaller values of V resulting in a substantial drop in current drive 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic hort Channel IV Plot (PMO) All polarities of all voltages and currents are reversed  V (V)  V = .V V = .V V = .V V = .V  X  PMO transistor,.um, L d =.um, W/L =., V =.V, V T = .V 9// VLI esign I; A. Milenkovic I The MO Currentource Model I I = for V V T I = k W/L [(V V T )V min V min /](+ λv ) for V V T with V min = min(v V T, V, V AT ) and V T = V  V T etermined by the voltages at the four terminals and a set of five device parameters V T (V) γ(v. ) V AT (V) k (A/V ) λ(v  ) NMO...6 x 6.6 PMO x // VLI esign I; A. Milenkovic 6
7 R eq (Ohm) x 7 6 The Transistor Modeled as a witch V V T R on... V (V) (for V = V, V = V V /) V (V) NMO(kΩ) PMO (kω). 9 9// VLI esign I; A. Milenkovic 7 Modeled as a switch with infinite off resistance and a finite on resistance, R on 8 Resistance inversely proportional to W/L (doubling W halves R on ) For V >>V T +V AT /, R on independent of V Once V approaches V T, R on increases dramatically. R on (for W/L = ) For larger devices divide R eq by W/L Other (ubmicon) MO Transistor Concerns Velocity saturation ubthreshold conduction Transistor is already partially conducting for voltages below VT Threshold variations In longchannel devices, the threshold is a function of the length (for low V) In shortchannel devices, there is a draininduced threshold barrier lowering at the upper end of the V range (for low L) Parasitic resistances resistances associated with the source and drain contacts Latchup R R 9// VLI esign I; A. Milenkovic 8 ubthreshold Conductance ubthreshold I vs V  I  ubthreshold exponential region V T Quadratic region Linear region... V (V) I ~ I e (qv /nkt) where n Transition from ON to OFF is gradual (decays exponentially) Current rolloff (slope factor) is also affected by increase in temperature = n (kt /q) ln () (typical values 6 to mv/decade) Has repercussions in dynamic circuits and for power consumption I = I e (qv /nkt) (  e (qv /kt) )( + λv ) V from to.v 9// VLI esign I; A. Milenkovic 9 9// VLI esign I; A. Milenkovic ubthreshold I vs V Threshold Variations I = I e (qv /nkt) (  e (qv /kt) )( + λv ) V T V T V from to.v Longchannel threshold Low V threshold Threshold as a function of the length (for low V ) L V raininduced barrier lowering (for low L) 9// VLI esign I; A. Milenkovic 9// VLI esign I; A. Milenkovic
8 Next Time: The CMO Inverter V V in V out C L 9// VLI esign I; A. Milenkovic
VLSI Design I; A. Milenkovic 1
Review: implified CMO Inverter Process CPE/EE 7, CPE 7 VLI esign I L: MO Transistor cut line epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic (
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