Lecture 7 - PN Junction and MOS Electrostatics (IV) Electrostatics of Metal-Oxide-Semiconductor Structure. September 29, 2005
|
|
- Claude Miller
- 6 years ago
- Views:
Transcription
1 Microelectronic Devices and Circuits - Fall 25 Lecture 7-1 Lecture 7 - PN Junction and MOS Electrostatics (IV) Electrostatics of Metal-Oide-Semiconductor Structure September 29, 25 Contents: 1. Introduction to MOS structure 2. Electrostatics of MOS at zero bias 3. Electrostatics of MOS under bias Reading assignment: Howe and Sodini, Ch. 3,
2 Microelectronic Devices and Circuits - Fall 25 Lecture 7-2 Key questions What is the big deal about the metal-oide-semiconductor structure? What do the electrostatics of the MOS structure look like at zero bias? How do the electrostatics of the MOS structure get modified if a voltage is applied across its terminals?
3 Microelectronic Devices and Circuits - Fall 25 Lecture Introduction Metal-Oide-Semiconductor structure: gate oide ε o = 3.9 ε o metal interconnect to gate n + polysilicon gate p-type ε s = 11.7 ε o metal interconnect to bulk MOS at the heart of the electronics revolution: Digital and analog functions: Metal-Oide-Semiconductor Field-Effect Transistor (MOSFET) is key element of Complementary Metal-Oide-Semiconductor (CMOS) circuit family Memory function: Dynamic Random Access Memory (DRAM) and Flash Erasable Programmable Memory (EPROM) Imaging: Charge-Couple Device (CCD) camera Displays: Active-Matri Liquid-Crystal Displays...
4 Microelectronic Devices and Circuits - Fall 25 Lecture MOS electrostatics at zero bias Idealized 1D structure: "metal" (n+ polysi) contact oide semiconductor (p type) contact -to Metal: does not tolerate volume charge charge can only eist at its surface Oide: insulator no volume charge (no free carriers, no dopants) Semiconductor: can have volume charge (SCR) Thermal equilibrium can t be established through oide; need wire to allow transfer of charge between metal and semiconductor. MOS structure: sandwich of dissimilar materials carrier transfer space-charge region at zero bias built-in potential
5 Microelectronic Devices and Circuits - Fall 25 Lecture 7-5 For most metals on p-si, equilibrium achieved by electrons diffusing from metal to semiconductor and holes from semiconductor to metal: log po, no po Na no ni 2 Na -to do Remember: n o p o = n 2 i Fewer holes near Si/SiO 2 interface ionized acceptors eposed (volume space charge)
6 Microelectronic Devices and Circuits - Fall 25 Lecture 7-6 Space charge density log po, no Na po no ni 2 Na -to do ρ ο QG -to do -qna In semiconductor: space-charge region close to Si/SiO 2 interface can do depletion approimation In metal: sheet of charge at metal/sio 2 interface Overall charge neutrality t o ρ o () =Q G δ( t o ) t o << ρ o () = < < do ρ o () = qn a do < ρ o () =
7 Microelectronic Devices and Circuits - Fall 25 Lecture 7-7 Electric field Integrate Gauss equation: E o ( 2 ) E o ( 1 )= 1 ɛ 2 1 ρ o ()d At interface between oide and semiconductor: change in permittivity change in electric field ɛ o E o = ɛ s E s E o E s = ɛ s ɛ o 3 E Eo Es
8 Microelectronic Devices and Circuits - Fall 25 Lecture 7-8 Start integrating from deep inside semiconductor: ρ ο -to do -qna Eο Eo Es -to do do < E o () = < < do E o () = qn a ɛ s ( do ) t o << E o () = ɛ s ɛ o E o ( = + )= qn a do ɛ o < t o E o () =
9 Microelectronic Devices and Circuits - Fall 25 Lecture 7-9 Electrostatic potential (with φ =@n o = p o = n i ) φ = kt q ln n o n i φ = kt q ln p o n i In QNR s, n o and p o known can determine φ: in n + gate: n o = N + d φ g = φ n + in p-qnr: p o = N a φ p = kt q ln N a n i φο φn+ φ B -to do φp Built-in potential: φ B = φ g φ p = φ n + + kt q ln N a n i
10 Microelectronic Devices and Circuits - Fall 25 Lecture 7-1 To get φ o (), integrate E o (); start from deep inside semiconductor bulk: φ o ( 2 ) φ o ( 1 )= 2 1 E o ()d Eο Eo Es -to do φο φn+ φb -to do Vo,o VB,o φp do < φ o () =φ p < < d φ o () =φ p + qn a 2ɛ s ( do ) 2 t o << φ o () =φ p + qn a 2 do 2ɛ s + qn a do ( ) ɛ o < t o φ o () =φ n +
11 Microelectronic Devices and Circuits - Fall 25 Lecture 7-11 Still don t know do need one more equation: Potential difference across structure has to add up to φ B : φ B = V B,o + V o,o = qn a 2 do 2ɛ s + qn a do t o ɛ o Solve quadratic equation: do = ɛ s t o [ 1+ 2ɛ2 oφ B ɛ o ɛ s qn a t 2 o 1] = ɛ s [ 1+ 4φ B C o γ 1] 2 where C o is capacitance per unit area of oide [units: F/cm 2 ]: C o = ɛ o t o and γ is body factor coefficient [units: V 1/2 ]: γ = 1 2ɛs qn a C o
12 Microelectronic Devices and Circuits - Fall 25 Lecture 7-12 Numerical eample: N d =1 2 cm 3,N a =1 17 cm 3,t o =8nm φ B = 55 mv + 42 mv = 97 mv C o = F/cm 2 γ =.43 V 1/2 do =91nm
13 Microelectronic Devices and Circuits - Fall 25 Lecture 7-13 There are also contact potentials total contact-to-contact potential difference is zero! "metal" contact oide semiconductor (p type) contact φο φn+ φb -to do φp
14 Microelectronic Devices and Circuits - Fall 25 Lecture MOS electrostatics under bias Apply voltage to gate with respect to semiconductor: "metal" (n+ polysi) VGB + - contact oide semiconductor (p type) contact -to Electrostatics of MOS structure affected potential difference across entire structure now. How is potential difference accommodated? Potential can drop in: gate contact n + -polysilicon gate oide semiconductor SCR semiconductor QNR semiconductor contact
15 Microelectronic Devices and Circuits - Fall 25 Lecture 7-15 Potential difference shows up across oide and SCR in semiconductor: φ V GB -t o? do φ B φ B +V GB Oide is insulator no current anywhere in structure In SCR, quasi-equilibrium situation prevails new balance between drift and diffusion electrostatics qualitatively identical to zero bias (but amount of charge redistribution is different) np = n 2 i
16 Microelectronic Devices and Circuits - Fall 25 Lecture 7-16 Apply V GB > : potential difference across structure increases need larger charge dipole SCR epands into semiconductor substrate: ρ -to d -qna E Eo Es -to d φ VGB= VGB> φb+vgb φb -to d log p, n Na p n ni 2 Na -to d Simple way to remember: with V GB >, gate attracts electrons and repels holes.
17 Microelectronic Devices and Circuits - Fall 25 Lecture 7-17 Qualitatively, physics unchanged by applying V GB >. Use mathematical formulation of zero bias, but: φ B φ B + V GB For eample, d (V GB )= ɛ s [ 1+ 4(φ B + V GB ) 1] C o γ 2 V GB d
18 Microelectronic Devices and Circuits - Fall 25 Lecture 7-18 Key conclusions Charge redistribution in MOS structure at zero bias: SCR in semiconductor built-in potential across MOS structure. In most cases, can do depletion approimation in semiconductor SCR. Application of voltage modulates depletion region width in semiconductor. No current flows.
Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure
Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with
More informationLecture 8 PN Junction and MOS Electrostatics (V) Electrostatics of Metal Oxide Semiconductor Structure (cont.) October 4, 2005
6.12 Microelectronic Devices and Circuits Fall 25 Lecture 8 1 Lecture 8 PN Junction and MOS Electrostatics (V) Electrostatics of Metal Oide Semiconductor Structure (cont.) Contents: October 4, 25 1. Overview
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More informationLecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)
Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Outline 1. Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime
More informationLecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium September 20, 2005
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 4-1 Contents: Lecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium September 20, 2005
More informationElectrical Characteristics of MOS Devices
Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage
More informationLecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium. February 13, 2003
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 4-1 Contents: Lecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium February 13, 2003
More informationWeek 3, Lectures 6-8, Jan 29 Feb 2, 2001
Week 3, Lectures 6-8, Jan 29 Feb 2, 2001 EECS 105 Microelectronics Devices and Circuits, Spring 2001 Andrew R. Neureuther Topics: M: Charge density, electric field, and potential; W: Capacitance of pn
More informationLecture 15 - The pn Junction Diode (I) I-V Characteristics. November 1, 2005
6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 15-1 Lecture 15 - The pn Junction Diode (I) I-V Characteristics November 1, 2005 Contents: 1. pn junction under bias 2. I-V characteristics
More informationFIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationLecture 6 - PN Junction and MOS Electrostatics (III) Electrostatics of pn Junction under Bias February 27, 2001
6.012 Microelectronic Devices and Circuits Spring 2001 Lecture 61 Lecture 6 PN Junction and MOS Electrostatics (III) Electrostatics of pn Junction under Bias February 27, 2001 Contents: 1. electrostatics
More informationLecture 13 - Carrier Flow (cont.), Metal-Semiconductor Junction. October 2, 2002
6.72J/3.43J - Integrated Microelectronic Devices - Fall 22 Lecture 13-1 Contents: Lecture 13 - Carrier Flow (cont.), Metal-Semiconductor Junction October 2, 22 1. Transport in space-charge and high-resistivity
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationLecture 17 - p-n Junction. October 11, Ideal p-n junction in equilibrium 2. Ideal p-n junction out of equilibrium
6.72J/3.43J - Integrated Microelectronic Devices - Fall 22 Lecture 17-1 Lecture 17 - p-n Junction October 11, 22 Contents: 1. Ideal p-n junction in equilibrium 2. Ideal p-n junction out of equilibrium
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationMicroelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 -
6.012 - Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - Posted on Stellar. Due net Wednesday. Qualitative description - MOS in thermal equilibrium
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
More informationEE105 - Spring 2007 Microelectronic Devices and Circuits. Structure and Symbol of MOSFET. MOS Capacitor. Metal-Oxide-Semiconductor (MOS) Capacitor
EE105 - Spring 007 Microelectronic Device and ircuit Metal-Oide-Semiconductor (MOS) apacitor Lecture 4 MOS apacitor The MOS tructure can be thought of a a parallel-plate capacitor, with the top plate being
More informationLecture 16 The pn Junction Diode (III)
Lecture 16 The pn Junction iode (III) Outline I V Characteristics (Review) Small signal equivalent circuit model Carrier charge storage iffusion capacitance Reading Assignment: Howe and Sodini; Chapter
More informationChoice of V t and Gate Doping Type
Choice of V t and Gate Doping Type To make circuit design easier, it is routine to set V t at a small positive value, e.g., 0.4 V, so that, at V g = 0, the transistor does not have an inversion layer and
More informationLecture 7 - Carrier Drift and Diffusion (cont.) February 20, Non-uniformly doped semiconductor in thermal equilibrium
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 7-1 Lecture 7 - Carrier Drift and Diffusion (cont.) February 20, 2007 Contents: 1. Non-uniformly doped semiconductor in thermal equilibrium
More informationLecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)
Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationLecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 16-1 Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model April 8, 2003 Contents: 1. I-V characteristics (cont.) 2. Small-signal
More informationan introduction to Semiconductor Devices
an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor -
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/18/2007 P Junctions Lecture 1 Reading: Chapter 5 Announcements For THIS WEEK OLY, Prof. Javey's office hours will be held on Tuesday, Sept 18 3:30-4:30
More informationFundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationElectronic Devices and Circuits Lecture 5 - p-n Junction Injection and Flow - Outline
6.012 - Electronic Devices and Circuits Lecture 5 - p-n Junction Injection and Flow - Outline Review Depletion approimation for an abrupt p-n junction Depletion charge storage and depletion capacitance
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationLecture 8 - Carrier Drift and Diffusion (cont.) September 21, 2001
6.720J/3.43J - Integrated Microelectronic Devices - Fall 2001 Lecture 8-1 Lecture 8 - Carrier Drift and Diffusion (cont.) September 21, 2001 Contents: 1. Non-uniformly doped semiconductor in thermal equilibrium
More informationSemiconductor Junctions
8 Semiconductor Junctions Almost all solar cells contain junctions between different materials of different doping. Since these junctions are crucial to the operation of the solar cell, we will discuss
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm 2 Name: SID: Closed book. Two sheets of notes are
More informationLecture Notes 2 Charge-Coupled Devices (CCDs) Part I. Basic CCD Operation CCD Image Sensor Architectures Static and Dynamic Analysis
Lecture Notes 2 Charge-Coupled Devices (CCDs) Part I Basic CCD Operation CCD Image Sensor Architectures Static and Dynamic Analysis Charge Well Capacity Buried channel CCD Transfer Efficiency Readout Speed
More informationSemiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5
Semiconductor Devices C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Global leader in environmental and industrial measurement Wednesday 3.2. afternoon Tour around facilities & lecture
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation
More informationECE 340 Lecture 39 : MOS Capacitor II
ECE 340 Lecture 39 : MOS Capacitor II Class Outline: Effects of Real Surfaces Threshold Voltage MOS Capacitance-Voltage Analysis Things you should know when you leave Key Questions What are the effects
More informationThe Three terminal MOS structure. Semiconductor Devices: Operation and Modeling 115
The Three terminal MOS structure 115 Introduction MOS transistor two terminal MOS with another two opposite terminal (back to back of inversion layer). Theses two new terminal make the current flow if
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at
More informationLecture 22 Field-Effect Devices: The MOS Capacitor
Lecture 22 Field-Effect Devices: The MOS Capacitor F. Cerrina Electrical and Computer Engineering University of Wisconsin Madison Click here for link to F.C. homepage Spring 1999 0 Madison, 1999-II Topics
More information1 cover it in more detail right away, 2 indicate when it will be covered in detail, or. 3 invite you to office hours.
14 1 8 6 IBM ES9 Bipolar Fujitsu VP IBM 39S Pulsar 4 IBM 39 IBM RY6 CDC Cyber 5 IBM 4381 IBM RY4 IBM 381 Apache Fujitsu M38 IBM 37 Merced IBM 36 IBM 333 Vacuum Pentium II(DSIP) 195 196 197 198 199 NTT
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationECE321 Electronics I
ECE321 Electronics I Lecture 4: Physics of Semiconductor iodes Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: pzarkesh.unm.edu Slide: 1 Review of Last
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationEE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions
EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 pn Junction p-type semiconductor in
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 217 MOS Transistor Theory, MOS Model Lecture Outline! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff
More informationLecture 7 MOS Capacitor
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 7 MOS Capacitor Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030
More informationLecture 3 Semiconductor Physics (II) Carrier Transport
Lecture 3 Semiconductor Physics (II) Carrier Transport Thermal Motion Carrier Drift Carrier Diffusion Outline Reading Assignment: Howe and Sodini; Chapter 2, Sect. 2.4-2.6 6.012 Spring 2009 Lecture 3 1
More informationn N D n p = n i p N A
Summary of electron and hole concentration in semiconductors Intrinsic semiconductor: E G n kt i = pi = N e 2 0 Donor-doped semiconductor: n N D where N D is the concentration of donor impurity Acceptor-doped
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 6: September 14, 2015 MOS Model You are Here: Transistor Edition! Previously: simple models (0 and 1 st order) " Comfortable
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationV BI. H. Föll: kiel.de/matwis/amat/semi_en/kap_2/backbone/r2_2_4.html. different electrochemical potentials (i.e.
Consider the the band diagram for a homojunction, formed when two bits of the same type of semicondutor (e.g. Si) are doped p and ntype and then brought into contact. Electrons in the two bits have different
More informationLong-channel MOSFET IV Corrections
Long-channel MOSFET IV orrections Three MITs of the Day The body ect and its influence on long-channel V th. Long-channel subthreshold conduction and control (subthreshold slope S) Scattering components
More informationClassification of Solids
Classification of Solids Classification by conductivity, which is related to the band structure: (Filled bands are shown dark; D(E) = Density of states) Class Electron Density Density of States D(E) Examples
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationCharge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn )
The Inverted MO Capacitor (V > V Tn ) We consider the surface potential as Þxed (ÒpinnedÓ) at φ s,max = - φ p φ(x).5 V. V V ox Charge torage in the MO tructure Three regions of operation: Accumulation:
More informationLecture 19 - p-n Junction (cont.) October 18, Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode: parasitics, dynamics
6.720J/3.43J - Integrated Microelectronic Devices - Fall 2002 Lecture 19-1 Lecture 19 - p-n Junction (cont.) October 18, 2002 Contents: 1. Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode:
More informationECE 440 Lecture 20 : PN Junction Electrostatics II Class Outline:
ECE 440 Lecture 20 : PN Junction Electrostatics II Class Outline: Depletion Approximation Step Junction Things you should know when you leave Key Questions What is the space charge region? What are the
More informationCHAPTER 5 MOS FIELD-EFFECT TRANSISTORS
CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancement-type N-MOS transistor 5.3 I-V characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More information! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)
ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationChapter 7. The pn Junction
Chapter 7 The pn Junction Chapter 7 PN Junction PN junction can be fabricated by implanting or diffusing donors into a P-type substrate such that a layer of semiconductor is converted into N type. Converting
More informationSolid State Electronics. Final Examination
The University of Toledo EECS:4400/5400/7400 Solid State Electronic Section elssf08fs.fm - 1 Solid State Electronics Final Examination Problems Points 1. 1. 14 3. 14 Total 40 Was the exam fair? yes no
More informationSchottky Rectifiers Zheng Yang (ERF 3017,
ECE442 Power Semiconductor Devices and Integrated Circuits Schottky Rectifiers Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Schottky Rectifier Structure 2 Metal-Semiconductor Contact The work function
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 6: September 18, 2017 MOS Model You are Here: Transistor Edition! Previously: simple models (0 and 1 st order) " Comfortable
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More information1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00
1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.
More informationSemiconductor Physics fall 2012 problems
Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each
More informationLecture 22 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) April 2, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 22-1 Lecture 22 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) April 2, 2007 Contents: 1. Ideal MOS structure
More informationConsider a uniformly doped PN junction, in which one region of the semiconductor is uniformly doped with acceptor atoms and the adjacent region is
CHAPTER 7 The PN Junction Consider a uniformly doped PN junction, in which one region of the semiconductor is uniformly doped with acceptor atoms and the adjacent region is uniformly doped with donor atoms.
More informationPN Junction. Ang M.S. October 8, Maxwell s Eqautions Review : Poisson s Equation for PNJ. Q encl S. E ds. σ = dq ds. ρdv = Q encl.
PN Junction Ang M.S. October 8, 0 Reference Sedra / Smith, M icroelectronic Circuits Maxwell s Eqautions Review : Poisson s Equation for PNJ. Gauss Law for E field The total enclosed charge Q encl. insde
More informationLecture 20 - p-n Junction (cont.) October 21, Non-ideal and second-order effects
6.70J/3.43J - Integrated Microelectronic Devices - Fall 00 Lecture 0-1 Lecture 0 - p-n Junction (cont.) October 1, 00 Contents: 1. Non-ideal and second-order effects Reading assignment: del Alamo, Ch.
More informationOperation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS
Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2
More informationECE321 Electronics I
EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman Zarkesh-Ha Office: EE Bldg. 3B Office hours: Tuesday :-3:PM or by appointment E-mail: payman@ece.unm.edu Slide: 1
More informationFor the following statements, mark ( ) for true statement and (X) for wrong statement and correct it.
Benha University Faculty of Engineering Shoubra Electrical Engineering Department First Year communications. Answer all the following questions Illustrate your answers with sketches when necessary. The
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More information! Previously: simple models (0 and 1 st order) " Comfortable with basic functions and circuits. ! This week and next (4 lectures)
ESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems Lec 6: September 14, 2015 MOS Model You are Here: Transistor Edition! Previously: simple models (0 and 1 st order) " Comfortable
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationSemiconductor Integrated Process Design (MS 635)
Semiconductor Integrated Process Design (MS 635) Instructor: Prof. Keon Jae Lee - Office: 응용공학동 #4306, Tel: #3343 - Email: keonlee@kaist.ac.kr Lecture: (Tu, Th), 1:00-2:15 #2425 Office hour: Tues & Thur
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time
More informationLecture 17 The Bipolar Junction Transistor (I) Forward Active Regime
Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Outline The Bipolar Junction Transistor (BJT): structure and basic operation I V characteristics in forward active regime Reading Assignment:
More informationDevices. chapter Introduction. 1.2 Silicon Conductivity
chapter 1 Devices 1.1 Introduction The properties and performance of analog bicmos integrated circuits are dependent on the devices used to construct them. This chapter is a review of the operation of
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors. Fabrication of semiconductor sensor
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Fabrication of semiconductor sensor
More informationLecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 17-1 Lecture 17 - The Bipolar Junction Transistor (I) Contents: Forward Active Regime April 10, 2003 1. BJT: structure and basic operation
More information6.152J / 3.155J Spring 05 Lecture 08-- IC Lab Testing. IC Lab Testing. Outline. Structures to be Characterized. Sheet Resistance, N-square Resistor
IC Lab Testing Review Process Outline Structures to be Characterized Resistors Sheet Resistance, Nsquare Resistor MOS Capacitors Flatband Voltage, Threshold Voltage, Oxide Thickness, Oxide Charges, Substrate
More informationEE 3329 Electronic Devices Syllabus ( Extended Play )
EE 3329 - Electronic Devices Syllabus EE 3329 Electronic Devices Syllabus ( Extended Play ) The University of Texas at El Paso The following concepts can be part of the syllabus for the Electronic Devices
More information! Previously: simple models (0 and 1 st order) " Comfortable with basic functions and circuits. ! This week and next (4 lectures)
ESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems Lec 6: September 18, 2017 MOS Model You are Here: Transistor Edition! Previously: simple models (0 and 1 st order) " Comfortable
More information