Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:


 Wesley Stewart
 1 years ago
 Views:
Transcription
1 Serial : ND_EE_NW_Analog Electronics_05088 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: Ph: CLASS TEST 089 ELECTCAL ENGNEENG Subject : Analog Electronics Date of test : 05/08/08 Answer Key. (d) 7. (a) 3. (c) 9. (d) 5. (b). (a) 8. (a) 4. (c) 0. (a) 6. (d) 3. (b) 9. (b) 5. (b). (c) 7. (d) 4. (b) 0. (b) 6. (a). (b) 8. (a) 5. (a). (d) 7. (a) 3. (a) 9. (a) 6. (c). (c) 8. (c) 4. (a) 30. (b)
2 CT08 EE Analog Electronics 9 Detailed Explanations. (d) The given configuration is a current shunt feedback configuration. So, the input impedance decreases. (a) i if KA and the output impedance increases, of 0 ( KA i ) 3. (b) KCL at node V V V V0 0 V V V 0 V ( V V 0 ) V V ( ) 4. (b) For maximum power dissipation in Zener diode the current through the Zener diode should be maximum Therefore L value should be largest. Ω i S L 0 V Z 0 V L The maximum power dissipation in Zener diode is equal to power rating of the Zener diode. So P max 400 mw Thus z mw z 40 ma Now, s ma So L S z ma So L 0 V.98k Ω L 5. (a) Analyzing the circuit we observed that current is being sampled and current is being mixed. Thus, it is shuntseries feedback.
3 0 Electrical Engineering 6. (c) The given circuit is a potential divider/self biasing. B Stabilibity for self biasing circuit is given by: ( ) B β E S β B E For better stability S should be minimum B So, << E 7. (a) So β(forced) 0 C B 0 B ma The power dissipated in the transistor is P B V BE(on) C V CE(sat) ( ) (0.7) ( 0 3 ) (0.) P.8 mw 8. (a) The output voltage of an opamp integrator is t t VC V () t dt C 0 i ( ) dt C t t 0 C 0 t C At t ms, We want 0 V 9. (b) 0 Which means the time constant is 3 0 C τ C 0. ms Si max V Si kω kω k k kω V V D.7 V 0.7 V V max V kω ma
4 CT08 EE Analog Electronics 0. (b) During positive half cycle n kω kω kω this circuit can be redrawn as, n kω kω kω according to voltage division rule ( Vin )k Ω kω 5 sin ω 0 t this is during positive half cycle. Similarly during negative half cycle 5 sin ω 0 t n kω kω kω. (d) 5 sin ω 0 t 5 kω, 8 kω TH kω V TH ( 4) 5.8 V Thus the circuit is as follows 4 V 3 kω 5.8 V 6.06 kω kω
5 Electrical Engineering 5.8 (6.06 k) ( BQ ) V BE (β ) B ( k) (6.06 k 76 k) BQ BQ 6.4 µa EQ (β ) BQ 4.74 ma CQ β BQ 4.68 ma V CEQ 4 CQ C EQ E 4 (4.68) (3) (4.74) () 5. V. (c) As we know that for proper operation V DS V GS V T V D V S V G V S V T 5 V 5 V 5 V 5 V V D V G V T P Q at P V D V G V T Given V G for all transistor 5 V and V T for all transistors V V D at P V G V T 5 4 V V D at Q V G V T 5 4 V V D at V G V T 5 4 V According to the given options the only condition satisfied for the voltages at P, Q and is only option (c). 3. (c) When early affect is considered then the C  V CE plot is approximated by a straight line so from the given data we get slope of line equal to ma / V 0 So the equation of the straight line (relation between C  V CE ) C V CE 0 CmA value of C can be found by putting (.8 ma, V) in the above equation, V CE Hence, C.7 ma 0 Early voltage is the magnitude of value of V CE where C 0 So from above equation we get V A 34 V 4. (c) With all the parameter we draw the small signal model of the circuit, then we will find equivalent resistance seen across the capacitor. The cut off frequency will be π C eq The small signal model is
6 CT08 EE Analog Electronics 3 gmvbe 0 kω kω 0 kω V be r e r π β kω C 5 µ F The base resistance when seen from emitter get multiplied with. ( β ) So, eq r 0k k ( k ) π Ω Ω Ω β β eq (000) (6.40) 6.05 Ω So, f 97 Hz π C eq 5. (b) Since input impedance i 00 kω for 0 i 00 kω For the circuit shown is given by For 4 0, kω and For 4 0 kω, 0 or, 0 or,
7 4 Electrical Engineering or, 3. kω Hence, for potentiometer in the middle is ( 4 5 kω when potentiometer is set at its centre) or, (a) n the above circuit c B, B Applying KVL in the circuit, we get: (3 kω) (0 kω 68 kω) 0.7 or, (3K) (88 K).3 or, (9K) B (3K) C.3 or, C.58 ma 0 kω 68 kω 0.0µ F V 3 kω Thus, c.58 ma and E β C.60 β ma V T 6 r e 0 Ω and r.60 π βr e.4 kω E The small signal model of the given circuit for calculating the gain is shown below. 0 kω B i B C r π βi B r 0 E 68 kω 3 kω From the above circuit, i B V r π i or, and i B V O βi B (30 kω 68 kω 3 kω) i B ( ) i B So, A V V0 V i ( ) ib ib A V (a) n the circuit given below, ma 5 k
8 CT08 EE Analog Electronics ma.8k V 5 kω C 0 A C Q Q B.8 kω B KCL at node A C B C β C from here C since the circuit is current mirror circuit ma 8. (c) C C ma V kω kω 4 kω 8 kω V kω 7 kω The output of st opamp is represented by V o and output of second opamp is represented by V o. 8 8 So, V o V o 4 4 Vo 3...(i) and V o V o 8
9 6 Electrical Engineering 3 Vo...(ii) 8 Put the value of V o in equation (i), we get 3V V o o 3 8 3V o 6 4 4V o 3V o 8 7V o 8 V o 4 V 9. (d) We can write the dc drain current as 3V o D Q V 0.8 ma D ( 9) which yields V D 5.8 V Now, assume the transistor is biased in the saturation region. We then have D D V GS DSS VP 0.8 V GS.5.5 V GS.086 V Then V S V GS V V SD V S V D (5.8) 5.7 V 0. (a) kω ma kω x kω V Apply KCL at node V O, we get 0 3 x ( 0 ) ma
10 CT08 EE Analog Electronics 7. (c) To begin initially we assume both diode D and D are in their conducting state. Node equations at V A and V B are and ( V ) 5 B V A 0 D V A D 5 V B 0 We note that V B V A 0.7 Combining equations (i) and (ii) we find V A 7.6 V and V B 6.9 V Substituting this values in equation () D D ma Negative diode current shows that our assumption is wrong. Now assuming the diode D is off and D is on. V A V 0 V B (5 0.7) 9.53 V 0 5 The voltages shows that diode D is indeed reverse biased so D 0....(i)...(ii). (b) nitially assume each diode is in its conduction state. Starting with D 3 and considering the voltages, we see that V B 0.7 V and V A 0 KCL at node V A : V 5 ( 0.7) 0 A VA D 0 5K 5K Since V A D ma 5 0 which is inconsistent with the assumption that all diodes are on (an on diode would have a positive diode current). Now assume D and D 3 are on and D is off ( 0) D 5K 5K D.43 ma V A 5 ( ) (5 0 3 ).5 V
11 8 Electrical Engineering 3. (a) The given circuit is a current mirror circuit in which the output current is a mirror image of the input current if both the transistors are identical. i 9.3 kω 0 Q ( 700) β Q ( 75) β 4. (a) 0 V To calculate i, 9.3 i (0) 0 i ma Since the emitter area of transistor Q is half that of transistor Q, So i 0 /. Therefore, 0 ma V0 () s V () s where, z (s) sc z (s) sl i Z() s Z () s (s) LCs i V () s (t) Vm sin( ω0t) dt dt LC V m (t) sin( ω 0t) ω 0 5. (b) bias µ C W V V L n ox D ( ) GS T (V GS V T ) x C W L bias µ n ox µ C W V V L n ox D ( ) GS T...(i)...(ii)
12 CT08 EE Analog Electronics 9 Substituting the value of (V GS V T ) in equation (ii) x µ n Cox W bias L W n C µ ox L x bias 6. (d) Consider D OFF and D ON then Applying KVL in the outer most loop: 0 (00) ma now we calculate V D (9.5 0 )( 0 ) VD 0 V kω 0 Ω V D 0.3 V D 0.5 V since V D < 0.7 V, D is in OFF state i.e. our assumption is correct and hence (d) is correct option. 7. (d) G D V GS MΩ V g V m GS kω r 0 k d Ω z in MΩ z 0 r d D 0 k z 0 0 k Ω 8. (a) The duty cycle of the above astable multivibrator is T % duty cycle ON 00 T A B 00 A B A A 66% > 50% So, duty cycle of the output wave is greater than 50%
13 0 Electrical Engineering 9. (a) When the switch is closed the opamp is in closed loop. Thus, virtual short concept is applicable and current through the capacitor will be 0 ma. i.e., i C (t) 0 0 ma kω v c (t) t () C i C tdt 0 t (0 ma) (0) or, v c (t) dt t F 0 0 Thus, the value of v c at t ms will be 0 V 30. (b) n a CE unbypass amplifier, A V C E 4k k
Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:
Serial : CH_EE_B_Network Theory_098 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubaneswar Kolkata Patna Web: Email: info@madeeasy.in Ph: 056 CLASS TEST 089 ELECTCAL ENGNEENG Subject : Network
More informationRIB. ELECTRICAL ENGINEERING Analog Electronics. 8 Electrical Engineering RIBR T7. Detailed Explanations. Rank Improvement Batch ANSWERS.
8 Electrical Engineering RIBR T7 Session 089 S.No. : 9078_LS RIB Rank Improvement Batch ELECTRICL ENGINEERING nalog Electronics NSWERS. (d) 7. (a) 3. (c) 9. (a) 5. (d). (d) 8. (c) 4. (c) 0. (c) 6. (b)
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationDC Biasing. Dr. U. Sezen & Dr. D. Gökçen (Hacettepe Uni.) ELE230 Electronics I 15Mar / 59
Contents Three States of Operation BJT DC Analysis FixedBias Circuit EmitterStabilized Bias Circuit Voltage Divider Bias Circuit DC Bias with Voltage Feedback Various Dierent Bias Circuits pnp Transistors
More informationChapter 2  DC Biasing  BJTs
Objectives Chapter 2  DC Biasing  BJTs To Understand: Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented
More informationHomework Assignment 09
Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationESE319 Introduction to Microelectronics. Output Stages
Output Stages Power amplifier classification Class A amplifier circuits Class A Power conversion efficiency Class B amplifier circuits Class B Power conversion efficiency Class AB amplifier circuits Class
More informationFinal Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.
Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the opamp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at
More informationDelhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:
Serial : LS_B_EC_Network Theory_0098 CLASS TEST (GATE) Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubanewar Kolkata Patna Web: Email: info@madeeay.in Ph: 04546 CLASS TEST 089 ELECTRONCS
More informationDelhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:
Serial : LS_N_A_Network Theory_098 Delhi Noida Bhopal Hyderabad Jaipur Lucknow ndore Pune Bhubanewar Kolkata Patna Web: Email: info@madeeay.in Ph: 04546 CLASS TEST 089 NSTRUMENTATON ENGNEERNG Subject
More informationECE343 Test 2: Mar 21, :008:00, Closed Book. Name : SOLUTION
ECE343 Test 2: Mar 21, 2012 6:008:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
More informationBipolar Junction Transistor (BJT)  Introduction
Bipolar Junction Transistor (BJT)  Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification
More information55:041 Electronic Circuits The University of Iowa Fall Final Exam
Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a classb amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered
More informationCircle the one best answer for each question. Five points per question.
ID # NAME EE255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions
More informationChapter 2.  DC Biasing  BJTs
Chapter 2.  DC Biasing  BJTs Objectives To Understand : Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented
More informationECE342 Test 3: Nov 30, :008:00, Closed Book. Name : Solution
ECE342 Test 3: Nov 30, 2010 6:008:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown
More informationDEPARTMENT OF ECE UNIT VII BIASING & STABILIZATION AMPLIFIER:
UNIT VII IASING & STAILIZATION AMPLIFIE:  A circuit that increases the amplitude of given signal is an amplifier  Small ac signal applied to an amplifier is obtained as large a.c. signal of same frequency
More informationCHAPTER.4: Transistor at low frequencies
CHAPTER.4: Transistor at low frequencies Introduction Amplification in the AC domain BJT transistor modeling The re Transistor Model The Hybrid equivalent Model Introduction There are three models commonly
More informationEE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits
EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00
More informationChapter 3 Output stages
Chapter 3 utput stages 3.. Goals and properties 3.. Goals and properties deliver power into the load with good efficacy and small power dissipate on the final transistors small output impedance maximum
More information55:041 Electronic Circuits The University of Iowa Fall Exam 2
Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.
More informationID # NAME. EE255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom
ID # NAME EE255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.
More informationAt point G V = = = = = = RB B B. IN RB f
Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F
More informationESE319 Introduction to Microelectronics. BJT Biasing Cont.
BJT Biasing Cont. Biasing for DC Operating Point Stability BJT Bias Using Emitter Negative Feedback Single Supply BJT Bias Scheme Constant Current BJT Bias Scheme Rule of Thumb BJT Bias Design 1 Simple
More informationBiasing BJTs CHAPTER OBJECTIVES 4.1 INTRODUCTION
4 DC Biasing BJTs CHAPTER OBJECTIVES Be able to determine the dc levels for the variety of important BJT configurations. Understand how to measure the important voltage levels of a BJT transistor configuration
More informationAdvanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 WideSwing Current Mirrors I bias I V I in out out = I in V W L bias 
More informationEE 321 Analog Electronics, Fall 2013 Homework #8 solution
EE 321 Analog Electronics, Fall 2013 Homework #8 solution 5.110. The following table summarizes some of the basic attributes of a number of BJTs of different types, operating as amplifiers under various
More informationChapter 13 SmallSignal Modeling and Linear Amplification
Chapter 13 SmallSignal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 131 Chapter Goals Understanding of concepts related to: Transistors
More informationKOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU  Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II )
KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU  Control and Automation Dept. 1 4 DC BIASING BJTS (CONT D II ) Most of the content is from the textbook: Electronic devices and circuit theory,
More informationOperational amplifiers (Op amps)
Operational amplifiers (Op amps) v R o R i v i Av i v View it as an ideal amp. Take the properties to the extreme: R i, R o 0, A.?!?!?!?! v v i Av i v A Consequences: No voltage dividers at input or output.
More informationCARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130
ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED
More informationThe equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A =
The equivalent model of a certain op amp is shown in the figure given below, where R 1 = 2.8 MΩ, R 2 = 39 Ω, and A = 10 10 4. Section Break Difficulty: Easy Learning Objective: Understand how real operational
More informationElectronics II. Final Examination
The University of Toledo f17fs_elct27.fm 1 Electronics II Final Examination Problems Points 1. 11 2. 14 3. 15 Total 40 Was the exam fair? yes no The University of Toledo f17fs_elct27.fm 2 Problem 1 11
More informationElectronic Circuits Summary
Electronic Circuits Summary Andreas Biri, DITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent
More informationSolved Problems. Electric Circuits & Components. 11 Write the KVL equation for the circuit shown.
Solved Problems Electric Circuits & Components 11 Write the KVL equation for the circuit shown. 12 Write the KCL equation for the principal node shown. 12A In the DC circuit given in Fig. 1, find (i)
More informationECE137B Final Exam. There are 5 problems on this exam and you have 3 hours There are pages 119 in the exam: please make sure all are there.
ECE37B Final Exam There are 5 problems on this exam and you have 3 hours There are pages 9 in the exam: please make sure all are there. Do not open this exam until told to do so Show all work: Credit
More informationProblem Set 4 Solutions
University of California, Berkeley Spring 212 EE 42/1 Prof. A. Niknejad Problem Set 4 Solutions Please note that these are merely suggested solutions. Many of these problems can be approached in different
More informationECE 523/421  Analog Electronics University of New Mexico Solutions Homework 3
ECE 523/42  Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o
More informationCHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012
1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET DFET (Depletion MOS) MOSFET (Enhancement EFET) DC biasing Small signal
More informationE40M Review  Part 1
E40M Review Part 1 Topics in Part 1 (Today): KCL, KVL, Power Devices: V and I sources, R Nodal Analysis. Superposition Devices: Diodes, C, L Time Domain Diode, C, L Circuits Topics in Part 2 (Wed): MOSFETs,
More informationSeries & Parallel Resistors 3/17/2015 1
Series & Parallel Resistors 3/17/2015 1 Series Resistors & Voltage Division Consider the singleloop circuit as shown in figure. The two resistors are in series, since the same current i flows in both
More informationBipolar junction transistors
Bipolar junction transistors Find parameters of te BJT in CE configuration at BQ 40 µa and CBQ V. nput caracteristic B / µa 40 0 00 80 60 40 0 0 0, 0,5 0,3 0,35 0,4 BE / V Output caracteristics C / ma
More informationENGN3227 Analogue Electronics. Problem Sets V1.0. Dr. Salman Durrani
ENGN3227 Analogue Electronics Problem Sets V1.0 Dr. Salman Durrani November 2006 Copyright c 2006 by Salman Durrani. Problem Set List 1. Opamp Circuits 2. Differential Amplifiers 3. Comparator Circuits
More informationChapter 2. Engr228 Circuit Analysis. Dr Curtis Nelson
Chapter 2 Engr228 Circuit Analysis Dr Curtis Nelson Chapter 2 Objectives Understand symbols and behavior of the following circuit elements: Independent voltage and current sources; Dependent voltage and
More informationMicroelectronic Circuit Design 4th Edition Errata  Updated 4/4/14
Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: 1.35 x 10 6 cm/s Page 58, last exercise,
More informationGeneral Purpose Transistors
General Purpose Transistors NPN and PNP Silicon These transistors are designed for general purpose amplifier applications. They are housed in the SOT 33/SC which is designed for low power surface mount
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics Lena Peterson 20151013 Outline (1) Why is the CMOS inverter gain not infinite? Largesignal
More informationChapter 10 Instructor Notes
G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 hapter 10 nstructor Notes hapter 10 introduces bipolar junction transistors. The material on transistors has
More informationChapter 3. FET Amplifiers. Spring th Semester Mechatronics SZABIST, Karachi. Course Support
Chapter 3 Spring 2012 4 th Semester Mechatronics SZABIST, Karachi 2 Course Support humera.rafique@szabist.edu.pk Office: 100 Campus (404) Official: ZABdesk https://sites.google.com/site/zabistmechatronics/home/spring2012/ecd
More informationLecture 7: Transistors and Amplifiers
Lecture 7: Transistors and Amplifiers Hybrid Transistor Model for small AC : The previous model for a transistor used one parameter (β, the current gain) to describe the transistor. doesn't explain many
More informationMidterm Exam (closed book/notes) Tuesday, February 23, 2010
University of California, Berkeley Spring 2010 EE 42/100 Prof. A. Niknejad Midterm Exam (closed book/notes) Tuesday, February 23, 2010 Guidelines: Closed book. You may use a calculator. Do not unstaple
More informationSolution: Based on the slope of q(t): 20 A for 0 t 1 s dt = 0 for 3 t 4 s. 20 A for 4 t 5 s 0 for t 5 s 20 C. t (s) 20 C. i (A) Fig. P1.
Problem 1.24 The plot in Fig. P1.24 displays the cumulative charge q(t) that has entered a certain device up to time t. Sketch a plot of the corresponding current i(t). q 20 C 0 1 2 3 4 5 t (s) 20 C Figure
More informationV in (min) and V in (min) = (V OH V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs
ECE 642, Spring 2003  Final Exam Page FINAL EXAMINATION (ALLEN)  SOLUTION (Average Score = 9/20) Problem  (20 points  This problem is required) An openloop comparator has a gain of 0 4, a dominant
More informationMICROELECTRONIC CIRCUIT DESIGN Second Edition
MICROELECTRONIC CIRCUIT DESIGN Second Edition Richard C. Jaeger and Travis N. Blalock Answers to Selected Problems Updated 10/23/06 Chapter 1 1.3 1.52 years, 5.06 years 1.5 2.00 years, 6.65 years 1.8 113
More informationECE 3050A, Spring 2004 Page 1. FINAL EXAMINATION  SOLUTIONS (Average score = 78/100) R 2 = R 1 =
ECE 3050A, Spring 2004 Page Problem (20 points This problem must be attempted) The simplified schematic of a feedback amplifier is shown. Assume that all transistors are matched and g m ma/v and r ds.
More informationLecture 140 Simple Op Amps (2/11/02) Page 1401
Lecture 40 Simple Op Amps (2//02) Page 40 LECTURE 40 SIMPLE OP AMPS (READING: TextGHLM 425434, 453454, AH 249253) INTRODUCTION The objective of this presentation is:.) Illustrate the analysis of BJT and
More informationAmplifiers, Source followers & Cascodes
Amplifiers, Source followers & Cascodes Willy Sansen KULeuven, ESATMICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 005 02 Operational amplifier Differential pair v : B v + Current mirror
More informationVI. Transistor amplifiers: Biasing and Small Signal Model
VI. Transistor amplifiers: iasing and Small Signal Model 6.1 Introduction Transistor amplifiers utilizing JT or FET are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly.
More informationCHAPTER 7  CD COMPANION
Chapter 7  CD companion 1 CHAPTER 7  CD COMPANION CD7.2 Biasing of SingleStage Amplifiers This companion section to the text contains detailed treatments of biasing circuits for both bipolar and fieldeffect
More informationDelhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:
Serial : 0. LS_D_ECIN_Control Systems_30078 Delhi Noida Bhopal Hyderabad Jaipur Lucnow Indore Pune Bhubaneswar Kolata Patna Web: Email: info@madeeasy.in Ph: 04546 CLASS TEST 089 ELECTRONICS ENGINEERING
More informationElectronic Circuits. Transistor Bias Circuits. Manar Mohaisen Office: F208 Department of EECE
lectronic ircuits Transistor Bias ircuits Manar Mohaisen Office: F208 mail: manar.subhi@kut.ac.kr Department of Review of the Precedent Lecture Bipolar Junction Transistor (BJT) BJT haracteristics and
More information5. EXPERIMENT 5. JFET NOISE MEASURE MENTS
5. EXPERIMENT 5. JFET NOISE MEASURE MENTS 5.1 Object The objects of this experiment are to measure the spectral density of the noise current output of a JFET, to compare the measured spectral density
More informationBasics of Network Theory (PartI)
Basics of Network Theory (PartI). A square waveform as shown in figure is applied across mh ideal inductor. The current through the inductor is a. wave of peak amplitude. V 0 0.5 t (m sec) [Gate 987: Marks]
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS V th " VGS vi  I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationEE292: Fundamentals of ECE
EE292: Fundamentals of ECE Fall 2012 TTh 10:0011:15 SEB 1242 Lecture 20 121101 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Chapters 13 Circuit Analysis Techniques Chapter 10 Diodes Ideal Model
More informationECE 205: Intro Elec & Electr Circuits
ECE 205: Intro Elec & Electr Circuits Final Exam Study Guide Version 1.00 Created by Charles Feng http://www.fenguin.net ECE 205: Intro Elec & Electr Circuits Final Exam Study Guide 1 Contents 1 Introductory
More informationAssignment 3 ELEC 312/Winter 12 R.Raut, Ph.D.
Page 1 of 3 ELEC 312: ELECTRONICS II : ASSIGNMENT3 Department of Electrical and Computer Engineering Winter 2012 1. A commonemitter amplifier that can be represented by the following equivalent circuit,
More informationECE Analog Integrated Circuit Design  II P.E. Allen
Lecture 290 Feedback Analysis using Return Ratio (3/20/02) Page 2901 LECTURE 290 FEEDBACK CIRCUIT ANALYSIS USING RETURN RATIO (READING: GHLM 599613) Objective The objective of this presentation is: 1.)
More informationSwitchedCapacitor Circuits David Johns and Ken Martin University of Toronto
SwitchedCapacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationChapter 13 Bipolar Junction Transistors
Chapter 3 ipolar Junction Transistors Goal. ipolar Junction Transistor Operation in amplifier circuits. 2. Loadline Analysis & Nonlinear Distortion. 3. Largesignal equialent circuits to analyze JT circuits.
More informationVer 3537 E1.1 Analysis of Circuits (2014) E1.1 Circuit Analysis. Problem Sheet 1 (Lectures 1 & 2)
Ver 3537 E. Analysis of Circuits () Key: [A]= easy... [E]=hard E. Circuit Analysis Problem Sheet (Lectures & ). [A] One of the following circuits is a series circuit and the other is a parallel circuit.
More informationOperational amplifiers (Op amps)
Operational amplifiers (Op amps) Recall the basic twoport model for an amplifier. It has three components: input resistance, Ri, output resistance, Ro, and the voltage gain, A. v R o R i v d Av d v Also
More information4.4 The MOSFET as an Amp and Switch
10/31/004 section 4_4 The MSFET as an Amp and Switch blank 1/1 44 The MSFET as an Amp and Switch Reading Assignment: pp 7080 Now we know how an enhancement MSFET works! Q: A: 1 H: The MSFET as an Amp
More informationS.E. Sem. III [ETRX] Electronic Circuits and Design I
S.E. Sem. [ETRX] Electronic ircuits and Design Time : 3 Hrs.] Prelim Paper Solution [Marks : 80 Q.1(a) What happens when diode is operated at high frequency? [5] Ans.: Diode High Frequency Model : This
More informationELECTRONIC SYSTEMS. Basic operational amplifier circuits. Electronic Systems  C3 13/05/ DDC Storey 1
Electronic Systems C3 3/05/2009 Politecnico di Torino ICT school Lesson C3 ELECTONIC SYSTEMS C OPEATIONAL AMPLIFIES C.3 Op Amp circuits» Application examples» Analysis of amplifier circuits» Single and
More informationLecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen
Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output
More information7. DESIGN OF ACCOUPLED BJT AMPLIFIERS FOR MAXIMUM UNDISTORTED VOLTAGE SWING
à 7. DESIGN OF ACCOUPLED BJT AMPLIFIERS FOR MAXIMUM UNDISTORTED VOLTAGE SWING Figure. AC coupled common emitter amplifier circuit ü The DC Load Line V CC = I CQ + V CEQ + R E I EQ I EQ = I CQ + I BQ I
More informationELECTRONICS IA 2017 SCHEME
ELECTRONICS IA 2017 SCHEME CONTENTS 1 [ 5 marks ]...4 2...5 a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ]...5 3...6 a. [ 3 marks ]...6 b. [ 3 marks ]...6 4 [ 7 marks ]...7 5...8
More informationProf. Shayla Sawyer CP08 solution
What does the time constant represent in an exponential function? How do you define a sinusoid? What is impedance? How is a capacitor affected by an input signal that changes over time? How is an inductor
More informationFigure Circuit for Question 1. Figure Circuit for Question 2
Exercises 10.7 Exercises Multiple Choice 1. For the circuit of Figure 10.44 the time constant is A. 0.5 ms 71.43 µs 2, 000 s D. 0.2 ms 4 Ω 2 Ω 12 Ω 1 mh 12u 0 () t V Figure 10.44. Circuit for Question
More informationMetalOxideSemiconductor Field Effect Transistor (MOSFET)
MetalOxideSemiconductor ield Effect Transistor (MOSET) Source Gate Drain p p n substrate  SUB MOSET is a symmetrical device in the most general case (for example, in an integrating circuit) In a separate
More informationECE 304: Design Issues for Voltage Follower as Output Stage S&S Chapter 14, pp
ECE 34: Design Issues for oltage Follower as Output Stage S&S Chapter 14, pp. 131133 Introduction The voltage follower provides a good buffer between a differential amplifier and a load in two ways: 1.
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Threeterminal device whose voltagecurrent relationship is controlled by a third voltage
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 SwitchedCapacitor Amplifiers 13.4
More informationEIT QuickReview Electrical Prof. Frank Merat
CIRCUITS 4 The power supplied by the 0 volt source is (a) 2 watts (b) 0 watts (c) 2 watts (d) 6 watts (e) 6 watts 4Ω 2Ω 0V i i 2 2Ω 20V Call the clockwise loop currents i and i 2 as shown in the drawing
More informationElectronic Circuits. Prof. Dr. Qiuting Huang Integrated Systems Laboratory
Electronic Circuits Prof. Dr. Qiuting Huang 6. Transimpedance Amplifiers, Voltage Regulators, Logarithmic Amplifiers, AntiLogarithmic Amplifiers Transimpedance Amplifiers Sensing an input current ii in
More informationECE2262 Electric Circuits. Chapter 4: Operational Amplifier (OPAMP) Circuits
ECE2262 Electric Circuits Chapter 4: Operational Amplifier (OPAMP) Circuits 1 4.1 Operational Amplifiers 2 4. Voltages and currents in electrical circuits may represent signals and circuits can perform
More informationThe CommonEmitter Amplifier
c Copyright 2009. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The CommonEmitter Amplifier Basic Circuit Fig. shows the circuit diagram
More informationChapter 10 AC Analysis Using Phasors
Chapter 10 AC Analysis Using Phasors 10.1 Introduction We would like to use our linear circuit theorems (Nodal analysis, Mesh analysis, Thevenin and Norton equivalent circuits, Superposition, etc.) to
More informationSwitched Capacitor Circuits II. Dr. Paul Hasler Georgia Institute of Technology
Switched Capacitor Circuits II Dr. Paul Hasler Georgia Institute of Technology Basic SwitchCap Integrator = [n1]  ( / ) H(jω) =  ( / ) 1 1  e jωt ~  ( / ) / jωt (z)  z 1 1 (z) = H(z) =  ( / )
More informationEE100Su08 Lecture #9 (July 16 th 2008)
EE100Su08 Lecture #9 (July 16 th 2008) Outline HW #1s and Midterm #1 returned today Midterm #1 notes HW #1 and Midterm #1 regrade deadline: Wednesday, July 23 rd 2008, 5:00 pm PST. Procedure: HW #1: Bart
More informationEE105 Fall 2014 Microelectronic Devices and Circuits
EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)
More informationENGR 2405 Chapter 8. Second Order Circuits
ENGR 2405 Chapter 8 Second Order Circuits Overview The previous chapter introduced the concept of first order circuits. This chapter will expand on that with second order circuits: those that need a second
More informationDESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OPAMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C
MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OPAMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 Email: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OPAMP It consists of two stages: First
More informationDelhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Ph:
Serial : IG1_CE_G_Concrete Structures_100818 Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: Email: info@madeeasy.in Ph: 011451461 CLASS TEST 01819 CIVIL ENGINEERING
More informationEE 40: Introduction to Microelectronic Circuits Spring 2008: Midterm 2
EE 4: Introduction to Microelectronic Circuits Spring 8: Midterm Venkat Anantharam 3/9/8 Total Time Allotted : min Total Points:. This is a closed book exam. However, you are allowed to bring two pages
More informationU1 is zero based because its noninverting terminal is connected to circuit common. Therefore, the circuit reference voltage is 0 V.
When you have completed this exercise, you will be able to operate a zenerclamped op amp comparator circuit using dc and ac voltages. You will verify your results with an oscilloscope. U1 is zero based
More informationREACTANCE. By: Enzo Paterno Date: 03/2013
REACTANCE REACTANCE By: Enzo Paterno Date: 03/2013 5/2007 Enzo Paterno 1 RESISTANCE  R i R (t R A resistor for all practical purposes is unaffected by the frequency of the applied sinusoidal voltage or
More informationanalyse and design a range of sinewave oscillators understand the design of multivibrators.
INTODUTION In this lesson, we investigate some forms of waveform generation using op amps. Of course, we could use basic transistor circuits, but it makes sense to simplify the analysis by considering
More information