VI. Transistor amplifiers: Biasing and Small Signal Model

Transcription

1 VI. Transistor amplifiers: iasing and Small Signal Model 6.1 Introduction Transistor amplifiers utilizing JT or FET are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly. Then, similar FET circuits are briefly reviewed. onsider the circuit below. The operating point of the JT is shown in the i v E space. i R i v E v E i E V V Let us add a sinusoidal source with an amplitude of V in series with V. In response to this additional source, the base current will become i i leading to the collector current of i i and E voltage of v E v E. i i ~ R V i v E i v E v E v E V V For example, assume without the sinusoidal source, the base current is 150 µa, i = 22 ma, and v E = 7 V (the Q point). If the amplitude of i is 40 µa, then with the addition of the sinusoidal source i i = cos(ωt) and varies from 110 to 190 µa. The JT operating point should remain on the load line and collector current and E voltage change with changing base current while remaining on the load line. For example when base current is 190 µa, the collector current is 28.6 ma and E voltage is about 4.5 V. As can be seen from the figure above, the collector current will approximately be i i = cos(ωt) and E voltage is v E v E = cos(ωt). The above example shows that the signal from the sinusoidal source V is greatly amplified and appears as signals in collector current and E voltage. It is clear from the figure that this happens as long as the JT stays in the active-linear state. As the amplitude of i EE65 Lecture Notes (F. Najmabadi), Winter

2 is increased, the swings of JT operating point along the load line become larger and larger and, at some value of i, JT will enter either the cut-off or saturation state and the output signals will not be a sinusoidal function. Note: An important observation is that one should locate the Q point in the middle of the load line if we want to have the largest output signal. The above circuit, however, has two major problems: 1) The input signal, V, is in series with the V D voltage making design of previous two-port network difficult, and 2) The output signal is usually taken across as i. This output voltage has a D component which is of no interest and can cause problems in the design of the next-stage, two-port network. The D voltage needed to bias the JT (establish the Q point) and the A signal of interest can be added together or separated using capacitor coupling as dis iscussed below apacitive oupling For D voltages (ω = 0), the capacitor is an open circuit (infinite impedance). For A voltages, the impedance of a capacitor, Z = j/(ω), can be made sufficiently small by choosing an appropriately large value for (the higher the frequency, the lower the value that one needs). This property of capacitors can be used to add and separate A and D signals. Example below highlights this effect. onsider the circuit below which includes a D source of 15 V and an A source of = V i cos(ωt). We are interested to calculate voltages v A and v. The best method to solve this circuit is superposition. The circuit is broken into two circuits. In circuit 1, we kill the A source and keep the D source. In circuit 2, we kill the D source and keep the A source. Superposition principle states that v A = v A1 v A2 and v = v 1 v 2. A 1 R 2 15 V R 1 v A R 2 1 v 15 V 15 V R 2 v A1 1 v 1 v A2 R 2 1 v 2 R 1 R 1 R 1 onsider the first circuit. It is driven by a D source and, therefore, the capacitor will act as open circuit. The voltage v A1 = 0 as it is connected to ground and v 1 can be found by EE65 Lecture Notes (F. Najmabadi), Winter

3 voltage divider formula: v 1 = 15R 1 /(R 1 ). As can be seen both v A1 and v 1 are D voltages. In the second circuit, resistors R 1 and are in parallel. Let R = R 1. The circuit is a high-pass filter: V A2 = V i and V 2 = V i (R )/(R 1/jω). If we operate the circuit at frequency above the cut-off frequency of the filter, i.e., R 1/ω, we will have V 2 V A2 = V i and v 2 v A2 = V i cos(ωt). Therefore, for ω 1/R v A = v A1 v A2 = V i cos(ωt) v = v 1 v 2 = R 1 R 1 15 V i cos(ωt) Obviously, the capacitor is preventing the D voltage to appear at point A, while the voltage at point is the sum of D signal from 15-V supply and the A signal. Using capacitive coupling, we can reconfigure our previous amplifier circuit as is shown in the figure below. apacitive coupling is used extensively in transistor amplifiers. v E v E v E i i V ~ R i v E i v E v E v E V V JT amplifier circuits are analyzed using superposition, similar to the example above: 1) D iasing: The input A signal is set to zero and capacitors act as open circuit. This analysis establishes the Q point in the active-linear state. 2) A Response: D bias voltages are set to zero. The response of the circuit to an A input is calculated and the transfer function, input and output impedances, etc. are found. The break up of the problem into these two parts have an additional advantage as the requirement for accuracy are different in the two cases. For D biasing, we are interested in locating the Q point roughly in the middle of active-linear state. The exact location of the Q point is not important. Thus, a simple model, such as large-signal model of page 114 is quite adequate. We are, however, interested to compute the transfer function for A signals more accurately. We will develop a model which is more accurate for small A signals in this section. FET-based amplifiers are similar. FET should be biased similar to JT and the analysis method is broken into the D biasing and the A response. EE65 Lecture Notes (F. Najmabadi), Winter

4 6.2 JT iasing This simple bias circuit is usually referred to as fixed bias as a fixed voltage is applied to the JT base. As we like to have only one power supply, the base circuit is also powered by V. (To avoid confusion, we will use capital letters to denote D bias values e.g., I.) Assuming that JT is in active-linear state, we have: R V i i E-KVL: V = I R V E I = V V E R v E v E I = βi = β V V E R E-KVL: V = I V E V E = V I V E = V β R (V V E ) For a given circuit (known, R, V, and JT β) the above equations can be solved to find the Q-point (I, I, and V E ). Alternatively, one can use the above equations to design a JT circuit to operate at a certain Q point. (Note: Do not memorize the above equations or use them as formulas, they can be easily derived from simple KVLs). Example 1: Find values of, R in the above circuit with β = 100 and V = 15 V so that the Q-point is I = 25 ma and V E = 7.5 V. Since the JT is in the active-linear state (V E = 7.5 > V γ ), I = I /β = 0.25 ma. E-KVL and E-KVL result in: E-KVL: V R I V E = 0 R = = 57.2 kω E-KVL: V = I V E 15 = = 300 Ω Example 2: onsider the circuit designed in example 1. What is the Q point if β = 200. We have R = 57.2 kω, = 300 Ω, and V = 15 V but I, I, and V E are unknown. Assuming that the JT is in the active-linear state: E-KVL: V R I V E = 0 I = V V E R I = β I = 50 ma = 0.25 ma E-KVL: V = I V E V E = = 0 EE65 Lecture Notes (F. Najmabadi), Winter

5 As V E < v γ the JT is not in the active-linear state (since I > 0, the JT should be in saturation). The above examples show the problem with our simple fixed-bias circuit as the β of a commercial JT can depart by a factor of 2 from its average value given in the manufacturers spec sheet. More importantly, environmental conditions (mainly temperature) can play an important role. In a given JT, I increases by 9% per for a fixed V E (because of the change in β). onsider a circuit which is tested to operate perfectly at 25. At 35, β and I will be roughly doubled and the JT can be in saturation! In fact, the circuit has a build-in positive feedback. If the temperature rises slightly, the corresponding increase in β makes I larger. Since the power dissipation in the transistor is V E I, the transistor may get hotter which increases transistor β and I further and can cause a thermal runaway. The problem is that our biasing circuit fixes the value of I (independent of JT parameters) and, as a result, both I and V E are directly proportional to JT β (see formulas in the previous page). A biasing scheme should be found that make the Q-point (I and V E ) independent of transistor β and insensitive to the above problems Use negative feedback! Voltage-Divider iasing This biasing scheme can be best analyzed and understood if we replace R 1 and of the voltage divider with its Thevenin equivalent: R 1 V V = R 1 V and R = R 1 The emitter resistor,, provides the negative feedback. Suppose I becomes larger than the designed value (e.g., larger β due to an increase in temperature). Then, V E = I E will increase. Since V and R do not change, KVL in the E loop shows that I should decrease which will reduce I back towards its design value. If I becomes smaller than its design value opposite happens, I has to increase which will increase and stabilize I. Analysis below also shows that the Q point is independent of JT parameters: Thevenin Equivalent { V i i v E v E _ R i v E V _ i v E I E I = βi E-KVL: V = R I V E I E I = V V E R β E-KVL: V = I V E I E V E = V I ( ) EE65 Lecture Notes (F. Najmabadi), Winter

6 hoose R such that R β (this is the condition for the feedback to be effective): I I E V V E and I V V E β V E = V I ( ) V (V V E ) Note that now both I and V E are independent of β. Another way to see how the circuit works is to consider E-KVL: V = R I V E I E. If we choose R β (I E /I ) or R I I E (rhe feedback condition above), the KVL reduces to V V E I E, forcing a constant I E independent of the JT β. As I I E this will also fixes the Q point of JT. If the JT parameters change (different β due to a change in temperature), the circuit forces I E to remain fixed and changes I accordingly. This biasing scheme is one of several methods which fix I (and V E ) and allow the JT to adjust I (through negative feedback) to achieve the proper bias. This class of biasing methods is usually called self-bias schemes. Another important point follows from V V E I E. As V E is not a constant and can change slightly (can drop to 0.6 or increase to 0.8 V for a Si JT), we need to ensure that I E is much larger than possible changes in V E. As changes in V E = v γ is about 0.1 V, we need to ensure that V E = I E 0.1 or V E > = 1 V. Example: Design a stable bias circuit with a Q point of I = 2.5 ma and V E = 7.5 V. Transistor β ranges from 50 to 200. Step 1: Find V : As we like to have the Q-point to be located in the middle of the load line, we set V = 2V E = = 15 V. Step 2: Find and : V E = V I ( ) = 7.5 = 3 kω We are free to choose and (usually the A response sets the values of and as is discussed later). We have to ensure, however, that V E = I E > 1 V or > 1/I E = 400 Ω. Let s choose = 1 kω which gives = 3 = 2 kω (both commercial values). Step 3: Find R and V : We need to set R β. As any commercial JT has a range of β values and we want to ensure that the above inequality is always satisfied, we should use the minimum β value: R β min R = 0.1β min = , 000 = 5 kω V V E I E = = 3.2 V EE65 Lecture Notes (F. Najmabadi), Winter

7 Step 4: Find R 1 and R = R 1 = R 1 R 1 = 5 kω V V = = 3.2 R 1 15 = 0.21 The above are two equations in two unknowns (R 1 and ). The easiest way to solve these equations are to divide the two equations to find R 1 and use that in the equation for V : R 1 = 5 kω = 24 kω 0.21 = = 0.21R 1 = 6.4 kω R 1 Reasonable commercial values for R 1 and are and 24 kω and 6.2 kω, respectively. The voltage divider biasing scheme is used frequently in JT amplifiers. There are two drawbacks to this biasing scheme that may make it unsuitable for some applications: 1) ecause V > 0, a coupling capacitor is needed to attach the input signal to the amplifier circuit. As a result, this biasing scheme leads to an A amplifier (cannot amplify D signals). In some applications, we need D amplifiers. iasing with two voltage sources, discussed below, can solve this problem. 2) The voltage divider biasing requires 3 resistors (R 1,, and ), and a coupling capacitor. In Is, resistors and large capacitors take too much space compared to transistors. It is preferable to reduce their numbers as much as possible. For I applications, currentmirrors are usually used to bias JT amplifiers as is discussed below iasing with 2 Voltage Sources V This biasing scheme is also a self-bias method and is similar to the voltage-divider biasing. asically, we have assigned a voltage of V EE to the ground (reference voltage) and chosen V EE = V. As such, all of the currents and voltages in the circuit should be identical to the voltage-divider biasing. We should find that this is a stable bias point as long as R β. R i v E _ i _ v E E-KVL: R I V E I E V EE = 0 R I E β I E = V EE V E I E = V EE V E R /β V EE EE65 Lecture Notes (F. Najmabadi), Winter

8 Similar to the bias with one power supply, if we choose R such that, R β, we get: E-KVL: I I E V EE V E = const V = I V E I E V EE V E = V V EE I ( ) = const Therefore, I, and V E are independent β and bias point is stable. Similar to the voltagedivider bias, we need to ensure that I E 1 V to account for possible variation in V E. ias with two power supplies has certain advantages over biasing with one power supply, it has two resistors, R and (as opposed to three), and in fact, in most applications, we can remove R altogether and directly couple the input signal (without a coupling capacitor) to the JT). As such, such a configuration can also amplify D signals iasing in Is: urrent Mirrors The self-bias schemes above, voltage-divider and bias with 2 voltage sources, essentially operate the same way: They force I E to have a given value independent of the JT parameters. In principle, the same objective can be achieved if we could bias the JT with a current source as is shown. In this case, no bias resistor is needed and we only need to include resistors necessary for A operation. As such, biasing with a current source is the preferred way in most integrated circuits. Such a biasing can be achieved with a current mirror circuit. R i v E _ V i _ v E I onsider the circuit shown with two identical transistors, Q 1 and Q 2. ecause both bases and emitters of the transistors are connected together, KVL leads to v E1 = v E2. As JT s are identical, they should have similar i (i 1 = i 2 = i ) and, therefore, similar i E = i E1 = i E2 and i = i 1 = i 2 I ref 2i E β 1 V EE I o i = i E β 1 KL: I ref = i 2i E β 1 = I o I ref = I o = i = β β 2 = 1 1 2/β βi E β 1 i E β 1 2i E β 1 = β 2 β 1 i E i i Q1 Q 2 v E1 v E2 i E i E V EE We have explicitly used i = βi and i E = (β 1)i to illustrate the impact of β. EE65 Lecture Notes (F. Najmabadi), Winter

9 For β 1, I o I ref (with an accuracy of 2/β). This circuit is called a current mirror as the two transistors work in tandem to ensure that current I o remains the same as I ref no matter what circuit is attached to the collector of Q 2. As such, the circuit behaves as a current source and can be used to bias JT circuits, i.e., Q 2 collector is attached to the emitter circuit of the JT amplifier to be biased. Value of I ref can be set in many ways. The simplest is by using a resistor R c as is shown. y KVL, we have: V I ref I o V = I ref v E1 V EE i I ref = V V EE v E1 = const Q1 Q 2 v E1 v E2 i E i E V EE urrent mirror circuits are widely used for biasing JTs. In the simple current mirror circuit above, I o = I ref with a relative accuracy of 2/β and I ref is constant with an accuracy of small changes in v E1. Variations of the above simple current mirror, such as Wilson current mirror and Widlar current mirror, have I o = I ref even with a higher accuracy and also compensate for the small changes in v E. Wilson mirror is especially popular because it replace R c with a transistor. The right hand part of the current mirror circuit can be duplicated such that one current mirror circuit can bias several JT circuits as is shown. In fact, by coupling output of two or more of the right hand JTs, integer multiples of I ref can be made for biasing circuits which require a higher bias current. V Iref I o I o 2I o V EE A large family of JT circuit, including current mirrors, differential amplifiers, and emittercoupled logic circuits include identical JT pairs. These circuits are rarely made of discrete transistors because if one chooses two commercial JTs, e.g., two 2N3904, there is no guaranty that β 1 = β 2. However, if two identical JTs are manufactured together on one chip next to each other, β 1 β 2 within a couple of percent. EE65 Lecture Notes (F. Najmabadi), Winter

10 6.3 iasing FETs Field-effect transistors can also be used in amplifier circuits by operating the FET in the active state. Similar to JT amplifiers, we need to apply a D bias (in addition to the input A signal) so that the FET remains in the active state for the entire period of the A signal. The fixed-bias scheme for FETs is shown. Note that R G is not necessary for biasing but is necessary for A operation as without R G the input A signal will be grounded through V GG. GS-KVL: V GG = V GS I D = K(V GS V t ) 2 = K(V GG V t ) 2 DS-KVL: V DD = I D R D V DS V DS = V DD KR D (V GG V t ) 2 Similar to the JT β, both V t and K vary due to the manufacturing and environmental conditions. For example, as temperture is increased, both V t and K decrease: decreasing K decreases I D while decreasing V t raises I D. The net effect (usually) is that I D decreases. While the thermal runaway is not a problem in FETs, the bias point is not stable. Similar to the JT bias circuits, addition of a resistor R S provides the negative feedback necessary to stabilize the bias point. For the voltage divider self bias, V G is set by R 1 and. Since V GS = V G R S I D, any decrease in I D would increase V GS and increases I D. Similarly, any increase in I D would decrease V GS and decreases I D. As a result, I D will stay nearly constant (because I D = K(V GS V t ) 2, I D does not remain constant like I in a JT, rather it variation become much smaller by the negative feedback). Another difference between voltage-divider self-bias for FET with that of JT si that in the case of JT, we have to ensure that R β for negative feedback to be effective. THis generally limits the value of R 1 and. In a FET, I G = 0 and no such limitaion exists. Therefore, R 1 and can be taken to be large (MΩ) which is important in the A response as is discussed later. Self bias with 2 power supplies and FET current mirror bias are also shown below. R G V GG V DD R D V DD V DD V DD R 2 R D i D R i D D R I ref I o R 1 R S R 1 R S V SS Voltage-divider (Self ias) ias with 2 power supplies FET urrent Mirror EE65 Lecture Notes (F. Najmabadi), Winter

11 6.4 JT Small Signal Model We calculated the D behavior of the JT (D biasing) with a simple large-signal model. In the active-linear state, this model is simply: v E = 0.7 V, i = βi. This model is sufficient for calculating the Q point as we are only interested in ensuring sufficient design space for the amplifier, i.e., Q point should be in the middle of the load line in the active-linear state. In fact, for our good biasing scheme with negative feedback, the Q point location is independent of JT parameters (and, therefore, independent of model used!). i v γ v E i v sat v E A comparison of the simple largesignal model with the iv characteristics of the JT shows that our simple large-signal model is crude. For example, the input A signal results in small changes in v E around 0.7 V (Q point) and corresponding changes in i. The simple model cannot be used to calculate these changes (It assumes v E is constant!). Also for a fixed i, i is not exactly constant as is assumed in the simple model (see i vs v E graphs). As a whole, the simple large signal model is not sufficient to describe the A behavior of JT amplifiers where more accurate representations of the amplifier gain, input and output resistance, etc. are needed. A more accurate, but still linear, model can be developed by assuming that the changes in transistor voltages and currents due to the A signal are small compared to corresponding Q-point values and using a Taylor series expansion. onsider function f(x). Suppose we know the value of the function and all of its derivative at some known point x 0. Then, the value of the function in the neighborhood of x 0 can be found from the Taylor Series EE65 Lecture Notes (F. Najmabadi), Winter

12 expansion as: f(x 0 x) = f(x 0 ) x df ( x)2 d 2 f dx x=x0 2 dx 2... x=x0 lose to our original point of x 0, x is small and the high order terms of this expansion (terms with ( x) n, n = 2, 3,...) usually become very small. Typically, we consider only the first order term, i.e., f(x 0 x) f(x 0 ) x df dx x=x0 The Taylor series expansion can be similarly applied to function of two or more variables such as f(x, y): f(x 0 x, y 0 y) f(x 0, y 0 ) x f y f x x0,y 0 y In a JT, there are four parameters of interest: i, i, v E, and v E. The JT iv characteristics plots, specify two of the above parameters, v E and i in terms of the other two, i and v E, i.e., v E is a function of i and v E (written as v E (i, v E ) similar to f(x, y)) and i is a function of i and v E, i (i, v E ). Let s assume that JT is biased and the Q point parameters are I, I, V E and V E. We now apply a small A signal to the JT. This small A signal changes v E and i by small values around the Q point: x0,y 0 i = I i v E = V E v E The A changes, i and v E results in A changes in v E and i that can be found from Taylor series expansion in the neighborhood of the Q point, similar to expansion of f(x 0 x, y 0 y) above: v E (I i, V E v E ) = V E v E i i v E v Q v E E Q i (I i, V E v E ) = I i i i i v Q v E E Q EE65 Lecture Notes (F. Najmabadi), Winter

13 where all partial derivatives are calculated at the Q point and we have noted that at the Q point, v E (I, V E ) = V E and i (I, V E ) = I. We denote the A changes in v E and i as v E and i, respectively: v E (I i, V E v E ) = V E v E i (I i, V E v E ) = I i So, by applying a small A signal, we have changed i and v E by small amounts, i and v E, and JT has responded by changing, v E and i by small A amounts, v E and i. From the above two sets of equations we can find the JT response to A signals: v E = v E i i v E v E v E, i = i i i i v E v E where the partial derivatives are the slope of the iv curves near the Q point. We define h ie v E i, h re v E v E, h fe i i, h oe i v E Thus, response of JT to small signals can be written as: v E = h ie i h re v E i = h fe i h oe v E which is our small-signal model for JT. We now need to relate the above analytical model to circuit elements so that we can solve JT circuits. onsider the expression for v E v E = h ie i h re v E Each term on the right hand side should have units of Volts. Thus, h ie should have units of resistance and h re should have no units (these are consistent with the definitions of h ie and h re ). Furthermore, the above equation is like a KVL: the voltage drop between the base and emitter ( v E ) is equal to the sum of voltage drops across two elements. The voltage drop across the first element is h ie i. So, it is a resistor with a value of h ie. The voltage drop across the second element is h re v E. Thus, it is a dependent voltage source. E v ΒΕ i Β V 1 = h ie i V 2 = h v re E i Β v ΒΕ E h ie h re v E EE65 Lecture Notes (F. Najmabadi), Winter

14 Now consider the expression for i : i = h fe i h oe v E Each term on the right hand side should have units of Amperes. Thus, h fe should have no units and h oe should have units of conductance (these are consistent with the definitions of h oe and h fe.) Furthermore, the above equation is like a KL: the collector current ( i ) is equal to the sum of two currents. The current in first element is h fe i. So, it is a dependent current source. The current in the second element is proportional to h oe / v E. So it is a resistor with the value of 1/h oe. i = h i 1 fe i v E h fe i i 1/h oe v E i = h 2 oe v E E E Now, if put the models for E and E terminals together we arrive at the small signal hybrid model for JT. It is similar to the hybrid model for a two-port network. i v E _ E h ie i h i fe h 1/h oe v re v E E - - E The small-signal model is mathematically valid only for signals with small amplitudes. ut this model is so useful that is often used for signals with amplitudes approaching those of Q-point parameters by using average values of h parameters. h parameters are given in the manufacturer s spec sheets for each JT. It should not be surprising to note that even in a given JT, h parameter can vary substantially depending on manufacturing statistics, operating temperature, etc. Manufacturer s spec sheets list these h parameters and give the minimum and maximum values. Traditionally, the geometric mean of the minimum and maximum values are used as the average value in design (see the table below). Since h fe = i / i and JT β = i /i, β is sometimes called h F E in manufacturers spec sheets and has a value quite close to h fe. In most electronic text books, β, h F E and h fe are used interchangeably. EE65 Lecture Notes (F. Najmabadi), Winter

15 Typical hybrid parameters of a general-purpose 2N3904 NPN JT Minimum Maximum Average* r π = h ie (kω) h re β h fe h oe (µs) r o = 1/h oe (kω) 25 1, r e = h ie /h fe (Ω) * Geometric mean. As h re is small, it is usually ignored in analytical calculations as it makes analysis much simpler. This model, called the hybrid-π model, is most often used in analyzing JT circuits. In order to distinguish this model from the hybrid model, most electronic text books use a different notation for various elements of the hybrid-π model: r π = h ie r o = 1 h oe β = h fe i v E _ h ie h fe i i 1/h oe = i v E _ r π β i r o i E E The above hybrid-π model includes a current-controlled current source. A variant of the hybrid-π model can be developed which includes a voltage-controlled current source by noting ( v E = r π i : β i = β v E r π g m β r π = g m v E Transfer conductance i v E r π g m v E i r o r e 1 = r π g m β Emitter resistance _ E EE65 Lecture Notes (F. Najmabadi), Winter

16 6.5 FET Small Signal Model Similar to the JT, the simple large-signal model of FET (page 127) is sufficient for finding the bias point; but we need to develop a more accurate model for analysis of A signals. The main issue is that the FET large signal model indicates that i D only depends on v GS and is independent of v DS in the active state. In reality, i D increases slightly with v DS in the active state. We can develop a small signal model for FET in a manner similar to the procedure described in detail for the JT. The FET characteristics equations specify two of the FET parameters, i G and i D, in terms of the other two, v GS and v DS. (Actually FET is simpler than JT as i G = 0 at all times.) As before, we write the FET parameters as a sum of D bias value and a small A signal, e.g., i D = I D i D. Performing a Taylor series expansion, similar to pages 169 and 170, we get: i G (V GS v GS, V DS v DS ) = 0 v GS i D (V GS v GS, V DS v DS ) = i D (V GS, V DS ) i D v DS Q v GS i D Q v DS Since i G (V GS v GS, V DS v DS ) = I G i G and i D (V GS v GS, V DS v DS ) = I D i D, we find the A components to be: Defining v GS i G = 0 and i D = i D v DS Q v GS i D Q v DS We get: g m i D v GS and r o i D v DS i G = 0 and i D = g m v GS r o v DS This results in the hybrid-π model for the FET as is shown. Note that the FET hybrid-π model is similar to the JT hybrid-π model with r π. G i = 0 G v GS _ g m v GS r o i D D S EE65 Lecture Notes (F. Najmabadi), Winter

17 6.6 JT Amplifier ircuits As we have developed different models for D signals (simple large-signal model) and A signals (small-signal model), analysis of JT circuits follows these steps: D biasing analysis: Assume all capacitors are open circuit. Analyze the transistor circuit using the simple large signal mode as described in page 114. A analysis: 1) Kill all D sources 2) Assume coupling capacitors are short circuit. The effect of these capacitors is to set a lower cut-off frequency for the circuit. This is analyzed in the last step. 3) Inspect the circuit. If you identify the circuit as a prototype circuit, you can directly use the formulas for that circuit. Otherwise go to step 4. 4) Replace the JT with its small signal model. 5) Solve for voltage and current transfer functions and input and output impedances (nodevoltage method is the best). 6) ompute the cut-off frequency of the amplifier circuit. Several standard JT amplifier configurations are discussed below and are analyzed. For completeness, circuits include standard bias resistors R 1 and. For bias configurations that do not utilize these resistors (e.g., current mirror), simply set R = R ommon ollector Amplifier (Emitter Follower) D analysis: With the capacitors open circuit, this circuit is the same as our good biasing circuit of page 162 with = 0. The bias point currents and voltages can be found using procedure of pages c R 1 V A analysis: To start the analysis, we kill all D sources: V = 0 R 1 c c E R 1 EE65 Lecture Notes (F. Najmabadi), Winter

18 We can combine R 1 and into R (same resistance that we encountered in the biasing analysis) and replace the JT with its small signal model: c R v E _ i r π E β i i r o c R i r π r o E β i The figure above shows why this is a common collector configuration: the collector is common between the input and output A signals. We can now proceed with the analysis. Node voltage method is usually the best approach to solve these circuits. For example, the above circuit has only one node equation for node at point E with a voltage : r π 0 r o β i 0 = 0 ecause of the controlled source, we need to write an auxiliary equation relating the control current ( i ) to node voltages: i = r π Substituting the expression for i in our node equation, multiplying both sides by r π, and collecting terms, we get: [ ( 1 (1 β) = 1 β r π 1 )] [ = 1 β r ] π r o r o Amplifier Gain can now be directly calculated: A v = 1 r π 1 (1 β)(r o ) Unless is very small (tens of Ω), the fraction in the denominator is quite small compared to 1 and A v 1. To find the input impedance, we calculate i i by KL: i i = i 1 i = R r π EE65 Lecture Notes (F. Najmabadi), Winter

19 Since, we have i i = /R or R i i i = R Note that R is the combination of our biasing resistors R 1 and. With alternative biasing schemes which do not require R 1 and (and, therefore, R ), the input resistance of the emitter follower circuit will become large. In this case, we cannot use. Using the full expression for from above, the input resistance of the emitter follower circuit becomes: R i i i = R [r π ( r o )(1 β)] which is quite large (hundreds of kω to several MΩ) for R. Such a circuit is in fact the first stage of the 741 OpAmp. The output resistance of the common collector amplifier (in fact for all transistor amplifiers) is somewhat complicated because the load can be configured in two ways (see figure): First,, itself, is the load. This is the case when the common collector is used as a current amplifier to raise the power level and to drive the load. The output resistance of the circuit is R o as is shown in the circuit model. This is usually the case when values of R o and A i (current gain) is quoted in electronic text books. V V R 1 R 1 c c = R L R L R is the Load E Separate Load c r π E c r π E i β i i β i R r o R r o R L R o R o Alternatively, the load can be placed in parallel to. This is done when the common collector amplifier is used as a buffer (A v 1, R i large). In this case, the output resistance is denoted by R o (see figure). For this circuit, JT sees a resistance of R L. Obviously, if we want the load not to affect the emitter follower circuit, we should use R L to be much EE65 Lecture Notes (F. Najmabadi), Winter

20 larger than. In this case, little current flows in R L which is fine because we are using this configuration as a buffer and not to amplify the current and power. As such, value of R o or A i does not have much use. When is the load, the output resistance can be found by killing the source (short ) and finding the Thevenin resistance of the two-terminal network (using a test voltage source). c R r π E i β i r o i T v T KL: i T = i v T r o β i KVL (outside loop): r π i = v T R o Substituting for i from the 2nd equation in the first and rearranging terms we get: R o v T i T = (r o ) r π (1 β)(r o ) r π Since, (1 β)(r o ) r π, the expression for R o simplifies to R o (r o) r π (1 β)(r o ) = r π (1 β) r π β = r e As mentioned above, when is the load the common collector is used as a current amplifier to raise the current and power levels. This can be seen by checking the current gain in this amplifier: i o = /, i i /R and A i i o i i = R We can calculate R o, the output resistance when an additional load is attached to the circuit (i.e., is not the load) with a similar procedure: we need to find the Thevenin resistance of the two-terminal network (using a test voltage source). c R r π E i β i r o R o i T v T We can use our previous results by noting that we can replace r o and with r o = r o which results in a circuit similar to the case with no R L. Therefore, R o has a similar expression as R o if we replace r o with r o : c R r π E i β i r o R o i T v T EE65 Lecture Notes (F. Najmabadi), Winter

21 R o v T i T = (r o) r π (1 β)(r o ) r π In most circuits, (1 β)(r o ) r π (unless we choose a small value for ) and R o r e In summary, the general properties of the common collector amplifier (emitter follower) include a voltage gain of unity (A v 1), a very large input resistance R i R (and can be made much larger with alternate biasing schemes). This circuit can be used as buffer for matching impedance, at the first stage of an amplifier to provide very large input resistance (such in 741 OpAmp). The common collector amplifier can be also used as the last stage of some amplifier system to amplify the current (and thus, power) and drive a load. In this case, is the load, R o is small: R o = r e and current gain can be substantial: A i = R /. Impact of oupling apacitor: Up to now, we have neglected the impact of the coupling capacitor in the circuit (assumed it was a short circuit). This is not a correct assumption at low frequencies. The coupling capacitor results in a lower cut-off frequency for the transistor amplifiers. In order to find the cut-off frequency, we need to repeat the above analysis and include the coupling capacitor impedance in the calculation. In most cases, however, the impact of the coupling capacitor and the lower cut-off frequency can be deduced be examining the amplifier circuit model. onsider our general model for any amplifier circuit. If we assume that coupling capacitor is short circuit (similar to our A analysis of JT amplifier), v i =. V i c V i R i R o AV i Voltage Amplifier Model When we account for impedance of the capacitor, we have set up a high pass filter in the input part of the circuit (combination of the coupling capacitor and the input resistance of the amplifier). This combination introduces a lower cut-off frequency for our amplifier which is the same as the cut-off frequency of the high-pass filter: ω l = 2π f l = 1 R i c Lastly, our small signal model is a low-frequency model. As such, our analysis indicates that the amplifier has no upper cut-off frequency (which is not true). At high frequencies, the capacitance between E,, E layers become important and a high-frequency smallsignal model for JT should be used for analysis. You will see these models in upper division EE65 Lecture Notes (F. Najmabadi), Winter I o Vo Z L

22 courses. asically, these capacitances results in amplifier gain to drop at high frequencies. PSpice includes a high-frequency model for JT, so your simulation should show the upper cut-off frequency for JT amplifiers ommon Emitter Amplifier D analysis: Recall that an emitter resistor is necessary to provide stability of the bias point. As such, the circuit configuration as is shown has as a poor bias. We need to include for good biasing (D signals) and eliminate it for the A signals. The solution is to include an emitter resistance and use a bypass capacitor to short it out for A signals as is shown. R 1 c V Poor ias c R 1 V b Good ias using a by pass capacitor For this new circuit and with the capacitors open circuit, this circuit is the same as our good biasing circuit of page 162. The bias point currents and voltages can be found using procedure of pages A analysis: To start the analysis, we kill all D sources, short out b (which shorts out ), combine R 1 and into R, and replace the JT with its small signal model. We see that the emitter is now common between the input and output A signals (thus, the common emitter amplifier). Examination of the circuit shows that: c = r π i = ( r o ) β i A v = β r π ( r o ) β r π = r e R i = R r π R i β i r π r o E R o R o The negative sign in A ndicates a 180 phase shift between the input and output signals. This circuit has a large voltage gain but has a medium value for the input resistance. As with the emitter follower circuit, the load can be configured in two ways: 1) is the load; or 2) the load is placed in parallel to. The output resistance can be found by killing the source (short ) and finding the Thevenin resistance of the two-terminal network. For this circuit, we see that if = 0 (killing the source), i = 0. In this case, the strength of EE65 Lecture Notes (F. Najmabadi), Winter

23 the dependent current source would be zero and this element would become an open circuit. Therefore, R o = r o R o = r o Lower cut-off frequency: oth the coupling and bypass capacitors contribute to setting the lower cut-off frequency for this amplifier, both act as a high-pass filter with: ω l (coupling) = 2π f l = 1 R i c ω l (bypass) = 2π f l = 1 R E b where R E r e Note that usually r e and, therefore, R E r e. In the case when these two frequencies are far apart, the cut-off frequency of the amplifier is set by the larger cut-off frequency. i.e., ω l (bypass) ω l (coupling) ω l = 2π f l = 1 R i c ω l (coupling) ω l (bypass) ω l = 2π f l = 1 R E b When the two frequencies are close to each other, there is no exact analytical formulas, the cut-off frequency should be found from simulations. An approximate formula for the cut-off frequency (accurate within a factor of two and exact at the limits) is: ω l = 2π f l 1 R i c 1 R E b EE65 Lecture Notes (F. Najmabadi), Winter

24 6.6.3 ommon Emitter Amplifier with Emitter resistance A problem with the common emitter amplifier is that its gain depend on JT parameters: A v (β/r π ). Some form of feedback is necessary to ensure stable gain for this amplifier. One way to achieve this is to add an emitter resistance. Recall impact of negative feedback on OpAmp circuits: we traded gain for stability of the output. Same principles apply here. D analysis: With the capacitors open circuit, this circuit is the same as our good biasing circuit of page 162. The bias point currents and voltages can be found using procedure of pages A analysis: To start the analysis, we kill all D sources, combine R 1 and into R and replace the JT with its small signal model. Analysis is straight forward using node-voltage method. v E r π v E β i v E r o = 0 v E r o β i = 0 i = v E r π (ontrolled source aux. Eq.) 1 R v E _ i r π c E R 1 β i V i r o vo Substituting for i in the node equations and noting 1 β β, we get : v E β v E r π v E r o v E r o = 0 β v E r π = 0 Above are two equations in two unknowns (v E and ). Adding the two equation together we get v E = ( / ) and substituting that in either equations we can find. Using r π /β = r e, we get: A v = = r e (1 /r o ) (1 r e /r o ) r e (1 /r o ) where we have simplified the equation noting r e r o. For most circuits, r e. In this case, the voltage gain is simply A v = /. r o and EE65 Lecture Notes (F. Najmabadi), Winter

25 The input resistance of the circuit can be found from (prove it!) R i = R i Noting that i = ( v E )/r π and v E = ( / ) = ( / )A v, we get: R i = R r π 1 A v / Substituting for A v from above (complete expression for A v with r e /r o 1), we get: [ ( )] R i = R β r e 1 /r o For most circuits, r o and r e. In this case, the input resistance is simply R i = R (β ). As before the minus sign in A ndicates a 180 phase shift between input and output signals. Note the impact of negative feedback introduced by the emitter resistance: The voltage gain is independent of JT parameters and is set by and (recall OpAmp inverting amplifier!). The input resistance is also increased dramatically. As with the emitter follower circuit, the load can be configured in two ways: 1) is the load. 2) Load is placed in parallel to. The output resistance can be found by killing the source (short ) and finding the Thevenin resistance of the two-terminal network (by attaching a test voltage source to the circuit). i r π i 1 E β i i 2 r o i T R o v T Resistor R drops out of the circuit because it is shorted out. Resistors r π and are in parallel. Therefore, i 1 = (r π / ) i and by KL, i 2 = (β 1 r π / ) i. Then: ( i T = i i 1 = i 1 r ) π [ ( v T = i r π i 2 r o = i r o β 1 r ) ] π r π i r π i 1 E β i i 2 r o i T R o v T Then: R o = v T i T = r o 1 r o/r e 1 /r π EE65 Lecture Notes (F. Najmabadi), Winter

26 where we have used r π /β = r e. Generally r o r e (first approximation below) and for most circuit, r π (second approximation) leading to R o r o r o /r e 1 /r π r o r o r e = r o ( ) RE 1 r e Value of R o shows that can be found by a similar procedure. Alternatively, examination of the circuit R o = R o Lower cut-off frequency: The coupling capacitor together with the input resistance of the amplifier lead to a lower cut-off frequency for this amplifier (similar to emitter follower). The lower cut-off frequency is given by: ω l = 2π f l = 1 R i c A Possible iasing Problem: The gain of the common emitter amplifier with the emitter resistance is approximately /. For cases when a high gain (gains larger than 5-10) is needed, may be become so small that the necessary good biasing condition, V E = I E > 1 V cannot be fulfilled. The solution is to use a by-pass capacitor as is shown. The A signal sees an emitter resistance of 1 while for D signal the emitter resistance is the larger value of = 1 2. Obviously formulas for common emitter amplifier with emitter resistance can be applied here by replacing with 1 as in deriving the amplifier gain, and input and output impedances, we short the bypass capacitor so 2 is effectively removed from the circuit. c R 1 V 2 1 b The addition of by-pass capacitor, however, modifies the lower cut-off frequency of the circuit. Similar to a regular common emitter amplifier with no emitter resistance, both the coupling and bypass capacitors contribute to setting the lower cut-off frequency for this amplifier. Similarly we find that an approximate formula for the cut-off frequency (accurate within a factor of two and exact at the limits) is: ω l = 2π f l = 1 R i c 1 R E b where R E 2 (1 r e ) EE65 Lecture Notes (F. Najmabadi), Winter

27 6.6.4 ommon ase Amplifier y setting the signal ground at the base of the JT, one arrives at the common base amplifier (the input sginal is still applied between the base and the emitter). While it is possible to bias this configuration with a voltage divider self-bias, the preferred method is to bias this amplifier with two power supplies (or a current mirror). The bias point currents and voltages can be found using procedure of pages V A analysis: To start the analysis, we kill all D sources and replace the JT with its small signal model. We see that base is now common between the input and output A signals (thus, the common base amplifier). i r π β i = r o c i i E c β i V EE c E i r π r o Using node voltage method and noting i = /r π : β i r o = 0 ( 1 1 r o 1 r o β r π ) ( β rπ 1 ro ) = 0 A v = β r π ( r o ) β r π = r e which is exactly the gain of the common emitter amplifier (with no emitter resistor) except for the positive sign. This should not be surprising as compared to a common emitter, we have switched the terminals of the input signal (leading to the change in the sign of A v ) and the output voltage is v = v E v E v E because of the high gain of the amplifier. EE65 Lecture Notes (F. Najmabadi), Winter

28 The input resistance of the circuit can be found by finding i i from the circuit above and computing /i i to be R i = r π (r o ) r π r o (1 β) r π(r o ) r o (1 β) r π 1 β r π β = r e In the approximation, we first used the fact that r π r o (1 β) and then r o. Note that the input resistance is quite small. As before, the load can be configured in two ways: 1) is the load; or 2) load is placed in parallel to. The output resistance can be found by killing the source (short ) and finding the Thevenin resistance of the two-terminal network. For this circuit, we see that if = 0 (killing the source), i = 0. In this case, the strength of the dependent current source would be zero and this element would become an open circuit. In addition, emitter would be effectively grounded and resistors and r π are effectively shorted out of the circuit. Therefore, R o = r o R o = r o which are similar to the common amplifier with no emitter resistor. As a whole, this circuit is similar to common emitter amplifier with no resistor (large voltage gain, medium output resistance) but has a very low input resistance (r e ). As such, it is rarely used as a voltage amplifier (except for very specialized cases). Following the formula in page 13, the short circuit current-gain of this amplifier is: A i = Z I Z L Z o A v = r e 0 R c r e = 1 Therefore, this circuit has a low input resistance, a medium output resistance and currentgain of unity and, therefore, is a current buffer : It accepts an input signal current with a low input resistance and deliver nearly equal current to a much higher output resistance. ommon-base amplifiers are mostly used as a current buffer, typically forming circuits including two JTs (cascode amplifier) which are utilized specially in integrated circuits. EE65 Lecture Notes (F. Najmabadi), Winter

29 6.7 FET Amplifier ircuits As expected, FET amplifiers are very similar to the JT amplifiers. There are four basic FET amplifiers: 1) common-drain or source follower (similar to common collector or emitter follower), 2) common-source (similar to common emitter), 3) common source with a source resistor (similar to common emitter with an emitter resistor) and common gate (similar to common base). The analysis technique are exactly the same: 1) D-biasing analysis, and 2) A analysis in which we replace FET with its small signal model. In fact, by comparing the small signal model for an FET that that of a JT, we should be able to find the answer immediately by replacing β/r π = g m in the formulas of the equivalent JT circuits and then let r π (and of course, replace R D, R S, and R = R 1 R G = R 1 ). Therefore, we will only solve the common-source amplifier in detail and summarize the results for the other configurations ommon Source Amplifier V DD V DD D analysis: Recall that a source resistor is necessary to provide stability for the bias point. As such, the circuit configuration as is shown has a poor bias. We need to include R S for good biasing (D signals) and eliminate it for A signals. The solution is to include a source resistance and use a bypass capacitor to short it out for A signals similar to the JT common-emitter amplifier. R 1 c Poor ias R D c R 1 R S R D b Good ias using a by pass capacitor A analysis: To start the analysis, we kill all D sources, short out b (which shorts out R S ), combine R 1 and into R G, and replace the FET with its small signal model. We see that the source is now common between the input and output A signals (thus, the common source amplifier). Examination of the circuit shows that: c G i = 0 G D = v GS = (R D r o ) g m v GS g v m GS A v = g m (R D r o ) g m R D R i = R G R G v GS _ S r o R D R o R o R o = r o R o = R D r o EE65 Lecture Notes (F. Najmabadi), Winter

30 which are exactly the same as formulas for a JT common emitter amplifier if we let β/r π = g m and r π. Note that as an FET can be biased with large (MΩ) R 1 and (see page 167), the input resistance of this amplifier is considerably larger than that of a common emitter amplifier and can even be made to be infinitely large (resistance of the Gate insulator) by removing R G and biasing the circuit with two voltage supplies or a current mirror. Lower cut-off frequency: As R i is very large, the lower cut-off frequency is set by the bypass capacitor (unless c is chosen to be very small). ω l = ω l (bypass) = 2π f l = 1 R S b where R S R S 1 g m Note that usually R S 1/g m and, therefore, R S 1/g m ommon Source Amplifier with Source resistance Similar to common-emitter amplifier, the common source amplifier gain depends on the FET parameters (g m ). Addition of a source resistance will remove this dependency (similar to the common emitter amplifier with an emitter resistor). Details of the A analysis is left as an exercise. The parameters of this amplifier are: c R 1 V DD R D A v = g mr D 1 g m R S R D R S R S R i = R G R o = 1/g m r o ω l = 2π f l = 1 R i c R o = R D R o R D Similar to the common-emitter amplifier, the gain is set by R D and R S and is independent of the FET parameters. The input resistance of the circuit is large (much larger than common emitter amplifier because R 1 and can be large). EE65 Lecture Notes (F. Najmabadi), Winter