Chapter 3 Output stages


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1 Chapter 3 utput stages
2 3.. Goals and properties
3 3.. Goals and properties deliver power into the load with good efficacy and small power dissipate on the final transistors small output impedance maximum output excursion small distortions Class A:  very small distortions  poor efficacy Class B:  important distortions  good efficacy Class AB:  small distortions  good efficacy
4 3.. Class A output stage, common collector configuration
5 3.. Class A output stage, common collector configuration Q v i c3 Q Q 3 i o l v v C 3 0; i ; BE 3 0 CE 3 Transfer characteristic v f ( ) v v + v BE 3 c3 BE3 th i ln i + c3 S v l v v v + th th ln ln v With <<, th ln BE 3 l, the expression of the transfer characteristic S becomes, in consequence, v v + v, so linear.  v o n repose: BE3 S + v S l
6 v  Cesat3 slope BE3 v l small (Q 3 blocked)  l l large (Q saturated)  (  Cesat ) i C 3 i + C 3 + v l v l CE 3 i 0 v + C 3 CE 3 l
7 The maximum positive value of the output voltage is: M CEsat 3 The maximum negative output voltage depends on the value of l : for large l large, the negative limit of the output voltage is limited by the saturation of Q M CEsat M < for l small, the negative limit of the output voltage is limited by the blocking of Q M l < CEsat M t is possible to obtain in the same time maximum values of tension and current, so a maximum output power for an optimal value of the load resistance:
8 Fundamental energetical relations Noting: K where K is the utilization factor of the power supply, 0 K <. So: K K l l The power dissipated on Q 3 is: p D3 v p CE 3 D3 i C 3 sinωt + sinωt ( K sin ωt)( + K sinωt) ( ) K K pd3 K sin ωt + cos ωt So, the average power is: P D3 π π 0 p D3 dωt K
9 v t  i c, i c, i c3 i c i c i c3 l K v CE3, v CE t v CE v CE3 t p D3 p D t t
10 The power dissipated on Q is: p D i C v CE So, the average power is:: + π PD pddωt π The consumed power could be written: p A i C π i C sin ωt + P A p d t 0 A ω π The average output power is: π π ( K sinωt) ( + K sinωt) P p dωt ( K sinωt)( K sinωt) dωt π π 0 so, a maximum value of 5%. η A 0 P P A 5% K K
11 (P A, P, P D3, P D )/P A P A 0,5 0,5 P D P P D3 K / P P + D D3 P P P + P + P A D D3 P D
12 3.3. Class B elementary output amplifier stage
13 3.3. Class B elementary output amplifier stage ` v o Q B B B B C S Q S C B B B B Q  Cesat slope v i C i C i o Q v Q l v o slope  BEon BEon  Dead zone  ( / Cesat /) n repose: v 0; i 0; ic ic ; vbe + veb 0 f: Q Q; S S S th ln ic ic S 0
14 ` v o v o v t v t Transfer characteristic
15 v t  i c t i c v o l (i c i c ) t t  p D i c v CE t
16 Disadvantages of a pushpull class B output stage  dead zone (distortions)  requires PNP transistors (nonperformant) Solutions:  evolution to class AB  solution full NPN Fundamental energetical relations Noting: K where K is the utilization factor of the supply voltage, 0 K <. The average output power P is : π π ( K ) sinωt K 0 l K P p 0 dωt sinωt dωt π π Noting with P A the total delivered power (for both supply sources): P A l
17 Where the continuous component is: So:: π π 0 C sinωtdωt π C π l K π PA K πl The average dissipated power P D for a pair of transistors in class B is: 4K PD PA P K l π The previous expression represents a parabola in K, so the maximum could be obtained by making the derivate equal with zero: 4 K 0 K π π For this value of K it will be obtained the maximum average dissipated power (for both transistors): P DM π l π 4 l π 4 P M l P M l
18 n the following graphics it will be represented the normalized powers as function of K. P P A AM K; P P AM πk 4 ; P P D AM Kπ K 4 (P A, P, P D )/P AM π/4 P A P /π π/4 P D K / /π The efficacy depends on the amplitude of the output power: P π η K PA 4 ts maximum is obtained for K and it is π/4 (78.5%).
19 3.4. The nonlinearity reduction for a class B output stage due to the negative reaction
20 3.4. The nonlinearity reduction for a class B output stage due to the negative reaction v 5 pente 50,6 v S f 0kΩ pente 0, v r.5kω v S a 0 5 v 5 pente 56µ v S µ pente
21 3.5. Class AB output stage
22 3.5. Class AB output stage Q Q v i C i C Q Q l v o  n order to obtain a good linearity of the global transfer characteristic, it is necessary to:  have a good matching between the transistors from the circuit  proper choose of biasing voltage in repose  choose a prebiasing of the output stage in order to avoid the thermal embalmment
23 Circuit for avoiding the thermal embalmment () The biasing voltage of the output stage must be a temperaturedependent voltage (for example, the baseemitter voltage) v  Cesat Q  th ln( Q / S ) v v Q l v o  The diodeconnected transistors must be at the same temperature with the final transistors. n repose : v 0 QC QC Q Q BE + EB D th ln th Q S ln S SD Q  (  Cesat ) S SD S
24 Circuit for avoiding the thermal embalmment () ` Q Q 3 Q l v o th ln v + v BE EB v vbe 3 v CE 3 + Q S + ln Q S CE 3 ( ) + th ln S 3  Q S S S 3 +
25 Circuit for avoiding the thermal embalmment (3) Q Q 3 v Q Q v Q 4 Q  / BE / + BE BE 3 + / BE4 / Q th ln th ln S S Q
26 Circuit for avoiding the thermal embalmment (4) C Q 5 Q 3 BE th ln + C S BE + th BE 3 ln C S + EB4 th ln C 3 S 3 + th ln C 4 S4 v Q Q L C 3 C 4 C S 3 S S4 S Q 4 Q 6 v i  + max max + EC5sat EC6 sat BE 3 BE4
27 Circuit with overload protection () C Q 5 Q 3 Q Q 7 v + max BE7 Q L Q 4 v i Q 6 
28 Circuit with overload protection () C Q 5 Q Q Q 3 Q 7 v EB8 max L + max BE7 Q 8 Q 4 v i Q 6 
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