RIB. ELECTRICAL ENGINEERING Analog Electronics. 8 Electrical Engineering RIBR T7. Detailed Explanations. Rank Improvement Batch ANSWERS.


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1 8 Electrical Engineering RIBR T7 Session 089 S.No. : 9078_LS RIB Rank Improvement Batch ELECTRICL ENGINEERING nalog Electronics NSWERS. (d) 7. (a) 3. (c) 9. (a) 5. (d). (d) 8. (c) 4. (c) 0. (c) 6. (b) 3. (a) 9. (d) 5. (a). (a) 7. (c) 4. (c) 0. (b) 6. (b). (c) 8. (c) 5. (a). (c) 7. (a) 3. (d) 9. (c) 6. (b). (d) 8. (c) 4. (d) 30. (c) Detailed Explanations. (d) (6 m)(6 kω) 36 I 0 6 m 0 K I 0 6 m m 4 m I 0. (d) 00 k 0 k k 99 k
2 RIB8 EE nalog Electronics 9 Set, 0 R then F R 99k where ( ) 99k k so, Now, set k 0 k k 99 k then hence , 0 3. (a) 5 9 I L(max) z(min) 0 k i m 4. (c) For M to operate in saturation; dsi gs tn i 0 i lso, I D kn( gs ) ( ) tn kn gs tn gs gs 5 i 5 i 5 i > i i 6 i 3 Thus, maximum input that can be applied is 3.
3 0 Electrical Engineering 5. (a) The feedback element (R F ) is directly connected to both input and output. So, voltageshunt type of feedback. 6. (b) Since there is a D.C level shift in the output waveform, the circuit must be a clamper circuit and when the diode is conducting, the voltage at the output must be 5 as seen from the output waveform hence option (b) is correct. 7. (a) From the circuit it is clear that D will always be off. Thus kω 0 0 kω 0 kω (0 0.7) 0 kω 0 kω 8. (c) dt RC i t C 50 0 i t C.5 mf 9. (d) For the Hartly oscillator shown, L L 0. (b) For ve half cycle 0 ωt π L or 4 L 48 L L 48 µh L max 48 µh I B 0 sinωt 0k to produce sustained oscillations
4 RIB8 EE nalog Electronics I B 0sinωt D 0 kω I B sinωt m For ve half cycle π ωt π I B 0 sinωt 0k I B 0sinωt 0 kω 0 kω I B sinωt m form here I B sinωt m for all ωt R B I B B 0sinωt 0 kω 3 sinω t 0. (c) 0 0 R kω R kω R 3 50 kω R kω v 0 R 3 50 kω R kω v 0 C 0.0 µ F 0.0 µ F C 0.0 µ F 0.0 µ F figurei figureii alue of R corresponding to figurei is kω and value of R B is 5 kω. alue of R corresponding to figureii is 5kΩ and value of R B is kω. So, kω R 5 kω kω R B 5 kω f max R R C ( ) B
5 Electrical Engineering f max ( ) f max.7 khz. (d) ssume that the gain is very large i.e. v >> thus v for unbypassed R E and for large values of R E R E >> thus, the voltage gain of above circuit will become βrc gmrc re βrc v gmr β R E r βr r 3. (c) now, since β is very large thus, RC v R v 0k Ω kω 5 E E e E e 4 k 50 Ω Ω 0.5 b i b 50 Ω 50 Ω 50 Ω 50 Ω b 3 i b 4.3k and i b 00 for b k b and for b 6
6 RIB8 EE nalog Electronics Regulation Regulation 4.545% 00% 4. (c) Maximum power dissipation P Dmax Tjmax T 0 θ W (θ Thermal resistance) CE I C max P D max I C max (a) Base emitter loop.5 kω 500 kω I C I B IE kω R in 500 ki B 0.7 k (I B I C ) I C 00I B I E 0 I B from here I B 8.88 µ T T 6 β k Ω.38k Ω I I 8.8 C B R in ( β)r E.383k 0 k 0.38 kω 6. (b) Small signal circuit is i R G gs R D 7 kω gs 0 gs R D
7 4 Electrical Engineering gs i i R D W µ ncox I D m L v i R D (a) df f 0.% d 50, 000 d f f d β β 000 β 37.5 β Thus, f (c) Drawing the small signal model of the above circuit, we get R in in R r g π m π π Let R be the input resistance as seen in from point. Thus, to calculate R we can draw the diagram separately I π π R I r π gm
8 RIB8 EE nalog Electronics 5 9. (a) Thus, the value of the output voltage o in (R R ) o g m R rπ in g m D γ R eq kω i 0 eq eq R eq 6 3 kω. 9 i 0; as i > eq, D is ON and the voltage across the diode will be γ. γ i volts. 0. (c) 9 50 kω B I B 0.7 I B R B 0.5 m EC 4.7 kω E C 9 I C I B β 49(0.5) ( I E) m 0.49 m β m 0 µ 50 E I B R B EB (0.0) (50) 0.7. C EC P Q I C R C 9 (0.49)(4.7) (6.697 ) I C EC (0.49)(7.897) mw 3.87 mw
9 6 Electrical Engineering. (a) kω 0 kω i kω kω kω i 0 k Ω 0 k Ω k k 0 Ω Ω i 0( ) 0 i kω k Ω i i so, 0 i 0 i (0sinωt 0cosωt) m i (sinωt) m and i (cosωt) m. (c) We know β 0 sin( ωt 45 ) m β kω 0 Drawing the small signal equivalent, we get Iin R S in R R π π R L R C R eq R E in R I in R S (R R R eq ) in now, to calculate R eq, we can use another model I (I π )R E now, π I I R E I R E I β ( (β )R E )I I R eq π R E π R eq rπ ( β ) RE I
10 RIB8 EE nalog Electronics 7 R in R S [R R ( (β )R E ] putting the values R eq 0 kω kω R in kω 4.6 kω 5.6 kω 3. (d) Since the two port network is symmetric thus converting it into T network we get the circuit as shown below. 0 kω 0 kω I 3 i kω I I kω I 4 I i I k Ω 0 i and I 3 kω i and I 4 I I 3 kω 0 i or, i 0 4. (d) For S < 0 ; Diode is ON, and the positive terminal of opamp is forced to O. 0 S For S > 0; Diode is off and the positive terminal of opamp now follows S since no current flows in resistor, so must follow S. 0 S 5. (d) Let us assume M is in saturation I D W µ n Cox ( gs Th) 00 (0.36) µ L 0.8 I D 00 µ Now, D DD R D I D 0.8 DS ssumption is correct when g.0 s
11 8 Electrical Engineering 06.7 D Drain voltage changes by 34 m. I D 6. (b) Current through photodiode I (0.8) (0) m m I C β I E kω I I 0 I o kω ref I C I 8 m I E ( β ) IC 8.m β 80 β BE 0.7 so, I 0 kω 0.7 m I 0 I E I 8. ( 0.7) m 8.8 m 7. (c) knid m/ now, drawing the T equivalent model, we have R sig /g i m o sig i 0 R D R L i and out sig R gm sig ( R R ) D L R g m sig sig
12 RIB8 EE nalog Electronics 9 8. (c) out gm( RD RL) out sig g R out m sig ( 0 0 ) 0 0 m R 4R i R i R 4 i 4 i 8 i gain i 8 9. (c) MOS T serve as drain resistance for T DD DD T R out out out in T in T Calculating R out of T I x gs gs x pplying KCL at node, I x gs gs x Thus x I x g m R out for transistor T in gs gs R out out out gs R out
13 0 Electrical Engineering gs out in v in R out gm ( R g out m ) 30. (c) CC 0.5 m I 0.5 m Using current mirror concept, For large β, I I ref so, I y ( ) m I x ( ) m I x I y (0.5) 5 m.5 m
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