ECE 304: Design Issues for Voltage Follower as Output Stage S&S Chapter 14, pp

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Rudolf Shaw
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1 ECE 34: Design Issues for oltage Follower as Output Stage S&S Chapter 14, pp Introduction The voltage follower provides a good buffer between a differential amplifier and a load in two ways: 1. It reduces the Qpoint dependence of the differential amplifier upon the load because the voltage follower draws only a small DC base current from the diff amp at the Qpoint,. It presents a large ac smallsignal impedance to the differential amplifier, which has much less effect on the smallsignal voltage gain of the differential amplifier than a direct connection to the load. Criteria Here we want to examine the voltage follower in more detail as an output stage. There are six criteria for the quality of an output stage that we want to examine: 1. What is the maximum output swing possible in both the and the directions?. How linear is the output stage; that is, how much distortion is produced? 3. How much drive current can the output stage provide to its load? 4. How efficient is the output stage; that is, how much power is wasted? 5. What is the Thevenin resistance of the output stage? 6. What is the input resistance of the voltage follower stage? Let s begin with a particular circuit, as shown in Figure 1. Transient Analysis 1. DC {_DC} SIN {_S} 1kHz P {_CC} 8.615mA N mA 8.615uA {R_S} 15.5mA {I_M} Q3 {_CC} 8.615p P mA Q mA m mA Q PARAMETERS: R_S 1u R_L 1 R_M 1u _CC 1 _DC _S 1 I_M 15.5mA C_L 1pF mA {R_L} OUT {C_L} FIGURE 1 oltagefollower output stage. 1. N.model NPN (Is1fA Bf1) Unpublished work /13/5 J R Brews Page 1 /14/5

2 1 (R_L1,15 m) (558.3m,1.8454m) (R_L3,4.56) (R_L1k,9.95) (3.936,4.597) (9.49,9.98) (OUT) _DC FIGURE OUT vs. IN DC voltage transfer curves for several values of load resistance R L. For smaller values of R L the output voltage cannot swing very far negative, e.g. for R L 3Ω, OUT cannot go below OUT POINT 1: OUTPUT SWING We can examine Point 1 in the list of quality issues by looking at the DC voltage transfer curve of the stage shown in Figure. We see that for lower R L values the output voltage has a limited negative value. As shown in Figure 3, by running PSPICE for negative voltage input we see the reason for this limit on negative output swing pA Transient Analysis 1. DC {_DC} SIN {_S} 1kHz P {_CC} A 15.5mA mA {I_M} Q3 {R_S} N {_CC} P pA Q pA 15.mA Q PARAMETERS: mA R_S 1u R_L 1 R_M 1u _CC 1 _DC 1 _S 1 I_M 15.5mA C_L 1pF {R_L} OUT {C_L} 1. N FIGURE 3 Qpoint values for a large negative IN..model NPN (Is1fA Bf1) We see from Figure 3 that Q1 is cut off, and the current sourced by the load R L all goes through the current mirror transistor Q. Because the BE of Q is the same as that of Q3, which is set by the reference current I_M15.5 ma, it is not possible for Q to draw a current higher than I C (Q) 15. ma. Therefore, the negative maximum OUT is restricted by the condition OUT /R L 15. ma and OUT is limited in value to OUT 15.mA x R L 4.56 for R L 3Ω, and OUT.15 m for R L 1Ω. Unpublished work /13/5 J R Brews Page /14/5

3 To allow more negative output voltages we must increase the DCbias current of the current mirror. Larger bias current implies more power consumption, heating of the transistors, and possible thermal runaway. POINT : LINEARITY To examine Point in the quality issues, we can look at the slope of the transfer curve, which for an ideal follower would be unity. In Figure 4 the derivative of the transfer curve is shown. 1. (9.491,R_L1k) ( ,R_L3) ( m,R_L1) D((OUT)) _DC FIGURE 4 Derivative of DC transfer curve for several values of R L. We see from Figure 4 that only for R L 1kΩ is a nearly unity gain found over an extended voltage range. If we are to extend the operation of this output stage to lower values of R L we will have to increase the DC bias current provided by the current mirror. POINT 3: DRIE CURRENT TO THE LOAD Point 3 of the quality issues has been partly addressed: we have seen that in the negative swing direction the DC current through the current mirror limits the current that can be drawn through the load resistor. However, for capacitive loads this limit on the maximum current also limits the ability of the output voltage to follow the input voltage, as shown in Figure (.76) CL5uF CLuF (7.8m) (C_L1nF,4.16) 5. s.4ms.8ms 1.ms 1.6ms.ms (OUT) Time FIGURE 5 Output voltage for several capacitor loads. The input signal is 3.5 amplitude at 1kHz. The load resistor is R L 3 Ω. The output follows the input up to about C L.1µF, but above this value (e.g. for C L 5µF) the output cannot follow the input on the downward swing. Looking at the current needed to discharge the capacitor, we can see the reason for the failure to follow on the downswing. If υ O (t) sin(ωt), we have the current through the capacitor as dυ ι O C (t) C L C L ω o cos( ωt), dt Unpublished work /13/5 J R Brews Page 3 /14/5

4 which says that the maximum current needed by the capacitor is I c ωc L πc L /T, where Tperiod of applied signal. For 3.5 and T1ms, I c. x 1 4 C L 44 ma for C L µf. We have seen in Figure 3 that the maximum current that can be drawn from the capacitor is 15. ma, even if the resistor R_L carries no current itself. That is, C L µf is a lot larger than the maximum capacitor this output stage can drive. To allow this output stage to drive a large capacitor as load, we have to make the current mirror DCbias current larger than I CQ πc L /T. POINT 4: EFFICIENCY The useful power is the signal power actually delivered to the load, and does not include any DC power delivered. Taking the output voltage as υ O (t) OQ sin(ωt) (i.e. assuming no distortion) the average useful power is T 1 1 T 1 cos(4πt / T) P ( t / T) dt dt L sin π, T R L T R L R L which for 3.5 swing and R L 3 Ω provides P L.4 mw. To obtain the result from PSPICE, we can plot an integral over several cycles of ι O (t)υ O (t) and subtract the DC contribution. The result is shown in Figure 6. Using 1 cycle, from Figure 6 we find P L 1.7 mw. The DC contribution is (see Figure 7) PDC (7.8m) /3 Ω 1.73 mw. Hence the useful power is mw. 5m 5m (1.m,1.7m) s.4ms.8ms 1.ms 1.6ms.ms S(I(RL)*(RL:))/1m Time FIGURE 6 PSPICE plot of the integral of the instantaneous acdc load power over time, t <p L (t)> AE t ι υ ; the power consumed by the load is the difference O (t) O (t)dt between the yvalues at any two points 1 ms apart (1 cycle) divided by the period T1ms. In PSPICE S() denotes integral The power consumed by the circuit is that contributed by the three DC sources and the signal source. The signal source input is small because the current through the signal source is the base current of Q1, which is much smaller than the collector current. Therefore the input power from the signal source can be neglected. Because the time average of a sinusoid over one cycle is zero, the total power contributed by the three DC sources is the same as their DC power alone. Using the Qpoint data from Figure 7, for the positive source, the power contribution is 1.67mA x 1.167W, compared with.17w from PSPICE in Figure 8. For the negative source the current is 3.7mA or a power contribution of.37w, the same as PSPICE in Figure 8. The power delivered by the DC current source is 15.5mA W. This means the efficiency of this amplifier for 3 input is mw/( ) mw 3.4%! Almost all the energy is used to heat the transistors. Unpublished work /13/5 J R Brews Page 4 /14/5

5 PARAMETERS: mA DC {_DC} P {_CC} 15.5mA mA 16.7uA {R_S} N {_CC} 16.7p 9.75 P mA Q1 1.79mA R_S 1u R_L 3 R_M 1u _CC 1 _DC _S 3.5 I_M 15.5mA C_L 1pF 7.8m OUT Transient Analysis SIN {_S} 1kHz {I_M} Q mA Q.43mA {R_L} {C_L} 1. N FIGURE 7 The Qpoint currents and voltages for the case R L 1kΩ..model NPN (Is1fA Bf1) 4m (1.m,37.m) m (1.m,143.8m) (1.m,17.m) s.4ms.8ms 1.ms 1.6ms.ms S(I(IM)*(IM))/1ms S(I(N))*1/1ms S(I(P))*1/1ms Time FIGURE 8 The power integrals for the two DC voltage sources P and N, and the mirror reference current IM divided by the period T1 ms; we can read the power off the diagram at 1ms by using the cursor to label the value at 1ms. The current through N is I C, so an approximate formula for the efficiency of this stage is η RL ICQ 1 ( ) P N. When the input goes large and negative so Q1 cuts off, the largest I possible negative value of is I CQ R L making the approximate efficiency CQR η L. To ( P N ) increase the efficiency we can increase I CQ R L, but the largest negative value of possible is N υ CE (sat;q) or (max) N υ CE (sat) N.. Hence the maximum efficiency with N P is η %. Unpublished work /13/5 J R Brews Page 5 /14/5

6 POINT 5: OUTPUT R TH OF THE STAGE. OUTPUT RESISTANCE OF FOLLOWER PLUS DRIER R S r π I X X X RM β 1 I X X X R β M β 1 r O X IX X R M I X X RM R M X FIGURE 9 Smallsignal circuit to find Thevenin resistance of driver plus follower Using KL through r π we find EQ. 1 X X IX R M X ( r RS ) 1 π. β Collecting terms, we find that for the voltage follower the output resistance is EQ. X r RS RTh // RM // I π X 1, β with R M output resistance of the current mirror, and r E r π /(β1). ADANTAGES OF LOW THEENIN RESISTANCE When there is a capacitive component of load C L, we find from Figure 1 that the output voltage is related to the input voltage as Th R L 1 R L R Th 1 jωc L (R Th // R L ) Unpublished work /13/5 J R Brews Page 6 /14/5

7 OUT PARAMETERS: AC Sweep {Rth} _THE 1 {CL} {RL} Rth 1k RL 1k CL 1uF FIGURE 1 Thevenin equivalent circuit of voltage follower with capacitive and resistive components of load. That is, at low frequencies the usual voltage divider expression applies, and a low R Th is advantageous for getting most of the input voltage into the load. At higher frequencies the output voltage falls off, with the corner frequency ω C at ω C C L (R Th //R L ) 1. When ωω C, the gain has a magnitude 1/ 1/ R L 1 R L 1 1 R L Th R L R Th 1 [ ωccl (R Th // R L )] R L R Th 1 1 1/ R L R Th i.e. a magnitude down from its maximum, or log 1 ( ) 3dB down. We see that a low R Th has the advantage of pushing the corner frequency to high values, which means the circuit responds well to fast signals. 1. (Rth1,99.1m) (689.5,544.6m) (16.1K,7.9m) (Rth3,769.m).5 (Rth1k,5.m) (318.4,354.m) 1.Hz 1Hz 1Hz 1.KHz 1KHz 1KHz 1.MHz 1MHz 1MHz (OUT) Frequency FIGURE 11 Frequency rolloff of gain of voltage follower for R L 1kΩ, C L 1 µf, and various values for R Th In Figure 11 the corner frequency f C ω C /(π) is marked. It varies approximately as 1/(R Th //R L ) as expected. Lower R Th wider bandwidth and larger output voltage at frequencies below the corner frequency. Unpublished work /13/5 J R Brews Page 7 /14/5

8 IX Point 6: Input impedance A driving stage like a differential amplifier may have very high output impedance. For example, the gain of many amplifiers cannot be obtained without high output impedance. In such cases, the Thevenin equivalent of the drive stage will have a large Thevenin resistance. Suppose we represent the drive stage alone by Figure 1, attached to a lowimpedance load. An unfavorable voltage divider will result when the load impedance is small compared to the Thevenin resistance of the drive stage. To fix this problem, a voltage follower can be placed between the drive stage and the load to magnify the load seen by the driver (reflection rule). In this way, a more favorable voltage divider results from the driver s viewpoint. r π r O X e βi X e I X βi e X e RM R M R L e RL C L jωc L e FIGURE 1 Smallsignal circuit for input resistance Using Figure 1, KCL at the emitter provides EQ I β ω e X( 1) e j CLe, RM RL 1 Rp // jωcl where the parallel resistance R p is EQ. 4 ( R // R // r ) R p M L O. Ohm s law across r π provides EQ. 5 e X I X r π. Substituting for e from EQ. 5 into EQ. 3 we find the input impedance is EQ. 6 X 1 Zin rπ ( β 1) Rp //. IX jωcl At low frequencies, Z in is just the increased input resistance of the reflection rule. The frequency dependence of Z in doesn t look too encouraging because C L R p is a rather long time constant, suggesting slow performance. However, if we attach the driver to Z in as shown in Figure 13, we will find the voltage at the input, in, is given by EQ. 7 below. Unpublished work /13/5 J R Brews Page 8 /14/5

9 EQ. 7 in ( β 1) S RS ( β ( re Rp ) 1) ( r R ) E r 1 jωc π L Rp // β 1 p R r 1 jωc R // S π L p β 1 EQ. 7 shows the favorable voltage division expected from the reflection rule at low frequencies, and, for R S >> r π, a simple rolloff frequency dependence governed by C L and the resistance as seen by C L looking back into the voltage follower, in parallel with R L. Compare with EQ.. Because of the reduced resistance due to division by β1, the corner is at a higher frequency than if R S were directly connected to the C L R L load: bandwidth is improved, in agreement with the output argument made earlier using Figure 1. R S IN in S Z in FIGURE 13 Input divider with voltage driver with resistance R S, and the F represented by its smallsignal input impedance Z in from EQ. 6; this circuit leads to EQ RS1k RS1k RSrPI RS1 1.Hz 1Hz 1KHz 1.MHz 1MHz 1GHz 1.THz (IN_SS) Frequency FIGURE 14 Behavior of input impedance for several values of R S ; for R S >> r π we have a simple rolloff behavior due to the pole in the denominator of EQ. 7, while the zero in the numerator of EQ. 7 intervenes to stop rolloff at a higher frequency, producing a step in the impedance that becomes smaller and smaller as R S is reduced From the driver s viewpoint the combined voltage follower and its load together appear as a load with large resistance component, which is favorable to placing most of the voltage across the load, and a large bandwidth. Unpublished work /13/5 J R Brews Page 9 /14/5

Homework Assignment 08

Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance