EEC 118 Lecture #4: CMOS Inverters. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

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1 EEC 118 Lecture #4: CMOS Iverters ajeeva Amirtharajah Uiversity of Califoria, Davis Jeff Parhurst Itel Cororatio

2 Outlie eview: Iverter Trasfer Characteristics Lecture 3: Noise Margis, ise & Fall Times, Iverter Delay CMOS Iverters: abaey 1.3., 5 (Kag & Leblebici, ad ) Amirtharajah/Parhurst, EEC 118 Srig 010 3

3 eview: Iverter oltage Trasfer Curve oltage trasfer curve (TC): lot of outut voltage out vs. iut voltage i i Iverter out dd out ideal actual Ideal digital iverter: Whe i=0, out=dd Whe i=dd, out=0 0 i dd Shar trasitio regio Amirtharajah/Parhurst, EEC 118 Srig 010 4

4 eview: Actual Iverter Outut Levels OH ad OL rereset the high ad low outut voltages of the iverter OH OH = outut voltage whe i = 0 ( Outut High) out OL = outut voltage whe i = 1 ( Outut Low) OL 0 i dd Ideally, OH = dd OL = 0 Amirtharajah/Parhurst, EEC 118 Srig 010 5

5 eview: OL ad OH I trasfer fuctio terms: OL = f( OH ) OH out OH = f( OL ) f = iverter trasfer fuctio OL OL i OH dd Differece ( OH - OL ) is the voltage swig of the gate Full-swig logic swigs from groud to dd Other families with smaller swigs Amirtharajah/Parhurst, EEC 118 Srig 010 6

6 eview: Iverter Switchig Threshold Iverter switchig threshold: OH out=i Poit where voltage trasfer curve itersects lie out=i out OL i M dd eresets the oit at which the iverter switches state Normally, M dd/ Sometimes other thresholds desirable Amirtharajah/Parhurst, EEC 118 Srig 010 7

7 TC Mathematical Defiitios OH is the outut high level of a iverter OH = TC( OL ) OL is the outut low level of a iverter OL = TC( OH ) M is the switchig threshold M = IN = OUT IH is the lowest iut voltage for which the outut will be the iut (worst case 1 ) dtc( IH )/d IH = -1 IL is the highest iut voltage for which the outut will be the iut (worst case 0 ) dtc( IL )/d IL = -1 Amirtharajah/Parhurst, EEC 118 Srig 010 8

8 Noise Margi ad Delay Defiitios NM L is the differece betwee the highest accetable 0 ad the lowest ossible 0 NM L = IL OL NM H is the differece betwee the lowest accetable 1 ad the highest ossible 1 NM H = OH IH t PHL is the roagatio delay from the 50% oit of the iut to the outut whe the outut goes from high to low t PLH is the roagatio delay from the 50% oit of the iut to the outut whe the outut goes from low to high t P is the average roagatio delay t is the rise time (usually 10% to 90%) t F is the fall time (usually 90% to 10%) Amirtharajah/Parhurst, EEC 118 Srig 010 9

9 CMOS Iverter Comlemetary NMOS ad PMOS devices I steady-state, oly oe device is o (o static ower cosumtio) i i=1: NMOS o, PMOS off out= OL = 0 i=0: PMOS o, NMOS off out= OH = dd Ideal OL ad OH! atioless logic: outut is ideedet of trasistor sizes i steady-state dd Gd out Amirtharajah/Parhurst, EEC 118 Srig

10 CMOS Iverter: TC PMOS NMOS i =4 Drai curret I DS i =3 i = i =1 dd out out = DS dd 0 1 i 3 4 Outut goes comletely to dd ad Gd Shar trasitio regio Amirtharajah/Parhurst, EEC 118 Srig

11 CMOS Iverter Oeratio NMOS trasistor: Cutoff if i < TN Liear if out < i TN Saturated if out > i TN PMOS trasistor i out Cutoff if ( i - ) < TP i < + TP Liear if ( out - )> i - - TP out > i - TP Sat. if ( out - )< i - - TP out < i - TP Amirtharajah/Parhurst, EEC 118 Srig 010 1

12 CMOS Iverter TC: Device Oeratio P liear N cutoff P cutoff N liear P liear N sat P sat N sat P sat N liear Amirtharajah/Parhurst, EEC 118 Srig

13 CMOS Iverter TC: Device Sizig out = =5 Icrease W of PMOS icreases TC moves to right Icrease W of NMOS icreases TC moves to left =0. For M = / = W W i Amirtharajah/Parhurst, EEC 118 Srig

14 Effects of M adjustmet esult from chagig / ratio: Iverter threshold M / ise ad fall delays uequal Noise margis ot equal easos for chagig iverter threshold Wat a faster delay for oe tye of trasitio (rise/fall) emove oise from iut sigal: icrease oe oise margi at exese of the other Iterfacig other tyes of logic (with differet swigs) Amirtharajah/Parhurst, EEC 118 Srig

15 CMOS Iverter: IL Calculatio KCL (NMOS saturatio, PMOS liear): ( GS, T 0, ) = ( GS, T 0, ) DS, [ ] Differetiate ad set dout/di to 1 DS, ( ) = ( )( ) ( ) i T 0, [ ] i ( ) ( ) d out dout = + ( ) ( ) i T 0, i T 0, d T 0, ( ) = ( + ) i out out IL T0, out IL T0, out out d i IL = out + T 0, + T 0, 1+ Solve simultaeously with KCL to fid IL = Amirtharajah/Parhurst, EEC 118 Srig

16 KCL: CMOS Iverter: IH Calculatio [ ( ) ] = ( ) GS, T 0, DS, DS, Differetiate ad set dout/di to 1 GS, [ ( ) ] = ( ) i T 0, out out i T 0, T 0, ( ) ( ) out out + = i d d T 0, out out i di di IH + = ( ) ( ) = out + IH T 0, + T0, 1+ IH ( + ) out T 0, = T0, T 0, Solve simultaeously with KCL to fid IH Amirtharajah/Parhurst, EEC 118 Srig

17 CMOS Iverter: M Calculatio KCL (NMOS & PMOS saturated): ( ) = ( ) GS, T 0, GS, T 0, ( ) = ( ) i T 0, i T 0, Solve for M = i = out M = T 0, ( + ) 1 T 0, = Amirtharajah/Parhurst, EEC 118 Srig

18 CMOS Iverter: Achievig Ideal M TH = T 0, + 1 Ideally, M = / 1+ ( + ) 1 T 0,, ideal = = + + T 0, T 0, Assumig T0, = T0,, W L μ = W μ L, ideal =1.5 Amirtharajah/Parhurst, EEC 118 Srig

19 CMOS Iverter: IL ad IH for Ideal M Assumig T0, =- T0,, ad = 1, 1 IL = IH = 5 8 IL ( 3 ) T 0 ( ) + = IH T 0 NM = = L IL OL IL NM = = = H OH IH IH IL Amirtharajah/Parhurst, EEC 118 Srig 010 0

20 Next Time: AC Characteristics & Fabricatio MOS Fabricatio CMOS Iverters AC Characteristics: Desigig for seed Amirtharajah/Parhurst, EEC 118 Srig 010 1

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